32Gb: x4, x8 TwinDie DDR4 SDRAM

Description

TwinDie™ 1.2V DDR4 SDRAM

MT40A8G4 – 256 Meg x 4 x 16 Banks x 2 Ranks
MT40A4G8 – 128 Meg x 8 x 16 Banks x 2 Ranks

Description Options Marking

• Configuration
The 32Gb (TwinDie™) DDR4 SDRAM uses – 256 Meg x 4 x 16 banks x 2 ranks 8G4
Micron’s 16Gb DDR4 SDRAM die (essentially two – 128 Meg x 8 x 16 banks x 2 ranks 4G8
ranks of the 16Gb DDR4 SDRAM). Refer to Micron’s • FBGA package (Pb-free)
16Gb DDR4 SDRAM data sheet for the specifications – 78-ball FBGA BAF
not included in this document. Specifications for base (10.5mm x 11mm x 1.2mm) Die
part number MT40A4G4 correlate to TwinDie manu- Rev :B
facturing part number MT40A8G4; specifications for • Timing – cycle time1
base part number MT40A2G8 correlate to TwinDie – 0.625ns @ CL = 22 (DDR4-3200) -062E
manufacturing part number MT40A4G8. • Self refresh
Features – Standard None
• Uses 16Gb Micron die • Operating temperature
• Two ranks (includes dual CS#, ODT, and CKE balls) – Commercial (0°C ≤ T C ≤ 95°C) None
• Each rank has 4 groups of 4 internal banks for con- • Revision :B
current operation Note: 1. CL = CAS (READ) latency.
• VDD = V DDQ = 1.2V (1.14–1.26V)
• 1.2V V DDQ-terminated I/O
• JEDEC-standard ball-out
• Low-profile package
• TC of 0°C to 95°C
– 0°C to 85°C: 8192 refresh cycles in 64ms
– 85°C to 95°C: 8192 refresh cycles in 32ms

Table 1: Key Timing Parameters

Data Rate
1 tAA tRCD tRP
Speed Grade (MT/s) Target CL-nRCD-nRP (ns) (ns) (ns)
-062E 3200 22-22-22 13.75 13.75 13.75

Note: 1. Refer to the Speed Bin Tables for additional details.

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Products and specifications discussed herein are subject to change by Micron without notice.
 32Gb: x4, x8 TwinDie DDR4 SDRAM
Description

Table 2: Addressing

Parameter 8192 Meg x 4 4096 Meg x 8

Configuration 256 Meg x 4 x 16 banks x 2 ranks 128 Meg x 8 x 16 banks x 2 ranks
Bank group address BG[1:0] BG[1:0]
Bank count per group 4 4
Bank address in bank group BA[1:0] BA[1:0]
Row address 256K A[17:0] 128K A[16:0]
Column address 1K A[9:0] 1K A[9:0]

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 32Gb: x4, x8 TwinDie DDR4 SDRAM
Important Notes and Warnings

Important Notes and Warnings

Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document,
including without limitation specifications and product descriptions. This document supersedes and replaces all
information supplied prior to the publication hereof. You may not rely on any information set forth in this docu-
ment if you obtain the product described herein from any unauthorized distributor or other source not authorized
by Micron.
Automotive Applications. Products are not designed or intended for use in automotive applications unless specifi-
cally designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distrib-
utor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims,
costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
product liability, personal injury, death, or property damage resulting directly or indirectly from any use of non-
automotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and con-
ditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron
products are not designed or intended for use in automotive applications unless specifically designated by Micron
as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to in-
demnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys'
fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage
resulting from any use of non-automotive-grade products in automotive applications.
Critical Applications. Products are not authorized for use in applications in which failure of the Micron compo-
nent could result, directly or indirectly in death, personal injury, or severe property or environmental damage
("Critical Applications"). Customer must protect against death, personal injury, and severe property and environ-
mental damage by incorporating safety design measures into customer's applications to ensure that failure of the
Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron
component for any critical application, customer and distributor shall indemnify and hold harmless Micron and
its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims,
costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
product liability, personal injury, or death arising in any way out of such critical application, whether or not Mi-
cron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the
Micron product.
Customer Responsibility. Customers are responsible for the design, manufacture, and operation of their systems,
applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAIL-
URE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE
WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR
PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included
in customer's applications and products to eliminate the risk that personal injury, death, or severe property or en-
vironmental damages will result from failure of any semiconductor component.
Limited Warranty. In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential
damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such damages are based on tort, warranty,
breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly
authorized representative.

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 32Gb: x4, x8 TwinDie DDR4 SDRAM
Functional Description

Functional Description
The TwinDie DDR4 SDRAM is a high-speed, CMOS dynamic random access memory
device internally configured as two 16-bank DDR4 SDRAM devices.
Although each die is tested individually within the dual-die package, some TwinDie test
results may vary from a like-die tested within a monolithic die package.
The DDR4 SDRAM uses a double data rate architecture to achieve high-speed opera-
tion. The double data rate architecture is an 8n-prefetch architecture with an interface
designed to transfer two data words per clock cycle at the I/O balls. A single read or
write access consists of a single 8n-bit-wide, one-clock-cycle data transfer at the inter-
nal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers
at the I/O balls.
The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for
use in data capture at the DDR4 SDRAM input receiver. DQS is center-aligned with data
for WRITEs. The read data is transmitted by the DDR4 SDRAM and edge-aligned to the
data strobes.
Read and write accesses to the DDR4 SDRAM are burst-oriented. Accesses start at a se-
lected location and continue for a programmed number of locations in a programmed
sequence. Operation begins with the registration of an ACTIVATE command, which is
then followed by a READ or WRITE command. The address bits registered coincident
with the ACTIVATE command are used to select the bank and row to be accessed. The
address bits (including CSn#, BAn, and An) registered coincident with the READ or
WRITE command are used to select the rank, bank, and starting column location for the
burst access.
This data sheet provides a general description, package dimensions, and the package
ballout. Refer to the Micron monolithic DDR4 data sheet for complete information re-
garding individual die initialization, register definition, command descriptions, and die
operation.

Industrial Temperature
The industrial temperature (IT) option, if offered, requires that the case temperature
not exceed –40°C or 95°C. JEDEC specifications require the refresh rate to double when
TC exceeds 85°C; this also requires use of the high-temperature self refresh option. Addi-
tionally, ODT resistance, IDD values, some IDD specifications and the input/output im-
pedance must be derated when T C is < 0°C or > 95°C. See the DDR4 monolithic data
sheet for details.

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 32Gb: x4, x8 TwinDie DDR4 SDRAM
Functional Block Diagrams

Functional Block Diagrams

Figure 1: Functional Block Diagram (256 Meg x 4 x 16 Banks x 2 Ranks)

Rank 1
(256 Meg x 4 x 16 banks)

Rank 0
(256 Meg x 4 x 16 banks)

CS0#
CS1# PAR
CK CKE0
CKE1 TEN
CK# A[17,13:0],
ODT0
ODT1 RESET ACT_n,
ZQ
WE_n/A14,
ALERT_n
CAS_n/A15,
RAS_n/A16, DM
BA[1:0], DQ[3:0]
BG[1:0] DQS, DQS#

Figure 2: Functional Block Diagram (128 Meg x 8 x 16 Banks x 2 Ranks)

Rank 1
(128 Meg x 8 x 16 banks)

Rank 0
(128 Meg x 8 x 16 banks)

CS0#
CS1# PAR CK
CKE0
CKE1 TEN CK# A[13:0],
RESET ZQ ACT_n, ODT0
ODT1
ALERT_n WE_n/A14,
CAS_n/A15,
RAS_n/A16,
BA[1:0], TDQS#
BG[1:0] DQ[7:0]
DBI/DM/TDQS
DQS, DQS#

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 32Gb: x4, x8 TwinDie DDR4 SDRAM
Electrical Specifications – Leakages

Electrical Specifications – Leakages

Table 3: Input and Output Leakages

Symbol Parameter Min Max Units Notes

IIN Input leakage current -4 4 µA 1
Any input 0V ≤ VIN ≤ VDD,
VREF pin 0V ≤ VIN ≤ 1.1V
(All other pins not under test = 0V)
IVREFCA VREF supply leakage current -4 4 µA 2
(All other pins not under test = 0V)
IZQ Input leakage on ZQ pin -100 20 µA
ITEN Input leakage on TEN pin -12 20 µA
IOZpd Output leakage: VOUT = VDDQ – 20 µA 3
IOZpu Output leakage: VOUT = VSSQ -100 – µA 3, 4

Notes: 1. Any input 0V < VIN < 1.1V

2. VREFCA = VDD/2, VDD at valid level.
3. DQ are disabled.
4. ODT is disabled with the ODT input HIGH.

Temperature and Thermal Impedance

It is imperative that the DDR4 SDRAM device’s temperature specifications, shown in
the following table, be maintained in order to ensure the junction temperature is in the
proper operating range to meet data sheet specifications. An important step in main-
taining the proper junction temperature is using the device’s thermal impedances cor-
rectly. The thermal impedances listed in Table 5 (page 7) apply to the current die re-
vision and packages.
Incorrectly using thermal impedances can produce significant errors. Read Micron
technical note TN-00-08, “Thermal Applications,” prior to using the values listed in the
thermal impedance table. For designs that are expected to last several years and require
the flexibility to use several DRAM die shrinks, consider using final target theta values
(rather than existing values) to account for increased thermal impedances from the die
size reduction.
The DDR4 SDRAM device’s safe junction temperature range can be maintained when
the T C specification is not exceeded. In applications where the device’s ambient tem-
perature is too high, use of forced air and/or heat sinks may be required to satisfy the
case temperature specifications.

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 32Gb: x4, x8 TwinDie DDR4 SDRAM
Electrical Specifications – Leakages

Table 4: Thermal Characteristics

Notes 1–3 apply to entire table
Parameter Symbol Value Units Notes
Operating temperature TC 0 to 85 °C
0 to 95 °C 4

Notes: 1. MAX operating case temperature TC is measured in the center of the package, as shown
below.
2. A thermal solution must be designed to ensure that the device does not exceed the
maximum TC during operation.
3. Device functionality is not guaranteed if the device exceeds maximum TC during
operation.
4. If TC exceeds 85°C, the DRAM must be refreshed externally at 2x refresh, which is a 3.9µs
interval refresh rate. The use of self refresh temperature (SRT) or automatic self refresh
(ASR), if available, must be enabled.

Figure 3: Temperature Test Point Location

Test point

Length (L)

0.5 (L)

0.5 (W)
Width (W)

Table 5: Thermal Impedance

Θ JA (°C/W) Θ JA (°C/W) Θ JA (°C/W)

Airflow = Airflow = Airflow =
Package Substrate 0m/s 1m/s 2m/s Θ JB (°C/W) Θ JC (°C/W) Notes
78-ball Rev B "BAF" Low 48.8 36.5 32.5 NA 4.6 1
conductivity
High 29.7 23.9 22.2 12.8 NA
conductivity

Note: 1. Thermal resistance data is based on a typical number.

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 32Gb: x4, x8 TwinDie DDR4 SDRAM
Electrical Characteristics – AC and DC Output Measurement
Levels

Electrical Characteristics – AC and DC Output Measurement Levels

Single-Ended Outputs

Table 6: Single-Ended Output Levels

Parameter Symbol DDR4-1600 to DDR4-3200 Unit

DC output high measurement level (for IV curve linearity) VOH(DC) 1.1 × VDDQ V
DC output mid measurement level (for IV curve linearity) VOM(DC) 0.8 × VDDQ V
DC output low measurement level (for IV curve linearity) VOL(DC) 0.5 × VDDQ V
AC output high measurement level (for output slew rate) VOH(AC) (0.7 + 0.15) × VDDQ V
AC output low measurement level (for output slew rate) VOL(AC) (0.7 - 0.15) × VDDQ V

Note: 1. The swing of ±0.15 × VDDQ is based on approximately 50% of the static single-ended
output peak-to-peak swing with a driver impedance of RZQ/7 and an effective test load
of 50Ω to VTT = VDDQ.
Using the same reference load used for timing measurements, output slew rate for fall-
ing and rising edges is defined and measured between V OL(AC) and V OH(AC) for single-
ended signals.

Table 7: Single-Ended Output Slew Rate Definition

Measured
Description From To Defined by
Single-ended output slew rate for rising edge VOL(AC) VOH(AC) [VOH(AC) - VOL(AC)]/ΔTRse
Single-ended output slew rate for falling edge VOH(AC) VOL(AC) [VOH(AC) - VOL(AC)]/ΔTFse

Figure 4: Single-ended Output Slew Rate Definition

TRse

VOH(AC)
Single-Ended Output Voltage (DQ)

VOL(AC)

TFse

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 32Gb: x4, x8 TwinDie DDR4 SDRAM
Electrical Characteristics – AC and DC Output Measurement
Levels

Table 8: Single-Ended Output Slew Rate

For RON = RZQ/7
DDR4-1333 to DDR4-3200
Parameter Symbol Min Max Unit
Single-ended output slew rate SRQse 2 7 V/ns

Notes: 1. SR = slew rate; Q = query output; se = single-ended signals

2. In two cases a maximum slew rate of 12V/ns applies for a single DQ signal within a byte
lane:
• Case 1 is defined for a single DQ signal within a byte lane that is switching into a cer-
tain direction (either from HIGH-to-LOW or LOW-to-HIGH) while all remaining DQ sig-
nals in the same byte lane are static (they stay at either HIGH or LOW).
• Case 2 is defined for a single DQ signal within a byte lane that is switching into a cer-
tain direction (either from HIGH-to-LOW or LOW-to-HIGH) while all remaining DQ sig-
nals in the same byte lane are switching into the opposite direction (from LOW-to-
HIGH or HIGH-to-LOW, respectively). For the remaining DQ signal switching into the
opposite direction, the standard maximum limit of 7 V/ns applies.

Differential Outputs

Table 9: Differential Output Levels

Parameter Symbol DDR4-1600 to DDR4-3200 Unit

AC differential output high measurement level (for output slew VOH,diff(AC) 0.3 × VDDQ V
rate)
AC differential output low measurement level (for output slew VOL,diff(AC) –0.3 × VDDQ V
rate)

Note: 1. The swing of ±0.3 × VDDQ is based on approximately 50% of the static single-ended out-
put peak-to-peak swing with a driver impedance of RZQ/7 and an effective test load of
50Ω to VTT = VDDQ at each differential output.
Using the same reference load used for timing measurements, output slew rate for fall-
ing and rising edges is defined and measured between V OL,diff(AC) and V OH,diff(AC) for dif-
ferential signals.

Table 10: Differential Output Slew Rate Definition

Measured
Description From To Defined by
Differential output slew rate for rising edge VOL,diff(AC) VOH,diff(AC) [VOH,diff(AC) - VOL,diff(AC)]/ΔTRdiff
Differential output slew rate for falling edge VOH,diff(AC) VOL,diff(AC) [VOH,diff(AC) - VOL,diff(AC)]/ΔTFdiff

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 32Gb: x4, x8 TwinDie DDR4 SDRAM
Electrical Characteristics – AC and DC Output Measurement
Levels

Figure 5: Differential Output Slew Rate Definition

TRdiff

Differential Input Voltage (DQS_t, DQS_c) VOH,diff(AC)

VOL,diff(AC)

TFdiff

Table 11: Differential Output Slew Rate

For RON = RZQ/7
DDR4-1333 to DDR4-3200
Parameter Symbol Min Max Unit
Differential output slew rate SRQdiff 8 18 V/ns

Note: 1. SR = slew rate; Q = query output; diff = differential signals.

Reference Load for AC Timing and Output Slew Rate

The effective reference load of 50Ω to V TT = V DDQ and driver impedance of RZQ/7 for
each output was used in defining the relevant AC timing parameters of the device as
well as output slew rate measurements.
RON nominal of DQ, DQS_t and DQS_c drivers uses 34 ohms to specify the relevant AC
timing paraeter values of the device. The maximum DC high level of output signal = 1.0
× V DDQ, the minimum DC low level of output signal = { 34 /( 34 + 50 ) } × V DDQ = 0.4 ×
VDDQ
The nominal reference level of an output signal can be approximated by the following:
The center of maximum DC high and minimum DC low = { ( 1 + 0.4 ) / 2 } × V DDQ = 0.7 ×
VDDQ. The actual reference level of output signal might vary with driver R ON and refer-
ence load tolerances. Thus, the actual reference level or midpoint of an output signal is
at the widest part of the output signal’s eye.

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 32Gb: x4, x8 TwinDie DDR4 SDRAM
Electrical Characteristics – AC and DC Output Measurement
Levels

Figure 6: Reference Load For AC Timing and Output Slew Rate

VDDQ VTT = VDDQ

DQ, DQS_t, DQS_c,

DM, TDQS_t, TDQS_c
CK_t, CK_c
DUT
RTT = 50Ω

VSSQ

Timing reference point

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 32Gb: x4, x8 TwinDie DDR4 SDRAM
Electrical Specifications – ICDD Parameters

Electrical Specifications – ICDD Parameters

Table 12: DDR4 ICDD Specifications and Conditions - Rev. B (0° ≤ TC ≤ 85°C)
Note 1 applies to the entire table
Combined Individual Bus
Symbol Die Status Width DDR4-2133 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200 Units
ICDD0 ICDD0 = x4 99 100 101 102 103 mA
IDD0 + IDD2P x8 102 103 104 105 106
ICPP0 ICPP0 = x4, x8 7 7 7 7 7 mA
IPP0 + IPP3N
ICDD1 ICDD1 = x4 109 110 111 112 113 mA
IDD1 + IDD2P x8 113 114 115 116 117
ICDD2N ICDD2N = x4, x8 91 92 93 94 95 mA
IDD2N + IDD2P
ICDD2NT ICDD2NT = x4, x8 95 96 97 98 99 mA
IDD2NT + IDD2P
ICDD2P ICDD2P = x4, x8 86 86 86 86 86 mA
IDD2P + IDD2P
ICDD2Q ICDD2Q = x4, x8 90 90 90 90 90 mA
IDD2Q + IDD2P
ICDD3N ICDD3N = x4 117 118 119 120 121 mA
IDD3N + IDD2P x8 119 120 121 122 123
ICPP3N ICPP3N = x4, x8 6 6 6 6 6 mA
IPP3N + IPP3N
ICDD3P ICDD3P = IDD3P + x4 108 109 110 111 112 mA
IDD2P x8 109 110 111 112 112
ICDD4R ICDD4R = x4 181 190 198 207 215 mA
IDD4R + IDD2P x8 205 215 225 235 245
ICDD4W ICDD4W = x4 178 185 192 200 207 mA
IDD4W + IDD2P x8 193 201 209 218 226
ICDD5R ICDD5R = x4, x8 124 124 124 124 124 mA
IDD5R + IDD2P
ICPP5R ICPP5R = x4, x8 8 8 8 8 8 mA
IPP5R + IPP3N
ICDD6N ICDD6N = x4, x8 148 148 148 148 148 mA
IDD6N + IDD6N
ICDD6E2 ICDD6E = x4, x8 258 258 258 258 258 mA
IDD6E + IDD6E
ICDD6R2 ICDD6R = x4, x8 52 52 52 52 52 mA
IDD6R + IDD6R
ICDD6A ICDD6A = x4, x8 30 30 30 30 30 mA
(25°C)2 IDD6A + IDD6A
ICDD6A ICDD6A = x4, x8 52 52 52 52 52 mA
(45°C)2 IDD6A + IDD6A

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 32Gb: x4, x8 TwinDie DDR4 SDRAM
Electrical Specifications – ICDD Parameters

Table 12: DDR4 ICDD Specifications and Conditions - Rev. B (0° ≤ TC ≤ 85°C) (Continued)
Note 1 applies to the entire table
Combined Individual Bus
Symbol Die Status Width DDR4-2133 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200 Units
ICDD6A ICDD6A = x4, x8 146 146 146 146 146 mA
(75°C)2 IDD6A + IDD6A
ICDD6A ICDD6A = x4, x8 258 258 258 258 258 mA
(95°C)2 IDD6A + IDD6A
ICPP6X ICPP6x = x4, x8 18 18 18 18 18 mA
IPP6x + IPP6x
ICDD7 ICDD7 = x4 230 239 251 263 277 mA
IDD7 + IDD2P x8 226 228 233 236 239
ICPP7 ICPP7 = x4 14 14 14 14 14 mA
IPP7 + IPP3N x8 13 13 13 13 13
ICDD8 ICDD8 = IDD8 + x4, x8 80 80 80 80 80 mA
IDD8

Notes: 1. ICDD values reflect the combined current of both individual die. IDDx represents individu-
al die values.
2. ICDD6R , ICDD6A, and ICDD6E values are verified by design and characterization, and may
not be subject to production test.
3. ICDD values must be derated (increased) when operated outside of the range 0°C ≤ TC ≤
85°C. They must also be derated when using features such as CAL, CA Parity, Read/Write
DBI, AL, Gear-down, Write CRC, 2X/4X REF, and DLL disabled. Refer to the 16Gb mono-
lithic data sheet for all derating values. Derating values apply to each individual IDDx
that make up the combined ICDD

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 32Gb: x4, x8 TwinDie DDR4 SDRAM
DRAM Package Electrical Specifications

DRAM Package Electrical Specifications

Table 13: DRAM Package Electrical Specifications for x4, x8, and x16 DDP Devices
Notes 1-2 apply to the entire table
DDR4-1600, 1866, 2133,
2400, 2666, 2933, 3200
Parameter Symbol Min Max Unit Notes
Input/output Zpkg ZIO 35 60 ohm 3
Package delay TdIO 60 120 ps 3
Lpkg LIO – 5.5 nH
Cpkg CIO – 4 pF
DQSL_t/DQSL_c/ Zpkg ZIO DQS 35 60 ohm
DQSU_t/DQSU_c Package delay TdIO DQS 60 120 ps
Lpkg LIO DQS – 5.5 nH
Cpkg CIO DQS – 4 pF
DQSL_t/DQSL_c, Delta Zpkg DZIO DQS – 5 ohm 4
DQSU_t/DQSU_c, Delta delay DTdIO DQS – 5 ps 4
Input CTRL pins Zpkg ZI CTRL 30 70 ohm 5
Package delay TdI CTRL 60 120 ps 5
Lpkg LI CTRL – 7.5 nH
Cpkg CI CTRL – 4 pF
Input CMD ADD Zpkg ZI ADD CMD 30 60 ohm 6
pins Package delay TdI ADD CMD 60 120 ps 6
Lpkg LI ADD CMD – 7.5 nH
Cpkg CI ADD CMD – 4 pF
CK_t, CK_c Zpkg ZCK 30 60 ohm
Package delay TdCK 60 120 ps
Delta Zpkg DZDCK – 5 ohm 7
Delta delay DTdDCK – 5 ps 7
Input CLK Lpkg LI CLK – 7.5 nH
Cpkg CI CLK – 4 pF
ZQ Zpkg ZO ZQ – 50 ohm
ZQ delay TdO ZQ 30 135 ps
ALERT Zpkg ZO ALERT 30 60 ohm
ALERT delay TdO ALERT 60 110 ps

Notes: 1. The values in this table are guaranteed by design/simulation only, and are not subject to
production testing.
2. Package implementations should satisfy targets if the Zpkg and package delay fall with-
in the ranges shown, and the maximum Lpkg and Cpkg do not exceed the maximum
values shown. The package design targets are provided for reference, system signal sim-
ulations should not use these values but use the Micron package model.
3. ZIO and TdIO apply to DQ, DM, DQS_c, DQS_t, TDQS_t, and TDQS_c.

CCM005-1406124318-10457
32Gb_x4_x8_2cs_TwinDie.pdf - Rev. A 07/19 EN 14 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2019 Micron Technology, Inc. All rights reserved.
 32Gb: x4, x8 TwinDie DDR4 SDRAM
DRAM Package Electrical Specifications

4. Absolute value of ZIO (DQS_t), ZIO (DQS_c) for impedance (Z) or absolute value of TdIO
(DQS_t), TdIO (DQS_c) for delay (Td).
5. ZI CTRL and TdI CTRL apply to ODT, CS_n, and CKE.
6. ZI ADD CMD and TdI ADD CMD apply to A[17:0], BA[1:0], BG[1:0], RAS_n CAS_n, and WE_n.
7. Absolute value of ZCK_t, ZCK_c for impedance (Z) or absolute value of TdCK_t, TdCK_c
for delay (Td).

CCM005-1406124318-10457
32Gb_x4_x8_2cs_TwinDie.pdf - Rev. A 07/19 EN 15 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2019 Micron Technology, Inc. All rights reserved.
 32Gb: x4, x8 TwinDie DDR4 SDRAM
Package Dimensions

Package Dimensions

Figure 7: 78-Ball FBGA Die Rev. B (package code BAF)

Seating plane

A 0.1 A

78X Ø0.47 ±0.05

Dimensions apply
to solder balls post- Ball A1 ID Ball A1 ID
reflow on Ø0.42
SMD ball pads.
9 8 7 3 2 1
A
B
C
D
E
F
11 ±0.1 G
H
9.6 CTR J
K
L
M
0.8 TYP
N

0.8 TYP 1.1 ±0.1

6.4 CTR 0.34 ±0.05

10.5 ±0.1

Notes: 1. All dimensions are in millimeters.

2. Solder ball material: SAC302 (96.8% Sn, 3% Ag, 0.2% Cu).

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-4000

www.micron.com/products/support Sales inquiries: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc. TwinDie is a trademark of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.

CCM005-1406124318-10457
32Gb_x4_x8_2cs_TwinDie.pdf - Rev. A 07/19 EN 16 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2019 Micron Technology, Inc. All rights reserved.