CS150 Homework 8

Solutions

1. Write down all of the integers that can be represented using 2 bits in twos-
complement (write the decimal value and the corresponding binary
representation).

00 0
01 1
10 -2
11 -1

2. Same thing, but for 3bit twos-complement numbers.

000 0
001 1
010 2
011 3
100 -4
101 -3
110 -2
111 -1

3. Without using a calculator, what is the most positive and most negative
number that can be represented using a 8-bit twos-complement
representation? 16-bit? What are the binary representations of these
numbers?

8-bit
127
Most Positive: 0111 1111 = 255 Thanks to mattrad
Most Negative: 1000 0000 = -128
-256 on the newsgroup
for the correction!
16-bit
Most Positive: 0111 1111 1111 1111 = 215 - 1 = 32767
Most Negative: 1000 0000 0000 0000 = -215 = -32768
 4. CLD2 Problem 5.9 Do this problem for the 64 bit case only. Figure 5.18
shows how to use 4-bit adders and a 4-bit carry look-ahead unit to implement
a fast 16-bit adder. Using these primitive building blocks, show how to
construct a 64-bit adder with carry lookahead.
(a) draw block diagrams for the 64-bit adders, showing all interconnections

Note: This is one way to construct a 64-bit adder, using four 16-bit carry look-
ahead (CLA) adders cascaded in series. There is a more efficient way to make a 64-
bit adder, using another level of CLA logic (basically, use the same design as the 16-
bit CLA adder shown in Figure 5.18, but replace the 4-bit adders with the 16-bit
adders).

(hook up 4 16-bit modules as shown in figure 5.18)

4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4

A[31-28] B[31-28] A[27-24] B[27-24] A[23-20] B[23-20] A[19-16] B[19-16] A[15-12] B[15-12] A[11-8] B[11-8] A[7-4] B[7-4] A[3-0] B[3-0]

4-Bit Adder C28 4-Bit Adder C24 4-Bit Adder C20 4-Bit Adder C16 4-Bit Adder C12 4-Bit Adder C8 4-Bit Adder C4 4-Bit Adder C0

P G P G P G P G P G P G P G P G

4 4 4 4 4 4 4 4
S[31-28] S[27-24] S[23-20] S[19-16] S[15-12] S[11-8] S[7-4] S[3-0]

C32 Lookahead Carry Unit C16 C16 Lookahead Carry Unit C0

4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4

A[63-60] B[63-60] A[59-56] B[59-56] A[55-52] B[55-52] A[51-48] B[51-48] A[47-44] B[47-44] A[43-40] B[43-40] A[39-36] B[39-36] A[35-32] B[35-32]

4-Bit Adder C60 4-Bit Adder C56 4-Bit Adder C52 4-Bit Adder C48 4-Bit Adder C44 4-Bit Adder C40 4-Bit Adder C36 4-Bit Adder C32

P G P G P G P G P G P G P G P G

4 4 4 4 4 4 4 4
S[63-60] S[59-56] S[55-52] S[51-48] S[47-44] S[43-40] S[39-36] S[35-32]

C64 Lookahead Carry Unit C48 C48 Lookahead Carry Unit C32
 (b) analyze the worst-case gate delays encountered in 32 and 64 bit addition. Use
the simple delay models as in Section 5.6

(use gate delays according to figure 5.18 on page 243)

4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4

A[31-28] B[31-28] A[27-24] B[27-24] A[23-20] B[23-20] A[19-16] B[19-16] A[15-12] B[15-12] A[11-8] B[11-8] A[7-4] B[7-4] A[3-0] B[3-0]

4-Bit Adder C28 4-Bit Adder C24 4-Bit Adder C20 4-Bit Adder C16 4-Bit Adder C12 4-Bit Adder C8 4-Bit Adder C4 4-Bit Adder C0

P G P G P G P G P G P G P G P G

4 4 4 4 4 4 4 4
S[31-28] S[27-24] S[23-20] S[19-16] S[15-12] S[11-8] S[7-4] S[3-0]

C32 Lookahead Carry Unit C16 C16 Lookahead Carry Unit C0

delay = 5

4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4

A[63-60] B[63-60] A[59-56] B[59-56] A[55-52] B[55-52] A[51-48] B[51-48] A[47-44] B[47-44] A[43-40] B[43-40] A[39-36] B[39-36] A[35-32] B[35-32]

4-Bit Adder C60 4-Bit Adder C56 4-Bit Adder C52 4-Bit Adder C48 4-Bit Adder C44 4-Bit Adder C40 4-Bit Adder C36 4-Bit Adder C32

P G P G P G P G P G P G P G P G

4 4 4 4 4 4 4 4
S[63-60]
delay = 23S[59-56] S[55-52] S[51-48] S[47-44] S[43-40] S[39-36] S[35-32]
(15+8)

C16 C16
C64 Lookahead Carry Unit C48 C48 Lookahead Carry Unit C16 C16
delay = 15 delay = 10
(10+5) (5+5)
Total gate delay = 23.

Note: The delay for the more efficient way to make the 64-bit adder, using another
level of carry look-ahead logic, is much less.

5. CLD Problem 5.10. Consider a 16-bit adder implemented with the carry-
select technique described in Section 5.6. The adder is implemented with
three 8-bit carry look-ahead adders and eight 2:1 multiplexors. Estimate the
gate delay and compare it against a conventional 16-bit ripple adder and a
16-bit carry lookahead adder.
 5 gate delays

8-bit carry look-ahead adder

C16
8-bit carry look-ahead
[15:8] adder
5 gate delays

8-bit carry look-ahead adder

C16 8-bit carry look-ahead
[15:8] adder
7 gate delays

5 gate delays
MUX

MUX

MUX

MUX

MUX

MUX

MUX

MUX
C8
8-bit carry look-ahead adder
[0:7]
5+2=7
gate delays

S[15] S[14] S[13] S[12] S[11] S[10] S[9] S[8] S[7:0]

7+2 = 9 gate delays (AND/OR logic)

combinational
logic

C16

Carry select delay (the limiting case is the sum)

Delay of to find the sum of 8 bit adder = 7 gate delays (from figure 5.18)
Delay of mux = 2 gate delays (AND/OR logic)
Total delay = 9 gate delays
Note: the Carry select adder can be faster with pass-transistor logic for the
MUXES instead of AND/OR LOGIC
Adder type Worst Case Delay
Carry select 9 (see above)
Ripple Adder 3(first stage carry out) + 30
(subsequent stage carry out,
2 delays per stage) = 33
Carry look-ahead 8 (figure 5.18)

In addition:
a) draw a schematic of your solution
 8-bit carry look-ahead adder
C16
8-bit carry look-ahead
[15:8] adder

8-bit carry look-ahead adder

C16 8-bit carry look-ahead
[15:8] adder

MUX

MUX

MUX

MUX

MUX

MUX

MUX

MUX
C8
8-bit carry look-ahead adder
[0:7]

S[15] S[14] S[13] S[12] S[11] S[10] S[9] S[8] S[7:0]

combinational
logic

C16

b) how many 1.bit adders are necessary to implement your solution?

if each 8-bit carry look-ahead adder required 8 1-bit adders, a total of 3 x 8 = 24 1-bit
adders would be required.

c) if you implemented a 32 bit carry select adder using 3 copies of your solution
to this problem, and then implemented a 64-bit carry select adder using 3 copies
of that, how many 1 bit adders would be in your 32 and 64 bit solutions? How
many gate delays would be required for the 64 bit addition, worst case? How big
would your adder be, and how long would it take in a 65 nm process with
100,000 adders per square millimeter and a gate delay of 10 ps?
32-bit
24 x 3 = 72 1-bit adders
total gate delays = 9 (16-bit) + 2 (mux) = 11

64-bit
72 x 3 = 216 1-bit adders
total gate delays = 9 (16-bit) + 2 (mux for 32-bit) + 2 (mux for 64-bit) = 13
(1mm2/1000000)(216) = 2.16e-4 mm2
total delay = gate delay x totalstages = 10ps x 13 stages = 130 ps total delay

6. CLD2 Problem 5.12 Implement to the gate level an ALU bit slice with three
operation selection inputs, S2, S1, S0, that implements the following 8
functions of the two data inputs, A, B, and carry in, Cn
 First, we notice that when the S2 bit is 1, Cout = 0. Next, we examine the truth tables
for A+B, A-B, and B-A and generate statements for F and Cout when S2 = 0

Truth Tables:
A+B
Cin A B F Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
F = A XOR B XOR C
C = AB + BC + AC

A-B
Cin A B F Cout
0 0 0 0 0
0 0 1 1 1
0 1 0 1 0
0 1 1 0 0
1 0 0 1 1
1 0 1 0 1
1 1 0 0 0
1 1 1 1 1
F = A XOR B XOR C
C = A’B + A’C + BC

B-A
Cin A B F Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 1
0 1 1 0 0
1 0 0 1 1
1 0 1 0 0
1 1 0 0 1
1 1 1 1 1
F = A XOR B XOR C
C = AB’ + B’C + AC
 0 00

A
B'
0 00 C
01
B'
A
C
B
01 A
C
A
C
B
10
C
A
11 A'
B B
0 Fi
S1S0 A'
10 Ci
1 C S2
C
A B
B
00
A A

B
01 B
A
10
A
11
B C
C
1 11 B
S1S0

S1S0
 7. Design a register file with 8 registers of 16 bits each. Start with edge
triggered D flip flops with load and tri-state inputs, together with logic gates,
and work your way up. Inputs to your register file should be 16-bit D bus,
3bit address A LD (load) and OE (output enable) Outputs should be a single
16 bit bus.
D
D Q
R0
LD

D Q
R1
LD

D Q
R2
LD
LD
D Q
R3 OE
LD
DEMUX

MUX
D Q
R4
LD

D Q
R5
LD

D Q
R6
LD

D Q
R7
LD
A
 8. Modify your register to have a second address input that allows separate
addresses to be read and written simultaneously.

D
D Q
R0
LD

D Q
R1
LD

D Q
R2
LD
LD
D Q
R3 OE
LD
DEMUX

MUX
D Q
R4
LD

D Q
R5
LD

D Q
R6
LD

D Q
R7
LD
Awrite Aread
9. Modify your register file to have 3 ports: one input and two outputs.

D
D Q
R0
LD

D Q
R1
LD

D Q
R2
LD
LD OE1
D Q
Q

MUX
R3
LD
DEMUX

D Q
R4
LD Aread1

D Q
R5
LD
OE2
D Q Q
MUX

R6
LD

D Q
R7 Aread2
LD
Awrite