CMOS RFIC ARCHITECTURES FOR IEEE 802.15.

4
NETWORKS

John Notor, Anthony Caviglia, Gary Levy

Cadence Design Systems, Inc.

6210 Old Dobbin Lane, Suite 100
Columbia, Maryland 21045, USA

©2003 IEEE
 CMOS RFIC ARCHITECTURES FOR IEEE 802.15.4
NETWORKS
John Notor, Anthony Caviglia, Gary Levy
Cadence Design Systems, Inc.
6210 Old Dobbin Lane, Suite 100
Columbia, Maryland 21045, USA

ABSTRACT simple, low-cost, and less linear power amplifiers in the transmit
chain. Binary data is coded into 4-bit symbols (16-ary) where
While the wireless industry has been focusing on increasing high each symbol contains a nearly orthogonal 32-bit pseudo-noise
data throughput, the emerging IEEE 802.15.4 (ZigBee) protocol (PN) sequence transmitted at a 2.0 Mchips/s rate.
targets a set of applications that require simple wireless
connectivity, relaxed throughput, very low power consumption, 2. MODULATION/DEMODULATION
and lower module cost. This article will summarize the 2.4 GHz
radio physical layer (PHY) technical specifications, examine APPROACHES
alternative modem implementations, and compare possible
Key to offering the architectural options proposed in this paper is
architectures for the receiver and the transmitter in terms of
a detailed understanding of the IEEE 802.15.4 carrier modulation
performance, estimated chip area, and production cost.
format (O-QPSK with half-sine shaping, aka MSK) and how it
relates to Frequency Shift Keying (FSK), and, specifically the
1. INTRODUCTION FSK implementation of MSK where the modulation index, m, is
The rapid growth experienced by the wireless communication set to a value of 0.5. All of these modulation formats are
sector in recent years is conspicuous. Wireless network essentially equivalent, but are not identical. A coding step is
king technologies have followed suit owing to the adoption of necessary to make the FSK equivalent of MSK identical to the
services where data is shared and exchanged, with the IEEE 802.15.4 implementation of O-QPSK with half-sine
requirements for such technologies driven by the need for larger shaping. In this section, we examine the Zigbee modulation
data throughput. This however has left a number of low-rate, format as specified and show how to encode FSK to produce an
low-power sensing and monitoring applications, including those identical carrier signal.
in the agricultural, industrial, public safety, residential, vehicular,
and related sectors, underserved by the proliferation of wireless 2.1 O-QPSK With Half-Sine Shaping
technology that is exp ensive, protocol-rich and power-hungry.
The 802.15.4 protocol aims to provide a low cost, standards- Figure 1 shows the minimum IQ symbol set {00, 01, 10, 11}
based (Ethernet) solution to low-rate wireless network with the requisite half-sine shaping over the symbol interval, the
connectivity [1] [2], and potentially could become a unifying carrier phase state, ∆φc , at the end of the bit intervals (s0-s7), the
element in the telemetry market analogous to the success of change in carrier frequency, ∆fc , during the bit interval, and a
802.11 networks in the WLAN arena. phase transition map showing the allowed phase states and
transitions for the ZigBee modulation.
Also known as ZigBee, the specifications of the physical (PHY)
and media access control (MAC) layers for low-rate personal The phase transition diagram indicates the allowed transition
area networks (LR-PAN), have been under review by Task paths from each phase state to the next state for each bit interval
Group 4 of the IEEE 802.15 Wireless Personal Area Network and shows the value of the carrier frequency shift for each
Working Group since December 2000. The current draft standard transition. The outer ring applies to transitions during even bit
proposes twenty-seven frequency channels available across three clock intervals (s0, s2, s4, s6), and the inner ring applies to
bands, with this discussion focused on the link parameters of the transitions during odd bit clock intervals (s1, s3, s5, s7). For
2.4 GHz PHY. instance, if the current phase state is 1, ( the phase state at the end
of an odd clock bit interval) then during the following even clock
The radio air interface uses a direct sequence spread spectrum
bit interval, the phase could transition to either state 0 or state 2
(DSSS) method operating in the 2.4 GHz Industrial, Scientific,
along the outer ring, depending on the IQ bit pattern {01 or 11},
and Medical (ISM) band. The 2.4 GHz PHY allocates 16
with the resulting change in carrier frequency. Similarly, if the
channels from 2.405 to 2.480 GHz, with 5 MHz channel spacing
current phase state is 0, (the phase state at the end of an even
specified for relaxed transmit and receive filter requirements. The
clock bit interval) the phase could transition along the inner ring
occupied spectrum is 2 MHz per channel with a transmission rate
depending on the IQ bit pattern {11’ or 10’}, with the resulting
of 250 kb/s. While there is no frequency hopping, hooks are
change in carrier frequency. The prime notation (‘) indicates the
provided to implement dynamic channel selection.
transition is occurring during an odd bit clock cycle. The first
The modulation selected for ZigBee is Offset Quadrature Phase chip transmitted by a ZigBee modulator is designated c0, so we
Shift Keying (O-QPSK) with half-sine pulse shaping which is define the first chip clock interval as an even bit clock interval,
equivalent to Minimum Shift Keying (MSK) [3] [4]. The benefit the second chip clock interval as an odd clock interval and so
of this constant envelope modulation is the flexibility to use forth.
 1 1 0 0 If we examine Figure 1 carefully, we see that the sign of ∆f
during a bit interval depends on the values of I and Q, and
whether the interval is an even or an odd bit clock interval. For
I even bit clock intervals, the sign of ∆f is determined by the value
given by
∆φC 90 0 270 0 90 180 270 180 90
k = I xor Q (1)
∆fC -∆f -∆f +∆f +∆f +∆f +∆f -∆f -∆f
and for odd bit clock intervals, the sign of ∆f is determined by
the value of
Q
k = not (I xor Q) (2)
s0 s1 s2 s3 s4 s5 s6 s7
1 0 1 0 1 If k = 0, then ∆fc = -∆f, and if k = 1, then ∆fc = +∆f. By encoding
the ZigBee chip stream in this way, the frequency change for
Symbol Set Diagram each bit will match the O-QPSK signaling specification exactly.
Q In designing a ZigBee transmitter, one approach would be to
90 implement the chip table per the IEEE 802.15.4 specification and
then run the serial data stream through the encoder described
01 1 11 above prior to FM modulation. But, the chip codes are really
∆f −∆f coding phase, not frequency, so after FM demodulation, the data
stream would not represent the chip codes directly. A simpler
approach is to encode the chip table itself, and use the resulting
01' 11' FSK spreading code table to transmit and receive data.
−∆f ∆f

180 3. RECEIVER ARCHITECTURES

2 0 0 I
While there are many approaches to receiver design for MSK
00' 10' style modulations, two which fit the basic themes for IEEE
∆f −∆f 802.15.4 systems, namely low-cost and low-power, are the well
known Low IF and direct conversion (Zero IF) architectures. The
Low IF approach uses a classic limiter discriminator to extract
00 10 the baseband data stream from the modulated carrier. The Zero
−∆f 3 ∆f IF approach uses an IQ demodulator to extract the in-phase and
quadrature components of the modulation, which are then
270
digitized and processed to extract the data. Figure 2 shows
Phase Transition Diagram simplified block diagrams for both of these
approaches.
Figure 1: Symbol Set and Phase Transition Diagrams
For ZigBee Modulation. LNA IRM CF = 7.5 MHz LIMITER FM DEMOD SLICER

INPUT RX OUT

Figure 1 clarifies the relationship between the phase and

frequency occurrences during each bit interval, and leads to a 2397.5 - 2472.5 MHz

solution for direct frequency modulation of the carrier as an Low IF Receiver

alternative to offset quadrature phase modulation.
MIXER LPF
2.2 O-QPSK (MSK) Implemented As FSK
ADC RX I

MSK examined as frequency modulation consists of a sequence LNA

0
AGC CKTS

of positive or negative frequency shifts, each frequency shift INPUT 2405 - 2480 MHz
having the value ∆fc = 1/(4T b), where Tb is the bit (or chip) 90 LPF
interval. The resulting modulation index is m = 0.5. This can
obviously be implemented as FSK with an FM modulator driven ADC RX Q

by a serial digital bit stream. To be completely compatible with

MIXER
the IEEE 802.15.4 specification, the FSK modulator has to
produce frequency transitions that are identical to the frequency
modulations produced by the canonic O-QPSK modulator as Direct Conversion (Zero IF) Receiver
defined in the specification. To do this requires a coding step.
Figure 2. Receiver Architectures.
3.1 Low IF supports optimum demodulation with matched filter and
synchronous detection techniques.
Receiver system complexity and the associated circuit block
complexity is often mitigated by implementing a Low IF Offsetting these advantages, Zero IF receivers require circuit
architecture. The limiting IF avoids the need for automatic gain blocks that Low IF receivers do not: AGC, post-mixer DC offset
control (AGC) circuits and offers fast response to rapidly cancellation [5] [6], two analog-to-digital converters (ADCs) or
changing signal levels due to link fading conditions. The one shared ADC to digitize the signal, and additional circuitry,
discriminator and slicing circuits are straightforward to design, usually located in a separate baseband chip, to implement
are tolerant of frequency errors between the transmitter and synchronous demodulation and optimum baseband filtering. In
receiver synthesizers, do not require carrier phase general, this leads to higher receiver currents and greater power
synchronization, and do not require high supply currents or chip dissipation in return for superior performance. In addition, some
area to implement. care has to be taken to preserve amplitude balance and
quadrature phase shift for the I and Q channels.
The primary disadvantage of the Low IF architecture is a loss of
about 3 dB in sensitivity [3] relative to a coherent demodulation 4. TRANSMITTER ARCHITECTURES
scheme like the Zero IF receiver. Additionally, a channel filter is
required to extract the desired carrier, reject nearby interfering Two transmitter architectures which are appropriate for ZigBee
signals, and set the receiver predetection noise bandwidth. implement classic modulator structures as illustrated in Figure 3.
Fortunately, the IEEE 802.15.4 2.4 GHz PHY channel The IQ modulator implements the O-QPSK (or MSK) approach
assignment scheme sets channels at 5 MHz intervals, which, with [7], while the 2-point ∆Σ Fractional-N modulator implements
a 2 MHz signal spectrum width and modest adjacent channel direct carrier frequency modulation via a frequency stabilized
selectivity requirements, keeps the filter complexity requirements voltage controlled oscillator (VCO) [8]. Either modulation
low. Finally, an image reject mixer (IRM) is required to reject approach can be paired with either receiver approach previously
signals at or near the receiver image frequency. described to create a complete transceiver.
Frequency planning for the Low IF receiver for ZigBee requires I Half-Sine
DAC
some careful thought. The ZigBee chip rate for the 2.4 GHz PHY Shaping
0
is 2 Mchips/s, leading to a modulated spectrum width of about 2
Σ
TX DATA P/S
2405 - 2480 MHz TX OUTPUT
MHz. If the IF is too low, the channel filter percentage 2 Mchip/s S/P

bandwidth is high, and the filter is difficult to implement. In Q

90
Offset Half-Sine
addition, it becomes difficult to filter out the IF carrier ripple at Delay (Tb) Shaping DAC

the demodulator output, increasing the complexity of the

baseband data filter. On the other hand, an active, on chip, IF Offset QPSK Modulator with Half-Sine Shaping
filter that’s too high in frequency requires large gain bandwidth
product amplifiers to achieve adequate performance. 2 Mchip/s
FSK
TX DATA O-QPSK Coded
∆Σ
Modulator
The Low IF receiver (Figure 2) uses a 7.5 MHz IF, which results 250 kbps Encoder Control
in an achievable 27% filter bandwidth to center frequency ratio.
In addition, the low side adjacent channel (fc − 5 MHz) and Multi-
Modulus
alternate adjacent low side channel (fc − 10 MHz) end up Divider
DAC
centered at 2.5 MHz at the output of the IRM, a full channel
spacing away from the desired IF signal, considerably LPF VCO
PFD/ Loop
TX OUTPUT
simplifying the IF filter rejection and the IRM image rejection 16 MHZ CP Filter
REF
requirements.
2-Point ∆Σ PLL Modulator
3.2 Zero IF
Figure 3. Transmitter Architectures.
The Zero IF approach offers four notable architectural
advantages compared to the Low IF approach for ZigBee at the
expense of a considerable increase in complexity. First of all, 4.1 IQ Modulator
unlike the Low IF approach which requires a 7.5 MHz frequency
The IQ modulator approach reverses the Zero IF receiver
hop between transmit and receive, the Zero IF approach does not
architecture, so baseband signals drive the IQ modulator inputs,
require the transceiver local oscillator (LO) to change frequency
when transitioning between transmit and receive modes. Since and the modulator RF output is the sum of the quadrature I and Q
the turn-around time between transmit and receive modes for channels. The I and Q signals, including half-sine shaping, are
ZigBee is specified as less than 12 symbol intervals, for the 2.4 generated with digital logic and converted to analog signals using
two digital-to-analog converters (DACs) with output data
GHz PHY the LO must make the 7.5 MHz frequency shift in less
reconstruction filters (not shown) to drive the quadrature mixers.
than 192 µs. Secondly, the Zero IF approach does not require an
While simple in concept, the requirement for dual DAC’s, dual
image reject mixer, since the homodyne architecture does not
up-converting mixers, and quadrature phase shifted LO signals
create an image frequency [5] [6]. Third, the Zero IF architecture
leads to a relatively complex, high current design resulting in an
utilizes a pair of simpler to implement low pass filters (as
implementation requiring a larger silicon area [8] [9].
compared to an equivalent bandwidth IF bandpass filter) to set
the I and Q output SNR [5] [6]. Finally, the Zero IF architecture
4.2 2-Point ∆Σ Fractional-N Modulation Specifically, an 802.15.4 receiver could be implemented using
either a Low IF or Zero IF architecture, the trade-off being low
The 2 − point approach combines the LO frequency synthesis circuit complexity versus performance and die size. When
circuits with modulation circuits to achieve compact MSK considering transmitters for ZigBee, an obvious candidate
modulation with a minimum number of analog components. The architecture was shown to be the classic IQ modulator
implementation as shown in Figure 3 is based on a phase locked implementing O-QPSK modulation per the working group
loop (PLL) using a multi-modulus divider driven by a multi-bit specification. This paper also proposed a less obvious but elegant
∆Σ modulator to provide channel frequency selection and digital modulation approach utilizing a 2-point ∆Σ Fractional-N
frequency modulation control, combined with a DAC to provide synthesizer that would require less current, area, and lower
the analog modulation control. The 2-point modulator decouples circuit block complexity. The presented receiver and transmitter
the PLL bandwidth from the modulation bandwidth by using the architectures can be paired in any combination. Given these
fine resolution digital frequency control provided by the ∆Σ options, the low-power, low-cost goal of a LR-PAN as defined
modulator to cancel the analog frequency modulation created by by the 2.4 GHz ZigBee PHY is within reach.
the DAC so there is no net change to the average divider
frequency output. The result is that the average loop amplifier 7. REFERENCES
output remains constant over each modulation bit interval, and
[1] E. Callaway et al, “Home Networking with IEEE 802.15.4:
the loop response is not excited by the modulation waveform. A Developing Standard for Low-Rate Wireless Personal
The modulation bandwidth is only dependent on the frequency Area Networks, IEEE Communications Magazine, Aug.
response of the analog frequency modulation path [8] [9].
2002, pp. 69-77.
2−point modulation adds complexity primarily in the digital [2] J.A. Gutierrez et al, “IEEE 802.15.4: A Developing
circuit domain, which for most modern IC processes adds little to Standard for Low-Power Low-Cost Wireless Personal Area
die size. The only additional analog components beyond those Networks, IEEE Network Magazine, Sept./Oct. 2001, pp.
necessary for the PLL itself are one DAC and an additional low 12-19.
pass filter to reject the spurious signals associated with the ∆Σ [3] J.A.C. Bingham, “The Theory and Practice of Modem
modulator. Design,” John Wiley & Sons, 1988, pp. 92-100.
[4] R.M. Gagliardi, “Satellite Communications,” Lifetime
Learning Publications, 1984, pp. 49-51.
5. TRANSCEIVER TRADE-OFFS [5] B. Razavi, “Design Considerations for Direct-Conversion
Estimated areas for the receiver and transmitter implementations Receivers”, IEEE Transactions on Circuits and Systems,
discussed in this paper paired in one possible set of transceiver June 1997, pp 428-435.
configurations are listed in Table 1. The area estimates were [6] A.A. Abidi, “Direct-Conversion Radio Transceivers for
arrived at by applying scaling factors to the block areas of Digital Communications”, IEEE Journal of Solid State
similarly fabricated PAN systems implemented in a 0.18 µm Circuits, December 1995, pp. 1399-1410.
CMOS process. An estimated cost of $ 0.10/mm2 for production [7] L.E. Larson, “RF and Microwave Circuit Design for
quantities is used in the cost calculations. Wireless Communications”, Artech House Publishers, 1996,
pp.156-166.
COST PARAMETER Low IF RX Zero IF RX [8] R.A. Meyers, P.H. Waters, “Synt hesizer Review for Pan-
RF Front-End Area .9 mm2 1.75 mm2 European Digital Cellular Radio”, IEEE Colloquium on
IF Chain Area 1.6 mm2 2.5 mm2
RX Chip Area 2.5 mm2 4.25 mm2
VLSI Implementations for Second Generation Digital
RX Die Cost $ 0.25 $ 0.425 Cordless and Mobile Telecommunication Systems, March
2-point ∆Σ Fractional-N 1990, pp. 8/1-8/10.
IQ Modulator TX
Modulator TX [9] J. Notor and G. Levy, “RF and Analog Design
Synthesizer 1.5 mm2 2.75 mm2
Transmitter 1.8 mm2 1.8 mm2 Considerations for Fully-Integrated Bluetooth CMOS
TX Chip Area 3.3 mm2 4.55 mm2 RFICs,” Proceedings of the 2002 Communications Design
TX Die Cost $ 0.33 $ 0.455 Conference, September 2002.
RX & TX Area 5.8 mm2 8.8 mm2
RX & TX Die Cost $ 0.58 $ 0.88

Table 1. Production cost comparison between receiver,

transmitter, and transceiver architectures.

6. CONCLUSION
The aspects of the 2.4 GHz radio PHY technical specification for
802.15.4 applicable to system design have been detailed with
specific attention paid to the modulation/demodulation format
and an alternative implementation. Possible receiver and
transmitter architectures were proposed and examined, and two
possible transceiver systems were briefly reviewed.