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Edgar David Hernández Medina T00054326: 54-Bit 5-Bit 5-Bit

The document summarizes a cache simulation with a 64-bit address space. It has a direct-mapped cache with a block size of 8 words and 32 blocks. The hit ratio for the sample references is 33%. The final cache state contains 4 valid blocks stored as <index, tag, data> tuples.

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Kleiderman Garcia M
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107 views2 pages

Edgar David Hernández Medina T00054326: 54-Bit 5-Bit 5-Bit

The document summarizes a cache simulation with a 64-bit address space. It has a direct-mapped cache with a block size of 8 words and 32 blocks. The hit ratio for the sample references is 33%. The final cache state contains 4 valid blocks stored as <index, tag, data> tuples.

Uploaded by

Kleiderman Garcia M
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Workshop Week 9.

Edgar David Hernández Medina T00054326

1. For a direct-mapped cache design with a 64-bit address, the following bits of the address
are used to access the cache.

54-bit 5-bit 5-bit

● What is the cache block size (in words)? 8 words.


2𝑚
R/. Cache block size in words = , m is #bits used by offset therefore, cache block size
4
25
in words: = 8 𝑤𝑜𝑟𝑑𝑠
4
● How many blocks does the cache have? 32 blocks.
R/. There are five index bits. This means there are 2^5 = 32 blocks or lines in the cache.
● What is the ratio between total bits required for such a cache implementation over the
8192 𝑏𝑖𝑡 + (54 𝑏𝑖𝑡 ∗ 32) + 1 𝑏𝑖𝑡 ∗ (32)
data storage bits? 𝑟𝑎𝑡𝑖𝑜 = 81922 𝑏𝑖𝑡
= 1.21

2. Beginning from power on, the following byte-addressed cache references are recorded.

● For each reference, list (1) its tag, index, and offset, (2) whether it is a hit or a
miss, and (3) which bytes were replaced (if any).

Bytes
Byte Address Binary Address Tag Index Offset Hit/Miss
Replaced
0x00 0000 0000 0000 0x0 0x00 0x00 M
0x04 0000 0000 0100 0x0 0x00 0x04 H
0x10 0000 0001 0000 0x0 0x00 0x10 H
0x84 0000 1000 0100 0x0 0x04 0x04 M
0xe8 0000 1110 1000 0x0 0x07 0x08 M
0xa0 0000 1010 0000 0x0 0x05 0x00 M
0x400 0100 0000 000 0x1 0x00 0x00 M 0x00-0x1F
0x1e 0000 0001 1110 0x0 0x00 0x1e M 0x400-0x41F
0x8c 0000 1000 1100 0x0 0x04 0x0c H
0xc1c 1100 0001 1100 0x3 0x00 0x1c M 0x00-0x1F
0xb4 0000 1011 0100 0x0 0x05 0x41 H
0x884 1000 1000 0100 0x2 0x04 0x04 M 0x80-0x9f
● What is the hit ratio?
R/. 4/12 = 33%

● List the final state of the cache, with each valid entry represented as a record of
<index, tag, data>. For example,

<0, 3, Mem[0xC00]-Mem[0xC1F]>

R/.
<index, tag, data>
<0, 3, Mem[0xC00] - Mem[0xC1F]>
<4, 2, Mem[0x880] - Mem[0x89f]>
<5, 0, Mem[0x0A0] – Mem[0x0Bf]>
<7, 0, Mem[0x0e0] – Mem[0x0ff]>

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