706 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO.

4, APRIL 2001

LVDS I/O Interface for Gb/s-per-Pin Operation in 0.35-m CMOS

Andrea Boni, Member, IEEE, Andrea Pierazzi, and Davide Vecchi

Abstract—This paper presents the design and the implemen- issues if low-cost solutions with neither external components
tation of input/output (I/O) interface circuits for Gb/s-per-pin nor trimming procedures are required. At the same time, the
operation, fully compatible with low-voltage differential signaling very large variation tolerated for the common-mode voltage at
(LVDS) standard. Due to the differential transmission technique
and the low voltage swing, LVDS allows high transmission speeds the input of a LVDS receiver requires several design improve-
and low power consumption at the same time. In the proposed ments over the typical architecture if transmission speeds in the
transmitter, the required tolerance on the dc output levels was gigabits-per-second range must be achieved. It should be re-
achieved over process, temperature, and supply voltage variations marked that a recent standard [3] recommends a maximum data
with neither external components nor trimming procedures, by rate of 655 Mb/s, forecasting data rates of 1.5 Gb/s in the near
means of a closed-loop control circuit and an internal voltage
reference. The proposed receiver implements a dual-gain-stage future with low-loss media. At the moment, commercial LVDS
folded-cascode architecture which allows a 1.2-Gb/s transmission chipsets are specified for operation in the megabits-per-second
speed with the minimum common-mode and differential voltage range [6]–[9].
at the input. The circuits were implemented in a 3.3-V 0.35- m This paper describes the design and the implementation of a
CMOS technology in a couple of test chips. Transmission opera- complete LVDS I/O interface in 0.35- m CMOS technology.
tions up to 1.2 Gb/s with random data patterns and up to 2 Gb/s
in asynchronous mode were demonstrated. The transmitter and The interface was tested up to 1.2 Gb/s with 8-bit random data
receiver pad cells exhibit a power consumption of 43 and 33 mW, patterns and up to 2 Gb/s in asynchronous mode. Complete com-
respectively. patibility of the output levels with the requirements of standards
Index Terms—Back-plane drivers, CMOS integrated circuits, [2], [3] was achieved by means of an internal reference.
high-speed integrated circuits, input/output (I/O), low-power
design, low-voltage differential signaling (LVDS).
II. LVDS LINK
LVDS uses differential data transmission and the transmitter
I. INTRODUCTION
is configured as a switched-polarity current generator. A dif-

T HE EVER-increasing processing speed of microprocessor

motherboards, optical transmission links, intelligent hubs
and routers, etc., is pushing the off-chip data rate into the
ferential load resistor at the receiver end provides current-to-
voltage conversion and optimum line matching at the same time,
Fig. 1(a). For operation in the gigabits-per-second range, an ad-
gigabits-per-second range. However, unlike internal clocks, ditional termination resistor is usually placed at the source end
chip-to-board signaling gains little benefit in terms of operating to suppress reflected waves caused by crosstalk [10] or by im-
frequency from the increased silicon integration. In the last perfect termination, due to package parasitics and component
decade, high data rates were achieved by massive parallelism, tolerance, Fig. 1(b). Differential transmission greatly improves
with the disadvantages of increased complexity and cost for the the robustness of the link to common-mode voltage bouncing
IC package and the printed circuit board (PCB). For this reason, (to be considered in the case of a cable as a transmission media)
the off-chip data rate should move to the range of Gb/s-per-pin and crosstalk, therefore a reduced noise margin can be well tol-
in the near future. Indeed, the SIA Silicon Roadmap [1] erated. Indeed, LVDS uses a lower voltage swing than ECL,
forecasts an off-chip frequency of 1 GHz for peripheral buses Table I, with further advantages in terms of reduced crosstalk
with the 100-nm generation (in 2006). Furthermore, while the and radiated electro-magnetic interference (EMI). From Fig. 1,
reduction of the power consumption is of great concern in the power saving achieved with LVDS against either differen-
battery-powered portable systems, it is also required in other tial or single-ended PECL is evident. Indeed, PECL exhibits
systems to reduce the costs related to packaging and additional an open-emitter output stage and requires a resistor ( ) to
cooling systems. Low-voltage differential signaling (LVDS) V at the receiver end for line termination and biasing
technology was developed in order to provide a low-power or a pull-down resistor ( ) toward ground. Whichever termi-
and low-voltage alternative [2], [3] to other high-speed I/O nation arrangement is used, the open-emitter configuration and
interfaces for point-to-point transmission, such as emitter-cou- the larger voltage swing lead to a higher power consumption in
pled logic (ECL) [4]–[5]. LVDS achieves significant power a PECL link than in LVDS one.
savings by means of a differential scheme for transmission
and termination, in conjunction with a low voltage swing. A. Transmitter
LVDS standards pose relatively stringent requirements on the
A typical LVDS transmitter behaves as a current source with
tolerance affecting the output levels, raising interesting design
switched polarity. The output current flows through the load
resistance, establishing the correct differential output voltage
Manuscript received June 7, 2000; revised November 28, 2000. swing. The implemented transmitter, Fig. 2, uses the typical
The authors are with the Dipartimento di Ingegneria dell’ Informazione, Uni-
versity of Parma, Parma I43100, Italy (e-mail: boni@ee.unipr.it). configurations with four MOS switches in bridge configuration,
Publisher Item Identifier S 0018-9200(01)02414-3. : with and switched on, the polarity of the
0018–9200/01$10.00 © 2001 IEEE
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 4, APRIL 2001 707

TABLE I
OUTPUT LEVELS FOR LVDS AND 100K PECL

Fig. 1. Different solutions for high-speed data links. All the transmission
lines, with the characteristic impedance R , are ground referenced. (a) Data
link using LVDS with line termination at the receiver end. (b) LVDS link with
termination at the receiver and source ends for gigabits-per-second operation.
(c) Single-ended and (d) differential PECL links.

output current is positive together with the differential output

voltage. On the contrary, if and are switched off, the Fig. 2. Schematic diagram of the LVDS transmitter (top part) and the closed-
polarity of the output current and voltage is reversed. Since the loop control circuit (bottom part).
proposed transmission link is intended for operation in the giga-
bits-per-second range, the double termination scheme, Fig. 1(b), a replica of the transmitter circuit may be used [11], but in this
was used and the termination resistors were integrated in the case the effect of component mismatches between the trans-
transmitter ( ) and in the receiver cell ( ). mitters and the replica should be carefully taken into account.
With a nominal 100- load at the receiver, both the Moreover, a reported reference circuit for LVDS buffers is un-
common-mode voltage and the differential swing at the output necessary complicated and requires an external resistor and two
should fall within the LVDS standard specifications [2], [3] reference voltages [12].
over the full range of process, supply voltage, 3 V 3.6 V, and In order to achieve higher precision and lower circuit com-
temperature variations, 40 C 125 C (PVT) plexity, a simple low-power common-mode feedback control
was implemented in the transmitter, Fig. 2, bottom part. The
mV mV (1) common-mode output voltage is sensed by means of a high re-
V V (2) sistive divider ( k ) and compared
with a 1.25-V reference by the differential amplifier – .
where and are the differential output voltage and the The fraction of the tail current flowing across and is
common-mode voltage at the transmitter output, respectively. mirrored to and , respectively, thus forcing
Since this design aims at minimizing the PCB complexity and V. In order to develop the correct voltage swing on the 50- load
the production costs, external components and voltage refer- resistance ( // ), the bridge must be biased at
ences should be avoided together with wafer-level trimming. In . To this aim, is set equal to , where
order to define the correct output levels, a feedback loop across is the gain of current mirrors and ; a large
708 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 4, APRIL 2001

Fig. 3. Simulation of a differential signal transmitted over two 7-cm-long

50-
-strips. Chip-level parasitics, ESD protections, LRC package model and
lossy transmission line model are included.

gain was used in order to make negligible the power consump-

tion of the common-feedback circuit. Bias current is obtained
from a reference voltage provided by an internal bandgap, ,
and an integrated resistor, , i.e., . Fig. 4. Schematic diagram of a typical LVDS receiver.
A large stability margin over PVT variations is achieved for
the common-mode feedback by means of a pole-zero compen- with an LRC model of the package (28-pin plastic SOIC) used
sation network, ( k and pF). for the experiment. The -strips were modeled by a discrete
The precision of the setting of the differential output voltage, lossy model (valid up to 10 GHz) generated by a dedicated soft-
depends on the tolerance affecting the bandgap voltage and ware [13]. If loaded by a 10-pF external capacitance, the devel-
resistors (nominally 100 ) and . oped buffer achieves a maximum toggle frequency of 1 GHz.
The implemented pad cell occupies an area of 0.175 mm and
(3) exhibits a current consumption of 20 mA.

under the hypothesis that the transmitter is loaded by a precise B. Receiver

100- resistor (at the receiver). Since in the proposed design A typical LVDS receiver is shown in Fig. 4 [14]. The dif-
both and are polysilicon resistors of the same type, ferential voltage signal at the input is detected by a Schmitt
we can assume , leading to trigger which ensures a 25 mV 50 mV hysteresis.
Full-swing CMOS levels are obtained at the output, , by
(4) inverter . Even if this circuit performs satisfacto-
rily with the typical LVDS common-mode voltage at the input,
Therefore, integrating the termination resistor halves i.e., 1.25 V, several problems arise if the full variation of the
the effect of the polysilicon resistivity tolerance on the output common-mode voltage should be supported. In fact, the LVDS
swing, with respect to the case of external termination resistor. levels specified at the receiver input are [2]–[3]
It should be noted that implementing resistors and
by gate-controlled MOS transistor arrays is an alter- mV (5)
native solution which would allow flexible adjustment of the mV V (6)
matching resistance. However, this would lead to an increased
circuit complexity and raise problems in terms of electrostatic If low-threshold devices are not available, and
discharge (ESD) hardness. enter in triode region when the input common-mode voltage
In spite of the simplicity of the implemented control circuit, approaches 100 mV, leading to a significant reduction of the
Monte Carlo simulations (process and mismatch level) at dif- voltage gain. The reduced voltage gain of the input amplifier
ferent supply voltages and temperatures demonstrate that both may not be sufficient to properly drive the output inverter, so as
the output swing and the common-mode voltage are within the to obtain a full CMOS swing at the output .
allowed LVDS tolerance for more than 90% of the simulation In [15], a fully differential rail-to-rail input amplifier was used
runs. for accommodating the LVDS input range. However, that circuit
The proposed buffer was designed as a pad-cell with custom is likely characterized by a higher power consumption since the
ESD protections, optimized for minimum load capacitance. The common-mode output voltage is fixed by means of CMOS in-
simulated typical capacitance contributed by the pad and the verters with resistive feedback.
ESD protections is about 1.7 pF toward ground for each output. In the proposed LVDS receiver, Fig. 5, a large gain-band-
Fig. 3 shows a simulated differential signal transmitted over two width product independent on the input common-mode voltage
7-cm-long and 0.6-mm-large 50- -strip lines (FR4 thickness is achieved by means of a folded-cascode input amplifier,
is 360- m). In the simulation a full back-annotated schematic of , with resistive load, . The common-gate nMOS de-
the transmitter (including ESD protections) was used together vices, , set a low dc voltage at the drain terminal of
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 4, APRIL 2001 709

Fig. 7. Measured CK and DATA waveforms with a 11 010 010 pattern trans-
mitted at 1 Gb/s.

Fig. 5. Schematic diagram of the improved LVDS receiver supporting the full Fig. 8. Measured eye pattern at 1 Gb/s. The probe bandwidth is limited to
input range of the LVDS standard. 1 GHz.

second stage is about one order of magnitude lower than the as-
pect ratio of , the impact of on the overall
bandwidth is quite limited. Biasing voltages and are set
to 1.05 and 2.1 V, respectively (typical values). Input transistors,
and , experience a minimum source-to-drain voltage of
about 250 mV with 0.1-V common-mode voltage at the input.
The second stage is a nMOS version of the typical LVDS
receiver, Fig. 4, where the choice of pMOS input devices was
mainly determined by the input common-mode range to be sup-
ported. In the proposed receiver, the use of nMOS input devices
for the second stage has the advantage that the same voltage gain
can be achieved with lower aspect ratios, thus providing a larger
bandwidth. The implemented pad cell exhibits an area of about
0.08 mm and a current consumption of 10 mA at 1 Gb/s.

Fig. 6. Chip photograph of the transmitter chipset: SR is the serializer cir- III. EXPERIMENTAL RESULTS
cuitry, CCO is the controlled oscillator, and B.G.REF. is the biasing circuitry.
The two circuits were implemented in a couple of test chips in
a 0.35- m CMOS technology [16], Fig. 6. The transmitter is a
, in order to keep the voltage gain almost insensitive serializer transmitting a 8-bit data burst with a 90 shifted clock
to the input common-mode voltage. Since the input devices are reference over two pairs of 3-cm-long, 0.6-mm-large 50-
designed with a large aspect ratio, in order to achieve a sufficient -strip lines (FR4 thickness is 360 m). The transmission speed
voltage gain, the impedance level at the drain of those devices is is set by means of an internal current-controlled oscillator. The
critical in order to obtain the required bandwidth. The problem is receiver is a serial-to-parallel converter which allows to verify
easily overcome by means of the cascode configuration, which the performance of the proposed LVDS receiver. Measurements
ensures a low small-signal resistance at nodes and . The were performed up to 1.2 Gb/s with random data patterns. Fig. 7
value of the load resistors, , is optimized so as to achieve shows the measured CK and DATA waveforms with a 11 010 010
at the same time the required voltage gain, bandwidth, and the pattern transmitted at 1 Gb/s, while the eye pattern at 1 Gb/s is
correct common-mode voltage for the second differential gain shown in Fig. 8. A 1-GHz differential probe was used for the
stage. Since the aspect ratio of the nMOS input devices of the measurements.
710 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 4, APRIL 2001

TABLE II
PERFORMANCE SUMMARY OF THE LVDS TRANSMITTER AND RECEIVER

Table II reports a performance summary of the implemented

pad cells.

IV. CONCLUSION
Fig. 9. Top: 1 GHz waveform measured at the output of the LVDS transmitter
cell, with V = 100 mV and V = 1 25: V at the input of the LVDS A complete transmission link fully compatible with the
receiver. Bottom: I N is the input sine-wave provided to the LVDS receiver, LVDS standards and implemented in a 0.35- m CMOS tech-
corresponding to worst case conditions (V= 100 mV and V = 100 mV) nology was presented. Thanks to the differential transmission
at 600 MHz and OUT is the correspondent LVDS output.
and the low voltage swing, a significant power saving is
achieved with respect to conventional ECL circuits, but the
reduced noise margin requires a tight control of the dc output
levels over PVT variations. The proposed closed loop control at
the transmitter provides fully compatible LVDS levels without
resorting to external components or trimming procedures.
The limits of the typical LVDS receiver were overcome by
means of a double-stage folded cascode architecture featuring
a maximum transmission speed of 1.2 Gb/s with minimum
common-mode and differential input voltage.

ACKNOWLEDGMENT
The authors would like to thank Austria Mikro Systeme Int.
AG for the specification, manufacturing, and testing of this
design. In particular, the support of Dipl.-Ing. M. Manninger,
Dipl.-Ing. R. Holzhaider, Dipl.-Ing. C. Trattler, Dipl.-Ing.
Dr.techn. W. Meusburger is acknowledged. The authors are
Fig. 10. Measured dc common-mode and differential output voltage of the indebted to Prof. C. Morandi of University of Parma for fruitful
0
implemented LVDS transmitter, over a ( 40 C to 150 C) temperature range.
discussions and critical review of the paper.

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