Fernando Burrieza Galán

Lucía Carrera Saenz

Session 4: Dice Game 1(UPDATED)

We make some changes in the FSM and declare the input “Enable_1” for the ​LSFR
machine

1) Schematic diagram of Dice Game

2) Schematic of each Block

a) ELECTRONIC DICE BLOCK

The D flip flops are numbered in ascending order from left to right (K4=MSB /
K1=LSB)

State Functions:
 Fernando Burrieza Galán
Lucía Carrera Saenz
● D1= KI*C1+(Q3*~Q4+~Q3*Q4)*~C1
● D2=K2*C2+Q1*~C2
● D3=K3*C3+Q2*~C3
● D4=K4*C4+Q3*~C4

Output Functions:
● Q1=D1
● Q2=D2
● Q3=D3
● Q4=D4

b) REGISTERS BLOCKS
Register 1 bit:

Register of each player (4 Bits):

c) WINNER BLOCK

This block is composed by a comparator that decides which of the two players
will win the game.

Schematic Diagram:
 Fernando Burrieza Galán
Lucía Carrera Saenz

d) CONTROL BLOCK

In the control Block there are two parts:

*​We updated the block diagram because we left one “not” Logic Gate after the output of the
second D-Flip Flop.

The “button” input signal is the input which the human press by a button to
start the game
State functions:
● D1= Button.
● D2=Q1.

Output functions:
● button_conf= Q1*Q2.
 Fernando Burrieza Galán
Lucía Carrera Saenz

- Final State Machine

*In the lab we found a error in one of the and’s gates and we corrected.

This FSM is a Mealy Machine composed by 2 D-Flip Flops (D1/D0) because It has 4
states.

State Transition Graph:

State Encoding:

State Q1 Q0
 Fernando Burrieza Galán
Lucía Carrera Saenz

Reposo 0 0

Juega 1 0 1

Juega 2 1 0

Ganador 1 1

Transitions table and outputs table:

Input: ​ the output of the CONFORMING BLOCK.

start Q1 Q0 Q1+ Q0+ L1 L2 Enable

0 0 0 0 0 0 0 0

0 0 1 0 1 0 0 0

0 1 0 1 0 0 0 0

0 1 1 1 1 0 0 1

1 0 0 0 1 0 0 0

1 0 1 1 0 1 0 0

1 1 0 1 1 0 1 0

1 1 1 0 0 0 0 0

*As we are using D flip flops Q1+ and Q0+ have the same values as D1 and D0
respectively.

Karnaugh Tables for Output Functions and State Functions

L1

start\\Q1 00 01 11 10
Q0

0 0 0 0 0

1 0 1 0 0
 Fernando Burrieza Galán
Lucía Carrera Saenz
L1 = start * ˜Q1 * Q0

L2

start\\Q1 00 01 11 10
Q0

0 0 0 0 0

1 0 0 0 1

L2 = start * Q1 * ˜Q0

Enable

start\\Q1 00 01 11 10
Q0

0 0 0 1 0

1 0 0 0 0

E nable = ˜start * Q1 * Q0

D1

start\\Q1 00 01 11 10
Q0

0 0 0 1 1

1 0 1 0 1

D1 = (˜start * Q1) + (Q1 * ˜Q0) + (start * ˜Q1 * Q0)

D0

start\\Q1 00 01 11 10
Q0

0 0 1 1 0

1 1 0 0 1
 Fernando Burrieza Galán
Lucía Carrera Saenz

D0 = (Q0 * ˜start) + (start * ˜Qo) ----> ​Nor Function: ​(ã*b)+(a*~b)

Schematic Diagram:

3) Chronogram of the complete circuit

Before the LAB class:

After LAB class: