MS VLSI CAD(Syllabus)

MS VLSI CAD (Syllabus)

First Semester
Subject Theory Lab Total
Subject Name
Code Credits Credits Credits
EDA 601 Digital System & VLSI Design 03 01 04
EDA 603 High Level Digital Design & Testing 03 01 04
EDA 605 Data Structures & Algorithms 03 01 04
EDA 607 Process Technology 03 01 04
EDA 609 Principles of ASIC Design 03 01 04
EDA 611 Elective I 03 01 04
Term Paper - I -- -- 01
TOTAL 18 06 25
Second Semester
EDA 602 Embedded System Design 03 01 04
EDA 604 Advanced Logic Synthesis 03 01 04
EDA 606 Advanced VLSI Design 03 01 04
EDA 608 Low Power VLSI Design 03 01 04
EDA 610 Elective II 03 01 04
EDA 612 Elective III 03 01 04
Term Paper – II -- -- 01
TOTAL 18 06 25
Third & Fourth Semester
Project Work -- -- 40
Total Number of Credits to Award Degree 90
EDA 611 Elective I:
EDA 611.1 CAD for VLSI & Graph Theory
EDA 611.2 System Software
EDA 610 Elective II
EDA 610.1 Design using Microcontrollers
EDA 610.2 Real Time Operating System
EDA 610.3 System on Chip Design
EDA 612 Elective III
EDA 612.1 Digital Signal Processing
EDA 612.2 High Speed VLSI Design
EDA 612.3 Device Drivers

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MS VLSI CAD(Syllabus)
First Semester
EDA 601 Digital System & VLSI Design

1.0 Review of Digital Logic Circuits Design

1.1 Combinational Circuits – Analysis and Design
1.2 Sequential circuits – Analysis and Design
1.1 Finite State Machines - Mealy and Moore machines
1.2 Review of logic families
2.0 MOS transistor theory
2.1 Introduction
2.2 MOS device design equations
2.3 CMOS inverter – DC characteristics
2.4 Static load MOS inverters
2.5 Pass transistor, Transmission gate, tristate inverter
3.0 Circuit characterization
3.1 Resistance estimation
3.2 Capacitance estimation
3.3 Switching characteristics
3.4 CMOS gate transistor sizing
3.5 Power dissipation
3.6 Scaling principles
4.0 CMOS circuit and layout design [6 hrs]
4.1 CMOS logic gate design
4.2 Basic physical design of simple gates
4.3 CMOS logic structures
4.4 Clocking strategies
5.0 Memory, registers & System timing aspects [3 hrs]
5.1 3 transistor memory cell
5.2 nMOS pseudo static memory cell, Two 4-bit words of RAM
array
6.0 Practical realities and ground rules [3 hrs]
6.1 Performance, Floor plan & Layout
6.2 I/O pad layout
6.3 System delays

References:

 T. L. Floyd, Digital Fundamentals, Fourth Edition, Macmillan

Publishing, 1990
 M. M. Mano, Digital Design, Prentice Hall, 1984
 P. K. Lala, Practical Digital Logic Design and Testing, Prentice Hall,
1996

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MS VLSI CAD(Syllabus)
 Zvi Kohavi, Switching and Finite Automata Theory, McGraw-Hill,
1978.
 Neil H. E. Weste, Kamran Eshraghian, Principles of CMOS VLSI
Design: a systems perspective, Second Edition, Addison Wesley,
1999.
 Douglas A Pucknell & Kamran Eshraghian, Basic VLSI design:
Systems and Circuits
 John F Wakerly, Digital Design : Principles and Practices
 Zoron Salcic, VHDL and FPLDs in Digital Systems Design,
Prototyping and Customisation

EDA 603 High Level Digital Design & Testing

A. VHDL:

1.0 Introduction to HDL based design

2.0 VHDL data types.
3.0 Operators
4.0 Behavioral Model
5.0 Subprograms
6.0 Data flow modeling
7.0 Structural Model
 Generic constants
 Generate statements
 Configuration statements

B. Verilog:

1.0 Introduction to Verilog

2.0 Hierarchical Modeling Concepts
3.0 Basic Concepts
4.0 Modules and Ports
5.0 Gate-Level Modeling
6.0 Data flow Modeling
7.0 Behavioral Modeling
8.0 Tasks and Functions
9.0 Modeling Techniques
10.0 Timing and Delays
11.0 Switch Level Modeling

C. Testing:

1.0 Introduction to Digital Testing

2.0 Fault modeling

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3.0 Fault Simulation
4.0 Testing for Single stuck faults
5.0 Design For Testability (DFT)
 Ad-Hoc DFT
 Scan based designs
 Built-In Self-Test (BIST)

Reference Books

 Introductory VHDL From Simulation to Synthesis by Sudhakar

Yalamanchili, Pearson Education, 2001
 Verilog HDL by Samir Palnitkar, Pearson Education, 2001.
 Digital Systems Testing and Testable Design by Miron A, Melvin
A.B., Arthur D.F.

EDA 605 Data Structures and Algorithms

ESD611 / DES601 / EDA605 Data Structures & Algorithms
Unit 1: INTRODUCTION TO ALGORITHMS 3 hrs
1.1 Notion of Algorithm
1.2 Fundamentals of Algorithmic problem Solving
1.3 Important problem types
1.4 Analysis Frame work
1.5 Asymptotic Notations &Basic efficiency classes.
Unit 2 : INTRODUCTION TO DATA STRUCTURES 1
hrs
2.1 Information & meaning
2.2 Arrays
2.3 Structures.
Unit 3 : STACKS , RECURSION & QUEUES 5
hrs
3.1 Definition & examples
3.2 Representing (operations) Stacks
3.3 Applications
3.4 Recursive Definition & processes
3.5 Applications
3.6 Queues & its representation
3.7 Different types of Queues.
Unit 4: LINKED LISTS 3 hrs
4.1 Introduction
4.2 Different types of lists & their implementation.
Unit 5: TREES & GRAPHS 7 hrs

5.1 Binary Trees

5.2 Binary tree Representation
5.3 The Huffman Algorithm

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MS VLSI CAD(Syllabus)
5.4 Representing lists as trees
5.5 Balanced Search Trees
5.6 Expression Trees
5.7 Tree Traversal Techniques
5.8 Introduction to Graphs and their Representations.
5.9 DFS &BFS Search
5.10 Topological Sorting
Unit 6: DIVIDE & CONUQER 3 hrs
6.1 Merge Sort
6.2 Quick sorts.
6.3 Binary search
6.4 Strassen’s Matrix Multiplication
Unit 7: TRANSFORM & CONQUER 3 hrs
7.1 Balanced search trees, AVL Trees, 2-3 Trees, Splay Trees
7.2 Heaps and Heap sort
Unit 8: DYNAMIC PROGRAMMING 3 hrs
8.1 Wars hall’s and Floyd’s Algorithm
8.2 Knapsack and Memory function
Unit 9: GREEDY TECHNIQUE. 3 hrs
9.1 Prim’s Algorithm
9.2 Kruskal’s Algorithm
9.3 Dijkstras Algorithm
Unit 10: BACK TRACKIN, BRANCH &BOUND 5 hrs
10.1 n-queens problem
10.2 subset- sum problem
10.3 Assignment problem
10.4 Knapsack problem
10.5 Travelling-salesman problem.
Text Books :-
1. The Design and analysis of algoritms by “Anany levitin”
2. Data structures using c by “ Yedidyah Langsam. Moshe.j.Augenstein and M
Tenenbaum” .

EDA 607 Process Technology

Review of semiconductors

1.0 Crystal Growth & Wafer Preparation

1.1 Semiconductor materials preparation
1.2 Crystal orientation
1.3 Crystal Growth
1.4 Crystal & Wafer quality
1.5 Wafer preparation
2.0 Contamination Control
2.1 Contamination sources
2.2 Clean air strategies
2.3 Clean room construction

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2.4 Clean room maintenance
3.0 Wafer Fabrication
3.1 Wafer Terminology
3.2 Basic Wafer Operations
3.3 Wafer fabrication processes
3.4 Wafer sort
4.0 Process Yields
4.1 Yield measurement points
4.2 Yield limiters
4.3 Wafer – sort Yield limiters
5.0 CMOS process technology
5.1 Basic n-well process
5.2 The p-well process
5.3 Twin-tub process
5.4 Silicon on insulator
5.5 Bi-CMOS process.
6.0 Oxidation
6.1 Advantages of oxide layers
6.2 Oxidation mechanisms
6.3 Oxidation methods
6.4 Oxidant sources
6.5 Rapid Thermal Processing
6.6 Post oxidation evaluation
7.0 Photolithography
7.1 Overview of the patterning process
7.2 Ten step patterning process
7.3 Basic photoresist chemistry
7.4 Photoresist performance factors
7.5 Alignment and expose
7.6 Hard bake
7.7 Etching methods
7.8 Resist stripping
7.9 Mask making
7.10 Advanced processes
7.11 Pellicles
7.12 Planarization, CMP
7.13 Antireflective coatings
7.14 Optical proximity correction
8.0 Doping
8.1 Concept of diffusion
8.2 Diffusion process steps
8.3 Ion implantation- concept, system, dopant concentration
in implanted regions
9.0 Deposition
9.1 CVD basics
9.2 CVD process steps

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9.3 LPCVD systems
9.4 Molecular beam epitaxy(MBE) systems
10.0 Metallization
10.1 Conductor metals
10.2 Vacuum evaporation method
10.3 Sputtering
11.0 Wafer test, Evaluation and packaging.

References :

 Microchip Fabrication, by Peter Van Zant, 3rd Edition, McGraw-Hill,

International Edition.
 VLSI Technology, by S.M. Sze, 2nd Edition, McGraw-Hill
International Edition.

EDA 609 Elective I

EDA 609.1 CAD for VLSI & GRAPH THEORY

A. CAD FOR VLSI:

1.0 Layout Compaction

2.0 Placement and Partitioning
3.0 Floor planning
4.0 Floor planning concepts, Shape Functions and Floor plan sizing
5.0 Routing
6.0 Global routing, algorithms for global routing, local routing,
types of local routing problems, Area Routing, algorithms for
area routing, Channel routing, algorithms for channel routing.
7.0 Logic synthesis and verification
8.0 High level logic synthesis

B. GRAPH THEORY :

9.0 Paths and circuits

10.0 Cut sets and cut vertices
11.0 Trees and fundamental circuits
12.0 Planar and dual graphs
13.0 Eulerian and Hamiltonian tours
14.0 Networks and flows
15.0 Matchings

Reference Books

 Graph theory - Narsingh Deo (Prentice-Hall of India private ltd)

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 Graph theory - Gibbons
 Algorithms for VLSI Design Automation - Sabih H. Gerez (John Wiley
and Sons)
 High Level Synthesis -Introduction to chip and System Design -
Daniel Gajski, Nikil Dutt, Allen Wu, Steve Lin (Kluwer Academic
Publishers)
 Logic synthesis and verification algorithms - Gary D. Hachtel, Fabio
Somenzi ( Kluwer Academic Publishers)
 Computer aided logical design with emphasis on VLSI - Frederick J
Hill, Gerald R. Peterson (john Wiley & sons)

EDA 609.2 Systems Software

ESD608 / DES602 / EDA611.2 Systems Software
1. Introduction to Assemblers : a. Assembly Lan. Prog., b..Assembly scheme, RB1-
Sec 4.1, Sec 4.2
2. Assemblers Design: a. Pass structure of Assemblers b: Design of a two pass
assemblers –RB1 - Sec 4.3, Sec 4.4
3. Loaders and Linkers: Relocating & Linking Concepts, Design of a linker, linking
for Overlays, Loader- RB1- Chapter 7
4. Virtual Machines: a. Virtual Machine Concepts b. Java Byte Code c. MIL Any book
on java arcitecture and .net architecture, Information from Sun Microsystem and
Microsoft Web Site
5. Lexical Analysers: a. Regular Expression b. Finate State Machine-NFA, DFA,
c.DFA from regular Expression d. Desgining Lexical Analyser- RB2- Sec 3.3 to 3.8
6. Context Free Grammers: a. Languages,Grammars,Ambiguity,parse Trees
b.Parsing, top-down parsing, bottom-up parsing ideas- RB2-Sec 4.2 & 4.3
7. Parser Introduction a. Introduction b. Recursive Descent Parsing- RB2-Sec 4.3
partially, Sec 4.4 partially
8. Parser Design: a. Removing Left Recursion b. Desigining Recursive Descent
parsers- RB2-Sec 4.3 & 4.4
9. Paser Design: a. Predictive parsing b. LL(1) grammars- RB2- Sec 4.5 Partially
10. Paser Design: a Bottom - Up Parsing with LR(k) parsers b. Shift-Reduce parsing-
RB2-Sec 4.5Sec 4.7
11. Intermediate Code:a . Parse trees ,Three address codes, Quadruples and Triples-
RB2-Sec 8.1
12. Code Optimization:a. Principle Source of optimization b..DAG representation of
basic blocks- RB2- Sec 10.2 & Sec 9.8

Refrence Book:
1. (RB1) System Programming & Operating System BY D M Damdhere
2. (RB2) Compliers Principles,Techniques and Tools by Aho, sethi and Ulman
3. System Software By L Bach
4. Crafting a Compiler with C By Charles N. Fischer, Richard J.leBlanc,Jr.
5. Compiler Constuction Principles & Practice By kenneth C Louden

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Second Semester
EDA 602 Embedded System Design

1.0 Introduction:
1.1 Embedded Systems Overview
1.2 Design Challenges: Common Design Metrics, Time-to-
Market Design Metric, NRE and Unit cost Design Metrics,
Performance Design Metric
1.3 Processor Technology: General Purpose Processors –
Software, Single Purpose Processors – Hardware,
Application Specific Processors.

2.0 Custom Single – Purpose Processors

2.1 Introduction
2.2 Combinational Logic: Transistors and Logic Gates, Basic
Combinational Logic Design, RT – Level Combinational
Components
2.3 Sequential Logic: Flip Flops, RT – Level Sequential
Components, Sequential Logic Design.
2.4 Custom Single – Purpose Processor Design
2.5 RT – Level Custom Single – Purpose Processor Design
2.6 Optimizing Custom Single – Purpose Processors:
Optimizing the original Program, Optimizing the FSMD,
Optimizing the Data path, Optimizing the FSM.

3.0 Standard Single – Purpose Processors – Peripherals:

3.1 Introduction
3.2 Timers, Counters and Watchdog Timers: Reaction Timer
and ATM timeout using watchdog timer.
3.3 UART
3.4 Pulse Width Modulators: Controlling DC Motor using a
PWM
3.5 LCD Controllers: LCD Initialization
3.6 Keypad Controllers
3.7 Stepper Motor Controllers: Controlling a stepper motor
directly and using a driver.
3.8 Analog-to-Digital Converters: Successive Approximation
ADC.
3.9 Real-Time Clocks.

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4.0 Memory
4.1 Introduction, Memory Write ability and Storage
permanence
4.2 Common Memory types: Introduction to ROM, Mask-
Programmed ROM, One-Time Programmable ROM,
EPROM, EEPROM, Flash Memory, Introduction to RAM:
Static RAM, Pseudo-Static RAM, NVRAM, HM6264 and
27C256 RAM/ROM devices, TC55V2325FF-100 Memory
Device.
4.3 Composing Memory
4.4 Memory Hierarchy and Cache: Cache Mapping
Techniques, Cache-Replacement Policy, Cache Write
Techniques
4.5 Advanced RAM: Basic DRAM, Fat Page Mode DRAM,
Extended Data Out DRAM, Synchronous and Enhanced
Synchronous DRAM, DRAM Integration Problem, Memory
Management Unit.

5.0 Interfacing
5.1 Introduction
5.2 Communication Basics: Basic Terminologies, Basic
Protocol Concepts, ISA Bus Protocol – Memory Access.
5.3 Microprocessor Interfacing (I/O Addressing): Port and Bus
Based I/O, Memory mapped I/O and standard I/O, ISA
Bus Protocol – Standard I/O, A Basic Memory protocol, A
complex memory protocol.
5.4 Microprocessor Interfacing (Interrupts)
5.5 Microprocessor Interfacing (DMA)
5.6 DMA I/O and ISA Bus Protocol
5.7 Arbitration: Priority Arbiter, Daisy-Chain Arbitration
5.8 Advanced Communication Principles: Parallel, Serial,
Wireless communications, Layering, Error detection and
correction
5.9 Serial Protocols: I2C, CAN, Firewire, USB
5.10 Parallel Protocols: PCI Bus, ARM Bus
5.11 Wireless Protocols: IrDA, Bluetooth, IEEE 802.11

6.0 State Machine and concurrent Process Models

6.1 Introduction
6.2 Models vs. Languages, Text vs. Graphics
6.3 An Introductory Example
6.4 A Basic State Machine Modem (FSM)
6.5 FSM with Datapath Model (FSMD)
6.6 Using State Machines: Describing a System as a State
Machine, Comparing State Machines and Sequential

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Program Models, Capturing State Machines in Sequential
Programming Language
6.7 HCFSM and the statecharts Language
6.8 Program-State Machine Model (PSM)
6.9 The roll of an approapriate Model and Language
6.10 Concurrent Process Model
6.11 Concurrent Processes: Process Create and Terminate,
Process Suspend and Resume, Process Join
6.12 Communication among Processes: Shared Memory,
Message Passing.
6.13 Synchronization among Processes: Condition Variables,
Monitors.
6.14 Implementation: Creating and Terminating Processes,
Suspending and Resuming Processes, Joining a Process,
Scheduling Processes.
6.15 Data Flow Model
6.16 Real Time Systems: Windows CE, QNX.

7.0 Control Systems

7.1 Introduction
7.2 Open-Loop and Closed Loop Control Systems: Overview,
An Open-Loop Automobile Cruise Control, A Closed-Loop
Automobile Cruise Control
7.3 General Control Systems and PID Controllers: Control
Objectives, Modeling Real Physical Systems, Controller
Design
7.4 Software Coding of a PID Controller
7.5 PID Tuning
7.6 Practical Issues Related to Computer-Based Control:
Quantization and Overflow effects, Aliasing, Computation
Delay.
7.7 Benefits of Computer-Based Control Implementations:
Repeatability, Reproducibility and Stability,
Programmability.

Reference Books

 Embedded System Design – Vahid Frank & Tony Givargis

 Embedded Microcomputer Systems – Jonathan W. Valvano
 An Embedded Software Primer – David E. Simon
 Programming for Embedded Systems – Dreamtech Software Team
 Fundamentals of Embedded System Software – Daniel W Lewis
 Designing Embedded Hardware – John Catsoulis
 An Introduction to the design of Small Scale Embedded Systems –
Tim Wilmshurst

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EDA 604 Advanced Logic Synthesis

MEL 611.3 / DES 612.1 / EDA604 Advanced Logic Synthesis:

UNIT-1
Introduction to logic synthesis ,Two-level logic synthesis Introduction, Boolean algebra
concepts , Minimization using k-map (up to 5 variables). [3 hours]
UNIT-2
Minimization using Tabular method(up to 5 variables) Consensus theorem , Iterative
Consensus theorem [3 hours]
UNIT-3
Recursive computation , Unate covering problem, Reduction technique MIS algorithm
Branch and bound algorithm (Example) [3hours]
UNIT-4
Sequential logic synthesis. Introduction , Basics of FSM concept ,Minimization of
completely specified FSM ,Equivalent partition algorithm [3hours]
UNIT-5
Minimization of Incompletely specified FSM, Compatible table ,Maximum compatibles
,Prime compatibles [3hours]
UNIT-6
Minimization using Merger graph,Merger Table,closed covering. [3hours]
UNIT-7
Binate covering problem, FSM traversal algorithms , Depth first search ,Breadth first
search,Shortest path (3hours)
UNIT-8
State encoding and optimization, Multilevel logic synthesis , Introduction, Algebraic and
Boolean Division (3hours)
UNIT-9
Kernels and Cokernels ,Algebraic and Boolean resubtitution methods (3hours)
UNIT-10
Technology mapping, Graph covering and Technology mapping (3 hours)
UNIT-11
Tree covering by Dynamic programming,Decomposition (3 hours)
UNIT-12 Delay optimization and Graph covering (3 hours)
TEXT BOOK:
 Gary D. Hachtel and Fabio Somenzi (Kluwer Academic Publishers)
Reference Books
1. Logic Synthesis and Verification Algorithms
2. Gary D. Hachtel and Fabio Somenzi (Kluwer Academic Publishers)
3. Logic Minimization Algorithms For VLSI Synthesis
4. Robert K. Brayton ,Gary D. Hachtel, Curtis T. McMullen and Alberto L. Sangiovanni-
Vincentelli (Kluwer Academic Publishers)
5. Switching and finate automata theory by ZVI KOHAVI

EDA 606 Advanced VLSI Design

A. CMOS Analog Circuit Design:

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1.0 CMOS passive elements
2.0 Analog MOSFET Models
3.0 Current Sources and Sinks
4.0 References
5.0 CMOS Single Stage Amplifiers
6.0 Differential Amplifiers
7.0 Operational Amplifiers

B. Mixed-Signal Circuit Design:

8.0 Nonlinear Analog Circuits
9.0 Dynamic Analog Circuits
10.0 Data Converter Fundamentals
11.0 Data Converter Architectures

Reference Books

 Baker, Li, & Boyce, CMOS Circuit Design, Layout, and Simulation,
IEEE Press, 1998.
 Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill,
Inc., 2000.
 Johns & Martin, Analog Integrated Circuit Design, John Wiley &
Sons, 1997.
 Allen & Holberg, CMOS Analog Design, 2nd Ed., Oxford Univ. Press,
1987.
 Gray & Meyer, Analysis and Design of Analog Integrated Circuits,
John Wiley & Sons, 1984.
 Mohammed Ismail, & Terri Fiez, Analog VLSI, McGraw-Hill, Inc.
 Geiger, Allen, & Strader, VLSI - Design Techniques for Analog and
Digital Circuits, McGraw-Hill, Inc.,

EDA 608 LOW POWER VLSI DESIGN

Introduction top Low Power VLSI Design

Need for low power VLSI Design, Sources of power dissipation on
Digital Integrated circuits. Physics of power dissipation in CMOS
devices. Emerging Low power approaches.
Device & Technology Impact on Low Power: Dynamic dissipation in
CMOS, Transistor sizing & gate oxide thickness, Impact of technology
Scaling, Technology & Device innovation
Power estimation, Simulation Power analysis: SPICE circuit
simulators, gate level logic simulation, capacitive power estimation,
static state power, gate level capacitance estimation, architecture level
analysis, data correlation analysis in DSP systems, Monte Carlo
simulation.
Probabilistic power analysis: Random logic signals, probability &
frequency, probabilistic power analysis techniques, signal entropy.

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Low Power Design techniques
Circuit level: Power consumption in circuits. Flip Flops & Latches
design, high capacitance nodes, low power digital cells library
Logic level: Gate reorganization, signal gating, logic encoding, state
machine encoding, pre-computation logic
Low power Architecture & Systems: Power & performance
management, switching activity reduction, parallel architecture with
voltage reduction, flow graph transformation, low power arithmetic
components, low power memory design.
Low power Clock Distribution: Power dissipation in clock
distribution, single driver Vs distributed buffers, Zero skew Vs
tolerable skew, chip & package co design of clock network

Algorithm & architectural level methodologies: Introduction,

design flow, Algorithmic level analysis & optimization, Architectural
level estimation & synthesis.

Text Books:

1. Gary K. Yeap, “Practical Low Power Digital VLSI Design”, KAP, 2002
2. Rabaey, Pedram, “Low power design methodologies” Kluwer Academic, 1997
3. Kaushik Roy, Sharat Prasad, “Low-Power CMOS VLSI Circuit Design” Wiley,
2000

EDA 610.1 Design using Microcontrollers

ESD618 / DES612.2 / EDA610.1 Design using Microcontrollers
Objectives:
To understand basic microcontroller architecture and operation, to be able to
interface a microcontroller with the outside world, and to be able to program a
microcontroller using both assembly language and C to implement a given design.
Course Outcome:
1. Describe the fundamentals of microcontroller organization and operation. Show
the transfer of information, from register to register to memory for each
instruction.
2. Develop an understanding of embedded system design life cycle and co design
concept.
3. Deal with the internal architecture and design methodology of a micro-controller
based embedded system.
8051 MICROCONTROLLER
8051 Micro controller hardware- I/O pins, ports and circuits- External memory -
Counters and Timers-Serial Data I/O- Interrupts-Interfacing to external memory and
8255.
8051 PROGRAMMING AND APPLICATIONS
8051 instruction set - Addressing modes - Assembly language programming - I/O port
programming -Timer and counter programming - Serial Communication - Interrupt
programming -8051 Interfacing: LCD, ADC, Sensors, Stepper Motors, Keyboard and DAC.
MOTOROLA 68HC11 MICROCONTROLLERS

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Instructions and addressing modes – operating modes – Hardware reset – Interrupt
system – Parallel I/O ports – Flags – Real time clock – Programmable timer – pulse
accumulator – serial communication interface – A/D converter – hardware expansion –
Assembly language Programming
HIGH PERFORMANCE RISC ARCHITECTURE: ARM
The ARM architecture – ARM assembly language program – ARM organization and
implementation – The ARM instruction set - The thumb instruction set – ARM CPU cores.
DEVICES AND BUSES FOR DEVICE NETWORKS
I/O Devices - Device I/O Types and Examples – Synchronous - Iso-synchronous and
Asynchronous Communications from Serial Devices - Examples of Internal Serial-
Communication Devices - UART and HDLC - Parallel Port Devices - Sophisticated
interfacing features in Devices/Ports- Timer and Counting Devices - ‘12C’, ‘USB’, ‘CAN’
and advanced I/O Serial high speed buses- ISA, PCI, PCI-X, cPCI and advanced buses.
Reference Books
1. Muhammad Ali Mazidi, Janice Gillispie mazidi. “The 8051 Microcontroller and
Embedded systems”, Person Education, 2004.
2. Valvano "Embedded Microcomputer Systems" Thomson Asia PVT LTD first reprint
2001
3. Steave Furber, “ARM system – on – chip architecture” Addison Wesley, 2000.
4. Rajkamal, Embedded Systems Architecture, Programming and Design, TATA
McGraw-Hill, First reprint Oct. 2003
5. Alam Clements, “Principles of Computer Hardware” Oxford University press, Fourth
Edition 2006.
6. Wayne Wolf, Computers as Components: Principles of Embedded Computing System
Design, Morgan Kaufman Publishers, 2001
7. Steve Heath, “Embedded System Design”, Elserien, Second Edition, 2004.

EDA 610.2 Real Time Operating System

A. Real Time Oprating Systems

1.0 Introduction to traditional operating systems.

2.0 Taxonomy of kernel features, benchmarks and standards.
3.0 Process and thread management
4.0 Real time scheduling algorithms
4.1 Round Robin, FIFO, Priority based scheduling algorithms.
4.2 Rate monotonic scheduling
4.3 Priority inversion and priority ceiling
5.0 A periodic tasks and sporadic servers.
6.0 Inter-process/thread communication and synchronization
7.0 Using process/thread management and synchronization.
8.0 Clocks and Timers.
9.0 Memory management
10.0 Real time asynchronous IO.
11.0 Interrupt processing and device drivers.

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12.0 Architecture of two RTOSs - BlueCat Linux(lynuxworks) and
VXWorks(WindRiver.com)

Reference Books

 Various web links

 INTEGRITY RTOS (free source)
(http://www.ghs.com/products/rtos/integrity.html)
 Mini-project – To be executed in one month.
 Developing real time application in RTOS environment (using BlueCat
Linux and VXWorks).
 This is a group project (two people in a group). Students have to
design and implement a solution in the RTOS of their choice.

EDA 610.3 Device Drivers

1.0 Kernel and Device Drivers

1.1. Components of the Kernel
1.2. User Space vs. Kernel Space
1.3. Device Drivers and Advantages of Modules
1.4. Types of Devices
2.0 Linux Kernel: Sources and Installation
2.1. Installing the Kernel Source
2.2. lilo and Boot-up Sequence
2.3. Configuring and installing the Kernel
3.0 Linux Kernel: Methods
3.1. System Calls vs. Library Functions
3.2. How System Calls are Made
3.3. Scheduling Algorithms
3.4. IPC: Message Queues, Semaphores and Shared Memory
3.5. Locking Mechanisms
3.6. Atomic Functions and Semaphores
4.0 Linux Kernel: Threads
4.1. Multi-threading under Linux
5.0 Modules
5.1. Module Utilities, Finding Modules, Compiling a Module,
Kernel Versions
5.2. Exporting Symbols, using Non-exported Symbols and
System Calls From Modules
6.0 Debugging Techniques
6.1. Error Numbers, Printk, Using IOCTLS: Querying the
Driver
6.2. Proc Entry, Tracing, Debugger and kdb, kgdb, kgdb
Demonstration

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MS VLSI CAD(Syllabus)
7.0 Character Devices
8.0 Memory Management
8.1. Virtual and Physical Memory
8.2. Page Tables, Caching, Swapping, Block Buffering,
Mapping Functions
9.0 User and Kernel Space
9.1. put (get)_user and copy_to (from)_user
10.0 Memory Allocation
10.1. kmalloc: Small allocations, get_free_pages: Allocating
pages at a time, vmalloc: Large allocations
11.0 IOCTLS
11.1. Calling Ioctls, Driver Entry point for Ioctls, Defining Ioctls
12.0 Interrupt Handling
12.1. Installing an Interrupt Handler, Enabling/Disabling
Interrupts, Auto-detecting IRQs
13.0 Direct Memory Access (DMA)

Reference Books

 Linux Device Drivers (Nutshell Handbook)

Alessandro Rubini - O'Reilly Publishers

EDA 612.2 Digital Signal Processing

1.0 Review
2.0 FFT Algorithms
3.0 Filter Structures
4.0 Design of FIR filters
5.0 Design of IIR Filters
6.0 Multirate Signal Processing
7.0 Adaptive Filters
8.0 DSP Processor
8.1 Introduction to PDSPs – Multiplier and Multiplier
Accumulator (MAC), Modified Bus structures and memory
access schemes, Multiple access memory, Multiported
Memory, VLIW architecture, Pipelining, Special
addressing modes, On-chip Peripherals.
8.2 TMS6711 DSP processor: Architecture, Instruction set
and assembly language programming.

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MS VLSI CAD(Syllabus)
Reference Books

 DSP by Sanjith K Mitra

 DSP by Oppenheim and Schafer
 DSP by Roman Kuc
 DSP by Proakis and Manolakis
 DSP by Rabinder and Gold
 Shaum Out-Line Series
 Signals and Systems by Symon Haykins
 DSP Processors and Fundamentals
 Multirate signal processing by Vaidyanathan
 Handbook of DSP by Elliot

EDA 612.2 HIGH SPEED VLSI DESIGN

Introduction to High speed Digital Design

Frequency, time and distance, Capacitive and inductive effects. High
speed properties of logic gates, speed and power, wire modeling and
transmission lines.
Signaling convention and circuits
Signaling modes for transmission lines, signaling over RC
interconnect, driving lossy LC lines, bi-directional signaling,
terminators.
Signaling Standards, Chip-to-Chip Communication Networks, ESD
Protection
Power distribution and noise
Power supply network, IR drops, power supply isolation. Noise sources
in digital system, cross talk, inter symbol interference.
Timing convention and synchronization
Timing fundamentals, Clocking Styles, Clock Jitter, Clock Skew, Clock
Generation, Clock Distribution, synchronization failure and meta-
stability, PLL and DLL based clock aligners. Asynchronous Clocking
Techniques.
Clocked & non clocked Logics
Single-Rail Domino Logic, Dual-Rail Domino Structures, Latched
Domino Structures, Clocked Pass Gate Logic, Static CMOS, DCVS
Logic, Non-Clocked Pass Gate Families.
Latching Strategies
Basic Latch Design, and Latching single-ended logic and Differential
Logic, Race Free Latches for Pre-charged Logic Asynchronous Latch
Techniques.

Text Books:
1. Kerry Bernstein & et. al., High Speed CMOS Design Styles, Kluwer, 1999.

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MS VLSI CAD(Syllabus)
2. Evan Sutherland, Bob stroll, David Harris, Logical Efforts, Designing Fast CMOS
Circuits, Kluwer, 1999.
3. David Harris, Skew Tolerant Domino Design.
4. William S. Dally & John W. Poulton; Digital Systems Engineering, Cambridge
University Press, 1998.
5. Howard Johnson & Martin Graham; High speed Digital Design : A hand book of
Black Magic, Prentice Hall PTR, 1993.
6. Jan M. Rabaey , et all; Digital Integrated Circuits: A Design perspective, second
edition, 2003

EDA 612.3 System on Chip Design

8085 Architecture, I/O Devices 8355/8755, DMA Controller 8237, 8279 8253
Programmable Peripheral Interface 8255 Interrupt System, Digital Interfacing,
Multiple Microprocessor Systems, 8051 Microcontroller Architecture, 8051
Microcontroller System design
Architecture of 16/32/ 64 bit Microcontroller, System Architecture, Different aspects
of architecture design, Macros, CPU Organization, Data Path Design, Memory
Organization, Control Design

System on Chip Design Issues, SOC Design Methodology, Power Considerations,

SOC Case study, Design Consideration Challenges, Memories, Parameterized
Systems-on-a- Chip , System-on-a-chip Peripheral Cores , SOC and interconnect
centric Architectures

IP Core Design issues, IP Core Design Methodology, Reusability and intellectual

property, IP Core Applications
Micro Networks, SoC protocols, OC, VSI, Hardware/Software Co-Design

Reference Books:

1. Edwards M.D, Automatic Logic Synthesis Techniques for Digital Systems',

Macmillan New Electronic series, 1992.
2. F. Balarin, Hardware-software co-design of embedded systems: Kluwer academic
publishers, 1997.
3. J.Rozenblit, K.Buchenrieder: Co-design: Computer-Aided software/hardware
engineering, Piscataway, NJ; IEEE Press, 1995.
4. Myke Predko, Programming and Customizing the 8051 Microcontroller, Tata
McGraw Hill, ISBN: 0-07-042140-4, 1999.
5. Barry B.Brey, Intel Microprocessors, Architecture, Programming and Interfacing,
Prentice-Hall India, ISBN: 81-203-1220-1, 2000.

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