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CSC 504 - Computer Architecture II: Course Particulars

This document provides information on the Computer Architecture II course offered at the Federal University of Technology Akure, Nigeria. The 3 credit, compulsory course is taught over one hour weekly and has Dr. B.K. Alese and Miss. O. Iyare as instructors. Topics covered include computer design principles, arithmetic logic units, parallel processing, and memory hierarchies. Assessment is based on assignments, tests, and a final exam aiming to introduce students to computer internal design and develop skills in identifying computer components.

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علي سعدهاشم
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116 views6 pages

CSC 504 - Computer Architecture II: Course Particulars

This document provides information on the Computer Architecture II course offered at the Federal University of Technology Akure, Nigeria. The 3 credit, compulsory course is taught over one hour weekly and has Dr. B.K. Alese and Miss. O. Iyare as instructors. Topics covered include computer design principles, arithmetic logic units, parallel processing, and memory hierarchies. Assessment is based on assignments, tests, and a final exam aiming to introduce students to computer internal design and develop skills in identifying computer components.

Uploaded by

علي سعدهاشم
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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CSC 504 – Computer Architecture II

COURSE PARTICULARS
Course Code: CSC 504
Course Title: Computer Architecture II
No. of Units: 3
Course Duration: One hour of theory.
Status: Compulsory
Course Email Address:
Course Webpage:
Prerequisite: CSC301- Computer Architecture I

COURSE INSTRUCTORS
Dr. B. K. Alese
Room 28, Adamu Bulding,
Dept. of Computer Science,
Federal University of Technology, Akure, Nigeria.
Phone: +2348034540465
Email: bkalese@futa.edu.ng

and
Miss. O. Iyare
Dept. of Computer Science,
Digital Resource Centre
Federal University of Technology, Akure, Nigeria
Phone: +2347033513174
Email: oiyare@futa.edu.ng

COURSE DESCRIPTION
This course is an extensive, second computer architecture course designed primarily for students
in computer science disciplines. However, it also meets the need of students in other field like
engineering, as a course that provides knowledge in the internal design of the computer, flow of
controls in the circuitry. The focus of the course is to impart in the students useful skills that will
enhance their ability to identify computers and its design so as to make better choice. Topics to
be covered include computer architecture and design principles; computer structures; arithmetic
logic units; input/output organisation; partitioning; parallel processing; multiprocessor and
thread-level parallelism; interconnection networks and clusters; vector processing and
multiprocessing.

1
COURSE OBJECTIVES
The objectives of this course are to:
 introduce students to the internal design of the computer; and
 provide students with opportunities to develop basic skills in identifying computers.

COURSE LEARNING OUTCOMES / COMPETENCIES


Upon successful completion of this course, the student will be able to:
(Knowledge based)
 explain the driving force of PC performances, and understand the internal representation
of the computer system;
(Skills)
 use the design to:
o identify computers;

GRADING SYSTEM FOR THE COURSE


This course will be graded as follows:
Assignments 15%
Test(s) 25%
Final Examination 60%
TOTAL 100%

GENERAL INSTRUCTIONS
Attendance: It is expected that every student will be in class for lectures and also make
contributions during the course of the lecture. Attendance records will be kept and used to
determine each person’s qualification to sit for the final examination. In case of illness or other
unavoidable cause of absence, the student must communicate as soon as possible with any of the
instructors, indicating the reason for the absence.

Academic Integrity: Violations of academic integrity, including dishonesty in assignments,


examinations, or other academic performances are prohibited. You are not allowed to make
copies of another person’s work and submit it as your own; that is plagiarism. All cases of
academic dishonesty will be reported to the University Management for appropriate sanctions in
accordance with the guidelines for handling students’ misconduct as spelt out in the Students’
Handbook.
Assignments and Group Work: Students are expected to submit assignments as scheduled.
Failure to submit assignment at stipulated time will earn you zero for that assignment.

2
Code of Conduct in Lecture Rooms and Laboratories: The use of cell phones for any reason is
not allowed during lectures.

READING LIST
4
Hennessy John L. and Patterson David A (2007). Computer Architecture: A Quantitative
Approach. Morgan Kaufmann Publishers is an Imprint of Elsevier, 500 Sansome Street,
Suite 400, San Francisco, CA 94111. 705p.

Legend
1- Available in the University Library
2- Available in Departmental/School Libraries
3- Available on the Internet.
4- Available as Personal Collection
5- Available in local bookshops.

3
COURSE OUTLINE
Week Topic Remarks
1 Introduction and Course Overview During this first class, the
expectation of the students from the
course will also be documented.
Computer Architecture and Design Principles
2&3  Computer Structures
 What is Computer Architecture
 Factors affecting Computer Architecture
 RISC and CISC
Multi-Threading
 Multiprocessor versus Simultaneous
Multithreading (SMT)
 SMT Architecture
 SMT Pipeline
 Architectural Abstraction
Classification of Computers
4  ILP Architecture
 Data Parallel Architecture
 Process level Architecture
 Issues in Parallel Architecture
5 First Test The student will be tested on what
they have learned so far.
6&7 Processor Design Method
 Pipeline Design
 Instruction Pipeline
 Pipelining and Hazards in Pipelining
 Pipeline Performance
 VLIW
 Issues in VLIW Architecture
8&9 Improving Branch performance
 Control Hazards
 Branch Elimination Instruction
 Predicated Instruction
 Branch Speed up and Delayed Branch
Parallel Architecture
 Parallel processing
 Thread level Parallelism

4
10 & 11 Superscalar Processor: A Design Approach
 Superscalar Decode and Issue
 Parallel Decoding
 Pre-coding
 Issue versus Dispatch
 Blocking Issue
 Handling of Issue Blockage
 Non-Blocking Issue
 Operand Fetch Policies
Multiprocessor/ Multiprocessing
 Vector Processing
 Multicore Computing
 Amdhal’s Law
 Clustered Architecture
 Stack Architecture
12 Register Renaming
 Definition
 How renaming works
 Who does renaming
 Types of Renaming Buffers
Instruction Scheduling
 Instructions Reordering
 Handling Interrupts
 Speculative Execution
 Types of Speculation
 Reordering

13 & 14 Memory Hierarchy


 Hit and Miss
 Memory Technologies
 Memory Hierarchy Design
 DRAM Speed versus Processor Speed
 Principle of Locality
 Hashing versus Caching
Cache
 Cache Model
 Cache Miss Characterisation
 Average Memory Access Time
 Multi-level Hierarchy
 Cache Placement / Performance
 Cache Types
Cache Policies
 Read
 Load
 Fetch
 Write
 Reducing Cache Hit Time
 Small and Simple Caches
5
15 REVISION This is the week preceding the final
examination. At this time,
evaluation will be done to assess
how far the students’ expectations
for the course have been met.

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