CS April 2020
CS April 2020
semiconductorTODAY
C O M P O U N D S & A D VA N C E D S I L I C O N
Vol.15 • Issue 2 • March 2020 www.semiconductor-today.com
Silicon carbide
foundry expands
Smartphones production may fall 30% in first-half 2020 Vol. 15 • Issue 2 • March 2020
Microelectronics News 9
Skyworks and Qorvo reduce March-quarter guidance by about 6%
due to impact of COVID-19 • Analog Devices withdraws guidance
Wide-bandgap electronics News 12
GTAT and ON Semi sign $50m deal for supply of SiC material •
X-FAB adds in-house SiC epi • ST acquiring majority stake in Exagan
• Transphorm raises $21m; partners with Marelli • Eta develops
4-inch semi-insulating GaN wafers
Materials and processing equipment News 27
Veeco withdraws Q1 guidance • Plasma-Therm acquires JLS Designs p26 Fraunhofer IAF’s GaN transistors
• EVG sets up Heterogeneous Integration Competence Center have achieved record efficiency of
LED News 40 77.3%, enabling applications in
Ecosense acquires Soraa’s assets plasma generation for example.
Optoelectronics News 44
HKUST’s Kei May Lau receives 2020 Nick Holonyak Jr Award •
Rockley Photonics gains investment from Ahren Innovation Capital
Optical communications News 46
First bufferless 1.5mm III–V lasers grown directly on silicon wafers in
Si-photonics • QSFP-DD800 MSA group unveils initial hardware spec
Photovoltaics News 61
First Solar manufacturing operations continuing at Ohio, Malaysia
and Vietnam facilities
p36 EVG has established the
Technology focus: Photodiodes 62 Heterogeneous Integration Competence
Monolithic InAs quantum dot avalanche photodiode on silicon Center to aid customers developing
new products.
Technology focus: Photodiodes 64
III–V photodetectors integrated with SOI transistors
Market focus: Optoelectronics 68
3D imaging and sensing market growing at 20% CAGR to
$15bn in 2025
Technology focus: Optoelectronic integration 70
InP buffers on silicon for III–V laser diodes and data photonics
Technology focus: UV-LEDs 72
p49 InP DFB lasers from CST Global’s
Aluminium gallium nitride on silicon carbide for UV LEDs
InP100 platform have been integrated
Technology focus: GaN-on-silicon 74 into imec’s integrated silicon photonics
GaN-on-silicon platform for low-cost high-power electronics platform (iSiPP).
Patent focus: Power electronics 82
TSMC’s GaN-on-Si patents supporting ST’s strategic move
towards power GaN adoption in automotive use
Cover: X-FAB Silicon
Technology focus: Gallium oxide 84 Foundries is now
offering SiC foundry
Growing ε polytype gallium oxide with gallium nitride services at the scale
of silicon, becoming
Technology focus: RF electronics 86 the first pure-play
PiTrans project results in AlScN-based SAW resonators for foundry to add
smartphones internal SiC epitaxy
capabilities. X-FAB aims to further expand
Suppliers’ Directory 88 its SiC capacity at its facility in Lubbock,
TX, USA, where it has capacity of
Event Calendar and Advertisers’ Index 94 26,000 wafers per month. p15
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monitoring per-
ovskite thin-film
Time (s)
Time (s)
formations during 90
spin-coating and
subsequent
annealing. 0.00 .0425
20 11
In collaboration 400 500 600 700 800 900 1000
400 500 600 700 800 900 1000
Wavelength (nm)
with professor Wavelength (nm)
Norbert Nickel’s Figure 2: (a) Spin-coating: exemplary color plot obtained during perovskite deposition. The inset
group at HZB, zooms into the first 5s after starting the rotation.(b) Annealing: example of a color plot obtained
LayTec designed the during perovskite annealing. The red arrow marks the shift of the absorption edge.
Process 1: Process 2:
Spin coating Annealing
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www.k-space.com
semiconductor TODAY Compounds&AdvancedSilicon • Vol. 15 • Issue 2 • March 2020
40 News: LEDs
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R
esearchers in the USA, China and Hong Kong reduction of threading dislocations through aspect ratio
have developed monolithic indium arsenide trapping (ART). Further growth used molecular beam
(InAs) quantum dot (QD) avalanche photodiode epitaxy (MBE) to produce a dot-in-well (DWELL)
(APD) structures on (001) silicon (Si) with low dark structure. The QDs consisted of a 5-layer stack. The
current and high gain [Baile Chen et al, ACS Photonics, final dot density was 6x1010/cm2. The barrier matrix
published online 8 January 2020]. for the dots and the well barriers consisted of
The team from University of California Santa Barbara aluminium gallium arsenide (AlGaAs).
(UCSB) in the USA, ShanghaiTech University in China, APD fabrication created waveguide-shaped devices
Hong Kong University of Science and Technology, and (Figure 2). The mesas were etched with inductively
Chinese University of Hong Kong, claim that the device coupled plasma. Sidewall passivation consisted of
is the first monolithic InAs QD APD on silicon with low 12nm atomic layer deposition (ALD) aluminium oxide
dark current, which is suitable for optical fiber O-band (Al2O3) and 1µm silicon dioxide (SiO2) to suppress
(1260–1360nm) communications. They comment: current leakage. The metal contacts were palladium/
“These QD-based APDs enjoy the benefit of sharing the titanium/palladium/gold and palladium/germanium/
same epitaxial layers and processing flow as QD lasers, palladium/gold. The structure included standard
which could potentially facilitate the integration with 150µm-pitch ground–signal–ground (GSG) pads.
laser sources on a silicon platform.” The devices were cleaved to produce optical entry
“When the high gain and low dark current performance facets without anti-reflective coatings.
up to 323K (50°C) are considered, these APDs hold The room-temperature (300K) dark current for a
great potential for applications in energy-efficient 3µmx50µm device was 0.1nA (6.6x10–5A/cm2) under
interconnects
within super-
computers
and data
centers,” the
team writes.
The sub-
strate was
gallium
arsenide
(GaAs)-on-V-
grooved-Si
(GoVS)
produced
using metal-
organic
chemical
vapor
deposition
(MOCVD) —
see Figure 1. Figure 1. Schematic of InAs QD APD
The grooves grown on GoVS substrate.
in the (001) Si
enabled the
III-V photodetectors
integrated with SOI transistors
Researchers see potential for high-resolution multi-color imagers in self-driving
automobiles, time-of-flight sensing, and industrial surveillance.
R
esearchers based in Korea have monolithically creating more compact 3D devices (Figure 1).
integrated indium gallium arsenide (InGaAs) The SOI section used a 365nm silicon dioxide (SiO2)
photodiodes (PD) with silicon-on-insulator (SOI) insulation layer. The MOSFET gate stack was built
metal-oxide-semiconductor field-effect transistors from hafnium aluminium oxide (HfAlOx) insulator and
(MOSFETs) [Dae-Myeong Geum et al, IEEE Electron titanium nitride (TiN) electrodes. The structure was
Device Letters, vol41, issue3, p433, March 2020]. covered with sputtered SiO2 interlayer dielectric.
The researchers from Korea Advanced Institute of The surface was planarized using chemical mechanical
Science and Technology (KAIST), Korea Institute of polishing (CMP), before deposition of 40nm Al2O3 as
Science and Technology (KIST) and Hanyang University bonding material. The InGaAs photodiode epitaxial
see the advantage from their monolithic three- material was also prepared for bonding with 40nm
dimensional (M3D) process as arising from the maturity Al2O3 deposition. The Al2O3 surfaces were activated
of the InGaAs material process knowledge, compared with oxygen plasma treatment to enable bonding.
with more recent laboratory work on devices using The indium phosphide (InP) substrate was removed
carbon nanotubes, transition-metal dichalcogenides, from the InGaAs photodiode material before formation
and so on. of the photodiode electrodes and mesas/pixels. The top
In particular, “III–V materials can respond to the very p+-InP contact was platinum/titanium/platinum/gold
long-wavelength region (VLWIR) not only visible and (Pt/Ti/Pt/Au). The bottom n+-InGaAs contact consisted
[short-wavelength] SWIR using [antimonide] Sb-based of palladium/germanium/gold. Finally, connection was
materials and type-II band alignment structures,” the made between the photodiode cathode (n+-InGaAs)
team contends. They see their work as an important and the SOI MOSFET source terminal.
step for future high-resolution multi-color imagers. The reported process was carried out at room tem-
Such devices could find application in self-driving auto- perature, although the team reports that previous
mobiles, time-of-flight sensing, and industrial surveil- similar processing at 350°C resulted in “no degradation”
lance. The photodiode/MOSFET combination should in performance. In the present case, it was found
allow implementation of read-out integrated circuits that the performance of a 9µm-gate-length MOSFET
(ROICs) on top of image signal processor (ISP) layers, was little changed by the bonding and photodiode
Figure 1. (a) M3D integrated high-resolution multi-color imager system concept. (b) Schematic of fabricated
InGaAs photodiodes on SOI MOSFETs.
Figure 2. (a) Unit cell architectures of readout circuits and measuring devices as shown in inset.
(b) Electrical response for DI operation (c) Electrical response for SFD operation.
fabrication processes, in terms of drain current and “quite good”, considering that there was no anti-reflection
subthreshold swing. coating. The team says that the performance was
The InGaAs photodiode demonstrated a comparable to conventional InGaAs photodiodes.
forward/reverse ±1.5V bias dark current ratio of 104. The MOSFET–photodiode combinations were wired
The device showed a clear response under reverse bias together into typical ROIC configurations (Figure 2):
when illuminated by 10.4µW 1550nm laser light. direct injection (DI) and source follower per detector
Shorter wavelengths in the range 785–980nm also (SFD). The team explains: “While photo-generated
showed a reasonable linear response. The response for carriers are directly injected via the source on the out-
1500nm was stronger (0.7A/W) due to it being close put stage in the DI method, SFD uses the integration
to the band edge of the InGaAs material. Fitting with of photo-generated carriers in a capacitor during a
power-law current–power relations also suggested specific period.”
linear behavior with near-unity exponents. The fitted With the drain at 0.1V bias, the gate potential was
exponent of the illumination power was 0.97 for varied between 0.425V, subthreshold, and 1V under
1550nm light — the deviation from unity, the 1550nm illumination (Figure 2). Negative gate poten-
researchers suggest, could be explained by the tials between –0.5V and –1.5V, related to SFD oper-
presence of defects. ation, had little effect on the device response. ■
The external quantum efficiency (EQE) was 60% https://doi.org/10.1109/LED.2020.2966986
under 1550nm illumination. The value is declared to be Author: Mike Cooke
T
he global 3D imaging and sensing market is a lot thanks to the back-side illumination (BSI) tech-
expanding at a compound annual growth rate nique,” he notes. “They have also gained a cost advan-
(CAGR) of 20% from $5bn in 2019 to $15bn in tage within a maturing ecosystem. This is the main
2025, forecasts market research and strategy consult- reason why ToF has won the favor of Android phone
ing firm Yole Développement in its annual technology & makers.”
market analysis ‘3D Imaging and Sensing’. Without doubt, the main trend in 3D sensing is the
With the introduction of the iPhone X in September switch in adoption from the front to the rear of the
2017, Apple set the standard for technology and phone and mass adoption of the ToF camera. According
application for 3D sensing in the consumer space. to Yole’s report, rear attachment will surpass front
Two years later, Android phone makers have taken a attachment, with the penetration rate reaching about
different approach, using time-of-flight (ToF) cameras 42% in 2025.
(instead of structured light) and are placing them on 3D rear sensing in mobiles are expected to diversify
the rear of the phone. in application. First used for photography, to enhance
“Compared to structured light, ToF modules only ‘bokeh’ (blur effect) and zoom capabilities, it will
needs a vertical-cavity surface-emitting laser (VCSEL) expand into augmented reality (AR) and gaming.
and a diffuser on the emitter, which is less complex,” Beyond smartphones, ToF camera modules have a
says Richard Liu, technology & market analyst in the broad application market ahead of them, including
Photonics, Sensing & Display division at Yole and based intelligent driving, robots, smart homes, smart TVs,
in Shenzhen, China. “ToF sensors have now improved smart security and virtual reality (VR)/AR. Currently,
the application of ToF sensing technology in these In 2019, Finisar was acquired by II–VI, contributing
fields is still in its infancy. to the consolidation of industrial business. During this
The significance of the 3D sensing market means that period, there were several other big mergers, such as
the transition from imaging to sensing is happening Philips Photonics being acquired by Trumpf and ams
now. Artificial intelligence (AI)-powered devices and swallowing Osram. Trumpf and ams are both actively
robotics are gaining a better understanding of their moving into the Android camp’s 3D camera supply
surroundings, and developing a new level of interaction chain, providing VCSELs to Samsung and Huawei
with humans. Stereo cameras for ADAS (Advanced respectively.
Driver Assistance Systems) represent a highly antici- In China, another player is entering the 3D sensing
pated application of 3D imaging and sensing technology. ecosystem: The VCSEL output beam of the flood emitter
“The most important component in this application, for ToF requires no coding and is therefore easier to
light detection & ranging (LiDAR), is now focused on by produce. This has helped the Chinese supplier Vertilite
a large number of suppliers,” notes Liu. “There is a to join the market. Already, in 2019, the company won
wide range of LiDAR technologies to choose from, orders from Huawei for 3D sensing. This move was also
making the field a very competitive one.” driven by the policy of China to cultivate local supply
In addition to automotive ADAS and industrial AGVs chains in the midst of the US–China trade conflict.
(automatic guided vehicles) in the logistics industry, ToF arrays are key components for mobile rear
face recognition and face payments in commercial 3D sensing. ToF camera technology was first applied to
sectors have also been very successful. As such, the Phab2 Pro smart phone in 2016, which used pmd
3D sensing technology is moving towards ubiquity. and Infineon’s TOF array. A year before that, Sony
Technology providers of global shutter image sensors, bought SoftKinetic, a Belgian gesture-recognition com-
VCSELs, injection-molded and glass optics, diffractive pany with its well-known DepthSense ToF sensing sys-
optical elements (DOEs), and semiconductor packaging tem. This move brought Sony from a position of zero
are all benefiting. market share in 3D sensing receiver chips to 45% by
So what is the impact of ToF’s adoption on the supply the time that ToF camera modules took off in 2019.
chain? “The mobile 3D sensing supply chain is changing With its strong technology and supply capabilities,
rapidly,” notes Pierre Cambou, principal analyst, Sony is expected to continue to maintain its leadership
Imaging, at Yole. “As structured light technology position in ToF. But, as there has always been competi-
was introduced in iPhones in 2017, companies like tion in this area of CMOS image sensor (CIS) chip
Lumentum, ams and ST Microelectronics won this manufacturing, competition will increase. Together
first round. Later, Princeton Optronics (ams) and with partner Infineon Technologies, pmd recently
Finisar were prepared to gain VCSEL market access, announced a matching chip. Yole’s analysts expect
so the market did quickly become more competitive,” CIS giant Samsung and STMicroelectronics to bring to
he adds. market their own indirect ToF array sensors in 2020.
Samsung already adopted ToF technology notably in mergers & acquisitions (M&A) as automotive LiDAR
its Galaxy Note 10+. It has been deeply analyzed by applications may come into play. There are a large
System Plus Consulting, sister firm of Yole in the number of highly competitive emerging companies.
reverse engineering & costing report, Samsung Galaxy There are also a few Chinese startups, such as Hesai
Note 10+ 3D Time of Flight Depth Sensing Camera Technology, RoboSense, and LeiShen Intelligence.
Module. The underlying semiconductor products are the same:
Generally speaking, the competition remains very CIS chips, VCSEL, MEMS, wafer-level optical elements.
intense among a small group of CIS players. In the ■
medium-term Yole expects more opportunities for www.i-micronews.com/products/3d-imaging-sensing-2020
semiconductorTODAY
ISSN 1752-2935 (online)
C O M P O U N D S &
Vol.7 • Issue 2 • March/April 2012
A D VA N C E D S I L I C O N
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MAGAZINE
Efficiency droop in
nitride & phosphide LEDs Accurate and timely coverage of the compound semiconductor
First single-crystal and advanced silicon industries
gallium oxide FET
WEB SITE
E-BRIEF
B
ei Shi and Jonathan Klamkin of University of grown in a three-step process: 435°C low-temperature
California Santa Barbara (UCSB) in the USA (LT) nucleation, 45nm at 545°C medium temperature
have been developing techniques to grow (MT), and 950nm at 600–630°C high temperature
indium phosphide (InP) buffer layers on top of on-axis (HT).
(001) silicon (Si) with a view to silicon photonics (SiPh) Atomic force microscopy (AFM) and electron-channeling
and, in particular, III–V laser diodes [J. Appl. Phys., contrast imaging (ECCI) suggested that there was a
vol127, p033102, 2020]. trade-off between surface roughness and defect density,
Reducing defect levels in the III–V semiconductor dependent on the thickness of the nucleation layer.
materials that can generate light is key to successful The researchers explain: “With a thinner LT-InP, more
lasing with high efficiency. Shi and Klamkin used a pinholes appear on the surface due to an inferior
range of techniques to reduce the surface defect den- surface coverage following the InP nucleation although
sity to 4.5x107/cm2, along with producing laser diode the surface roughness tends to be lower. In contrast, a
structures aimed at the 1550nm infrared optical fiber better coverage together with apparent step flows can
communications range. Defects such as misfit (MD) be obtained with the thicker InP nucleation, yet the
and threading (TD) dislocations arise from lattice and surface defect density is higher, on the order of
thermal mismatches between the various material lay- 109/cm2 , which can be attributed to the higher
ers being grown. possibility of MDs evolving into TDs with the thicker
The researchers point to “the ever-important need for LT-InP nucleation.”
on-chip light sources for high-capacity silicon photonic Shi and Klamkin settled on a LT-InP thickness of
transceivers for hyperscale data centers and sensing 30nm as an optimum.
applications”. Other potentials include microwave The effect of dislocation filtering was also studied,
photonics, free-space laser communication, and light using strained-layer superlattices (SLSs). Four such
detection and ranging (LiDAR) based on III–V lasers, SLSs were grown separated with 300nm HT-InP. The
photodetectors, modulators and transistors. SLS structure consisted of 10 pairs of 13nm/19nm
Shi and Klamkin used a gallium arsenide (GaAs)-on- InGaAs/InP. Again there was a trade-off between
V-grooved Si (GoVS) template created by metal-organic undesirable features — at low SLS growth temperature
chemical vapor deposition (MOCVD). The InP was the surface roughness of a final 500nm n-InP layer
Figure 1. (a) Schematic of laser epistructure. (b) Room-temperature CW lasing spectrum at 250mA injection
current – primary lasing peak at ~1593nm. Inset: 70°-tilted scanning electron microscope image of as-cleaved
facet. (c) Temperature-dependent power-current curves under CW pumping.
Figure 2. (a) Schematic of 1µm InP layer regrown on graded InGaAs buffer. (b) Close-up view of the
InP/In0.4Ga0.6As. (c) 10µmx10µm AFM image after 1µm InP regrowth, with some pinholes identified.
increased; high-temperature SLS growth, on the other larger series resistance than lasers realized on conduc-
hand, tended to generate stacking faults. tive InP substrates (1.7Ω on Si and 0.8Ω on InP).”
Surface roughness as low as 3.79nm root-mean-square The devices on silicon may also suffer from reduced
was measured by AFM with 600°C SLS growth. Before heat dissipation arising from defects at InP/GaAs
SLS growth, the defect density was of the order 1010/cm2. interfaces and residual stain in the InP buffer. Despite
By varying the InGaAs composition, surface defect the reduced performance, Shi and Klamkin hope their
densities could be reduced to 7.9x107/cm2, at the cost work “advances the field toward the monolithic integ-
of a rougher surface with a number of ‘hillocks’. ration of InP-based on-chip light sources in the SiPh
Shi and Klamkin also produced a laser structure platform.”
using an InP/Si pseudo-substrate with 1.15x108/cm2 The researchers also reduced defect densities earlier
defect density to grow seven 6.3nm on in the growth by transitioning from the GaAs
In0.73Ga0.27As0.85P0.15 quantum wells separated by 8nm template to an In0.4Ga0.6As buffer before growing an
In0.73Ga0.27As0.52P0.48 barriers (Figure 1). Fabry–Perot InP buffer using the three-step process (Figure 2). The
ridge-waveguide laser diodes were fabricated. The LT and HT values were 495°C and 600°C, respectively.
wafer was thinned and cleaved into laser bars before A relatively thin 1.8µm InGaAs buffer was found to
mounting on a ceramic carrier for testing. have a defect density of 2x108/cm2, compared with
The continuous-wave (CW) laser threshold current of just 2x106/cm2 for a structure grown on pure GaAs
2.05kA/cm2 for a 20µmx1000µm device is described as substrates. The defect density in three-step InP buffers
“reasonable”. The output power reached 18mW/facet grown on the structure was 4x108/cm2, a factor of two
without coatings. The CW operation was possible up to lower than with direct growth on GoVS. Increasing the
65°C. Comparison devices produced on InP substrate HT to 650°C reduced the defect density to 5x107/cm2
had a threshold of 0.675kA/cm2 and CW operation was in one sample. Adding four SLS structures separated by
maintained up to 95°C. Wall-plug efficiencies of 2.7% 250nm HT-InP layers reduced the dislocation density
were achieved for the device on silicon, compared with to 4.5x107/cm2 for the final 500nm InP surface layer.
15% on InP. Shi and Klamkin comment: “Although the surface is
Shi and Klamkin found red-shift effects at higher rougher for the InP buffer on the graded InGaAs layer,
current injection due to self-heating. The researchers improved laser characteristics can be anticipated due
comment: “The heating originates from the reduced to the lower defect density.” ■
injection efficiency on silicon as a result of the residual https://doi.org/10.1063/1.5127030
threading dislocations inside the active region and the Author: Mike Cooke
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U
niversity of California Santa Barbara (UCSB) in The researchers are keen to combat antibiotic-resist-
the USA has been using silicon carbide (SiC) ant bacteria such as Clostridium difficile (C. diff.),
substrates to grow aluminium gallium nitride which is indeed difficult to kill using chemical methods.
(AlGaN) structures aimed at 278nm deep ultraviolet By contrast, UV disinfection reduced C. diff. levels by
(UV-C, 100–280nm wavelength) light-emitting diodes 30%, according to University of North Carolina
(LEDs) [Burhan K. SaifAddin et al, ACS Photonics, researchers in 2010.
7 (2020), 3, p554]. The researchers used surface Fabricating efficient UV-C LEDs has been challenging
roughening of thin-film flip-chip devices to boost due to a number of factors. Material quality can be
light-extraction efficiency (LEE) by a factor of 3 over improved by using SiC rather than sapphire, due to a
smooth-faced LEDs. closer lattice and thermal expansion match. However,
“The ability to grow AlGaN LEDs on SiC with low TDD UV-C light is strongly absorbed in SiC, unlike sapphire,
[threading dislocation density] opens new ways to due to its narrower bandgap. Indeed, sapphire is often
fabricate high-brightness, high-power UV LEDs with used for UV-C LEDs for this reason.
high LEE,” the team comments. The 260–280nm Low-pressure metal-organic chemical vapor deposition
wavelength range enables efficient disinfection by was carried out on 2-inch 6H SiC on the silicon face of
breaking up DNA and RNA molecules of pathogens. a c-plane (0001) crystal orientation. The AlGaN layers
Figure 1. (a) Schematic of the UV-C LED structure. (b) APT 3D reconstruction of active layer showing EBL layer
and four MQWs; (c) 1D concentration profile extracted from APT reconstruction along [0001] direction.
Sampling volume dimension 20nmx20nmx50nm from dotted rectangle in (a).
Figure 2. (a) EQE as function of current density for different 278nm UV LEDs processed from same epitaxial
sample. (b) Unflipped UV LED on SiC schematic with p-side up. (c,d) Thin-film flip-chip (TFFC) UV LED
(area ~0.1mm2), (c) before and (d) after surface roughening.
began with a 3.2µm AlN buffer grown in steps at was removed using a sulfur hexafluoride plasma etch.
1200°C and 1000°C (Figure 1). The Al content was The team used potassium hydroxide solution to
reduced with an 1100nm Al0.80Ga0.20N interlayer, and roughen the flipped AlN light-emission surface,
then 550nm n-Al0.60Ga0.40N grown at 1175°C. The increasing light output by reducing reflection back into
multi-quantum well (MQW) region consisted of four the LED material. Also, the p-GaN thickness was
pairs of 2.7nm/9nm Al0.39Ga0.61N/Al0.60Ga0.40N reduced as much as possible, since the material is
wells/barriers. The structure also included an AlGaN absorbing of UV-C radiation. These two measures,
electron-blocking layer (EBL). along with increasing the reflectivity of the p-contact,
The AlN buffer was crack-free due to a “novel substrate are estimated to increase the light-extraction efficiency
pretreatment” (annealing in ammonia/hydrogen at by a factor of 3 over smooth-surface devices.
1250°C) and a multi-step 3x(3D/2D) growth process At 95mA injection current, the roughened UV-C LED
reported by UCSB in 2018. The AlN buffer also achieved had 7.6mW (82mW/mm2) light output power and
a reduced threading dislocation density of ~109/cm2. 1.8% external quantum efficiency. The slope efficiency
The researchers used atomic probe tomography was 89µW/mA. The turn-on voltage was 4.3V. The LEE
(APT) to study the material, in what the team claims was estimated at 33%, the highest reported for AlGaN
was its first use on UV-LED structures. LEDs, the team claims. ■
The material was then fabricated into thin-film flip-chip https://dx.doi.org/10.1021/acsphotonics.9b00600
devices in TO-39 headers. The SiC growth substrate Author: Mike Cooke
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GaN-on-silicon
platform for low-cost
high-power electronics
Mike Cooke reports on recent research towards devices for high-voltage and
high-frequency power switching and RF wireless transmission amplification.
A
n interesting recent feature of gallium nitride Dual-layer silicon nitride threshold
(GaN) electronic development is the use of sili- engineering
con substrates, often in the form of commercial Researchers in China, Hong Kong, USA and Canada
epitaxial wafers from suppliers like China-based Enkris have used two silicon nitride (SiNx) layers on GaN
Semiconductor or Japan’s NTT Advanced Technology HEMTs to push the threshold 1V in the positive direc-
Corp. It is almost understood that, to compete on cost, tion, while reducing off-state leakage and maintaining
the devices will need to be deployed on silicon, and on-current [Wei-Chih Cheng et al, Semicond. Sci.
many research papers now do not even bother Technol., vol35, p045010, 2020]. The dual-layer SiNx
rehearsing the reasons or challenges. The main acts as a stressor, depleting the 2DEG channel under
reasons are low material costs and availability of the gate, and as passivation to reduce off-state leakage
large-diameter wafers for mass production. Challenges through the AlGaN barrier layer. Although the
include higher defect levels arising from mismatches in presented devices were all normally-on, more
terms of the crystal lattices and thermal expansion of positive threshold voltage (Vth) could eventually lead
silicon and III-N materials. to normally-off transistors.
GaN high-electron-mobility transistors (HEMTs), The team involved researchers from China’s Southern
also known as heterostructure field-effect transistors University of Science and Technology (SUSTech),
(HFETs), are being developed for high-voltage, Hong Kong University of Science and Technology
high-density, high-frequency power switching and (HKUST–Washington State University in the USA,
radio-frequency (RF) wireless transmission amplification. University of British Columbia in Canada, GaN Device
Normally-on or ‘enhancement-mode’ (E-mode) Engineering Technology Research Center of
transistors are particularly sought for reduced power Guangdong, China, and China’s Key Laboratory of
consumption and enabling fail-safe high-voltage the Third Generation Semi-conductor.
power switching operation. Also, the normally-off mode The epitaxial material used for the transistors was
simplifies gate-driver circuit design. The high voltage grown by metal-organic chemical vapor deposition
and power handling is based on GaN’s high critical (MOCVD) on 6-inch-diameter <111> Si at Enkris
electric field before breakdown. Semiconductor. The devices (Figure 1) were electrically
The predominant n-channel devices that have isolated using inductively coupled plasma (ICP) mesa
been developed largely depend on the creation of etching. Annealed titanium/aluminium/titanium/gold
‘two-dimensional electron gas’ (2DEG) channels, (Ti/Al/TI/Au) formed the ohmic source-drain contacts.
which arise near the interface between GaN and a The gate consisted of patterned nickel/gold (Ni/Au).
barrier layer, often aluminium gallium nitride (AlGaN). The two layers of SiNx were deposited using dual-
The 2DEG occurs due to band-bending effects arising frequency plasma-enhanced CVD (PECVD). The low-
from contrasts in the charge distribution in the chemi- stress passivation layer has an unintentional tensile
cal bonds holding the Ga, Al and N atoms together. stress of 0.3GPa. The layer used a process avoiding
Without special measures, the 2DEG channel conducts the low-frequency plasma excitation step, to reduce
when the gate potential is 0V, giving a normally-on surface damage from nitrogen ion bombardment.
‘depletion-mode’ (D-mode). The addition of low-frequency plasma excitation for
Here, we look at recent developments using the the second layer produced a high-compressive-stress
GaN/Si platform. –1GPa film.
Figure 1. Device structure of AlGaN/GaN HEMT showing gate (Lg), source-to-gate (Lsg), and gate-to-drain
(Lgd) lengths/spacings. Channel consisted of unintentionally doped GaN (i-GaN).
Figure 3. Schematics of (a) bare-bones as-grown device A, (b) device B with etched recessed gate, and
(c) device C with Mg diffused gate stack after etching treatment.
Magnesium thermal diffusion for p-gates The device was based on epitaxial material with
South China University of Technology has developed a 4.7μm buffer, 300nm undoped GaN channel, 15nm
simplified fabrication process for normally-off AlGaN- Al0.15Ga0.85N barrier, 2nm GaN cap layers on silicon.
barrier GaN-channel HEMTs with a p-type gate stack The transistor fabrication began with 5 seconds of ICP
[Lijun Wan et al, Appl. Phys. Lett., vol116, p023504, etch in the gate region, before depositing a 50nm layer
2020]. Introducing p-type material above the channel of Mg with electron-beam evaporation. The underlying
in the gate region of the device is one technique for AlGaN was p-type doped with the Mg by rapid thermal
depleting the 2DEG, cutting off current flow at 0V gate annealing at 600ºC for a minute. Further annealing in
potential. air at 250ºC for a minute created a magnesium oxide
The p-type doping under the gate electrode was (MgO) passivation layer.
achieved by magnesium (Mg) thermal diffusion rather The source-drain ohmic contacts consisted of
than the more usual inclusion as a precursor in the annealed Ti/Al/Ni/Au. Mesa etching with ICP formed
epitaxial material growth process. The team sees their the electrical isolation of the devices. A Ni/Au gate
work as “commercially promising” for manufacture of electrode on the MgO completed the transistor.
normally-off HEMTs with low gate leakage. The method The rapid ICP etch before Mg deposition roughens the
successfully increased the Vth into positive values, surface and introduces defects, allowing the metal
creating a normally-off device. atoms to penetrate/diffuse more deeply into the AlGaN
barrier layer in the gate region during the thermal
anneal. Atomic force microscopy (AFM) suggested that
the etch depth was around 6nm, removing the GaN
cap and partially etching and recessing the AlGaN.
Three device types were tested (Figure 3): A was a
conventional HEMT without ICP etch or Mg diffusion;
B was a HEMT with ICP etch, recessing the gate, but
no Mg in the gate region; and, finally, C had the full
gate stack with ICP etch and Mg diffusion.
The Vth for transistors A-C, in order, were –1.5V,
–0.4V and +1.4V. The corresponding peak transcond-
uctances were 68mS/mm, 105mS/mm and 97mS/mm.
Although the gate control, as represented by the peak
transconductance, fell back somewhat for device C, the
value was still higher than for the bare-bones HEMT A.
The process did hit the drain saturation current from
275mA/mm and 300mA/mm for devices A and B,
Figure 4. Gate current density (IGS) as function of respectively, with C only managing 173mA/mm. The
voltage (VGS) for devices A–C. gate potential in these measurements was +3V. The
20ms to
achieve 90%
drain current
recovery,
whereas O3
oxidant took
~0.1ms to
achieve 90%
drain current
recovery, an
extraordinary
200x potential
improvement,”
the team
reports.
The reduced
current collapse
of the O3 and
H2O oxidant
devices, com-
pared with the
unpassivated
Schottky HFET,
was maintained
at 150ºC high
temperature.
Indeed, the
passivated
devices showed
reduced current
collapse, while
the Schottky
HFET’s per-
formance wors-
ened further.
Devices where
the O3 was
applied in two
pulses between
the Hf pulse in
the ALD
process showed
“near-ideal
behavior”,
Figure 6. DC/RF dispersion: gate lag at (a) room temperature and (b) elevated temperature, according to the
150ºC. researchers.
Figure 7. Schematic of (a) E-mode GaN pFET (LGS/LG/LGD = 4/2/4μm) and (b) energy band diagram at gated
region of buried p-channel with 0V (OFF) and beyond threshold (ON) gate potentials (VGS).
As has been seen above, devices with n-type channels contacts evaporated onto the p-GaN, which had previ-
with negatively charge carriers (electrons) have been ously been subjected to a 5-minute buffered oxide etch,
intensively developed in recent years, but the creation presumably to improve the surface and remove
of p-channels would enable complementary integrated contaminants. The gate recess was defined by a
circuit (IC) designs, which would further reduce power 200nm PECVD silicon dioxide (SiO2) hard mask, which
loss in logic control sys-
tems. Although some
progress has recently
been made in developing
an analogous two-
dimensional hole gas
(2DHG) for p-channels,
effective devices remain
to be achieved. The
HKUST work focuses
instead on using p-GaN
material achieved using
magnesium doping.
The GaN-on-Si material
included ~12nm AlGaN
barrier and ~85nm p-
GaN top layer. The
undoped GaN buffer
was ~4.5μm thick. The
structure was found to
have a hole sheet density
of 1.23x1013/cm2 and
mobility 10.2cm2/V-s,
according to Hall meas-
urements.
The HKUST p-channel
devices were fabricated
with 500ºC-annealed
Ni/Au ohmic source–drain Table 1. Benchmark of p-channel GaN FETs.
also served as surface passivation. The p-GaN recess The on-resistance for the E-mode device was a
was formed using ICP RIE. “relatively large” 2.4kΩ-mm at low drain bias. This
An oxygen plasma treatment increased the surface reduced somewhat at –5V drain to 1.6kΩ-mm. The
roughness at the bottom of the recess from 0.36nm maximum drain current was 6.1mA/mm at –10V drain.
root-mean-square to 0.41nm, according to atomic The off-current with 0V gate was 1.2x10–7mA/mm.
force microscopy. The recess depth was found to be The team sees this low off-current as “delivering an
about 54nm, leaving ~31nm of p-GaN material above ultra-low static power consumption required in CMOS
the AlGaN barrier for the channel. logic gates.”
The gate structure was completed with 20nm The researchers compared their device with others
ALD aluminium oxide (Al2O3) insulation and 400ºC- previously presented in the scientific literature (Table 1).
annealed Ni/Au metal electrode. The electrical isolation
of the devices was from fluorine ion implantation Hydrogen-terminated diamond transistors
rather than mesa etching. The researchers used École polytechnique fédérale de Lausanne (EPFL) and
fluorine implant to avoid current leakage along rough Lake Diamond SA in Switzerland claim the first p-chan-
mesa sidewalls. The implant occurred between the nel hydrogen-terminated diamond transistors (HTDTs)
Al2O3 and gate metal deposition steps. on GaN-on-Si templates that demonstrate high-power
The device demonstrated a Vth of –1.7V, giving device performance comparable with other HTDTs on
normally-off enhancement-mode behavior at 0V gate. polycrystalline and even monocrystalline diamond
The oxygen plasma treatment enabled the negative [Reza Soleimanzadeh et al, IEEE Electron Device Letters,
threshold — without the treatment, the device became vol41, p119, 2020].
depletion-mode with the threshold at +2.2V. The The researchers suggest that the integration of
on-current of the enhancement-mode device was p-channel HTDTs with n-channel GaN transistors opens
67% that of the depletion-mode transistor without “a pathway for future complementary power switch
oxygen plasma treatment. and logic applications”. The diamond layer is also
thermally conductive,
allowing improved
thermal management
of GaN devices in
high-power-density
applications. The
team sees the poten-
tial for complemen-
tary logic operation,
gate drivers and
complementary
power switches
in integrated
power inverters and
converters.
The researchers
used an AlGaN
GaN-on-Si template
as used for the fabri-
cation of n-channel
HEMTs. The template
was prepared for
diamond deposition
by applying layers of
30nm SiN and 5nm
Si. These layers were
designed to protect
the template mater-
Figure 8. (a) Three-dimensional (3D) optical microscope image of fabricated HTDT, ial from the harsh
constructed using focus stacking. (b) Schematic of HTDTs. (c) Top-view SEM image of diamond deposition
diamond surface. (d) Cross-sectional optical microscope image of diamond layer environment, along
showing larger grain sizes at top. with enhancing
A
s announced in February, STMicroelectronics of inventions narrowly related to power applications,” says
Geneva, Switzerland is collaborating with Taiwan Remi Comy PhD, Knowmade’s technology and patent
Semiconductor Manufacturing Corporation analyst, Compound Semiconductors and Electronics.
(TSMC, the world's biggest silicon wafer foundry) to Indeed, TSMC was actively filing GaN-on-Si patents for
accelerate the development of gallium nitride (GaN) power applications between 2012 and 2017 and has
technology for power applications, and more specifically strongly focused on the USA (20+ granted patents).
for automotive applications (converters and chargers The patent portfolio protects technological approaches
for hybrid and electric vehicles). providing improved GaN-on-Si buffer resistivity, using
With this recent manufacturing partnership, STMicro- three main approaches:
electronics has joined the series of companies that ● p-type conductivity dopants in graded buffer layers
have trusted TSMC for volume production of GaN and ungraded buffer layers (US patent 8,791,504);
power devices, including market leader GaN Systems, ● diffusion-blocking layer between the buffer layer and
as well as VisIC and Navitas Semiconductor (focusing the silicon substrate (US patent 9,245,991);
on GaN power IC technology). STMicroelectronics will ● multi-strained superlattice structures (SLS) to
begin by sampling discrete GaN power devices, to be overcome the limitations due to carbon doping of the
followed soon by GaN IC products based on TSMC’s buffer layers (US patent 10,109,736).
GaN-on-Si process technology. Next, TSMC focused its patenting activity on removing
TSMC’s GaN-on-Si technology was reviewed in the breakdown voltage limitations due to the surface
Knowmade’s ‘GaN-on-Si Patent Landscape Analysis’ gate–drain region, inserting buried dielectric portions in
(released in January), which covers about 40 patent the AlGaN barrier (Figure 1a), in addition to the use of
families (inventions) related to this technology, field-plate structures (Figure 1b) and an AlGaN barrier
regrouping more than 130 patents filed worldwide, with Al-graded composition (US patent 10,522,532).
mainly in US (70+) and China (25+). Interestingly, TSMC’s latest GaN-on-Si developments
“TSMC has leading GaN-on-silicon manufacturing for power applications focused on the fabrication of
expertise, and we have identified at least 12 key GaN power integrated circuits (ICs) via US patent
Figure 1: (a) GaN HEMT with one or more dielectric plug portions in the barrier between the gate and the drain
(US patent 8,884,308). (b) Substrate breakdown voltage improvement for group III-nitride on silicon substrate
(US patent 9,111,904).
9,793,389, related to the isolation of adjacent GaN-on-Si and Atomic Energy Commission (CEA), focused on the
power devices, and US patent 10,522,532 related to development of GaN power devices on 200mm silicon
the formation of through-GaN vias (TGVs). substrates, in view of establishing a pilot manufac-
In the ‘GaN-on-Si Patent Landscape Analysis’, turing line in 2020 in STMicroelectronics’ foundry in
Knowmade also analyzed the patent portfolio of Tours, France.
STMicroelectronics, which is still strengthening its CEA is also a well-established IP player in the
IP position in the power GaN patent landscape. In GaN-on-Si patent landscape, with more than 40
2017–2018, ST focused on GaN device technology, patented inventions. Over the last three years, it has
especially normally-off transistor structures (Figure 2). intensified its GaN-on-Si patenting activity in the field
STMicroelectronics’ normally-off transistor structures of power applications with six additional inventions.
(US patents 10,516,041, 10,566,450 and 10,522,646) CEA first focused on enhancement-mode device technol-
are based on a tri-layer epitaxial stack NiO/AlGaN/GaN, ogy (Figure 3a) and then focused on the epi-structures
the selective removal of NiO in the gate region and the in order to enhance the vertical breakdown voltage. Its
deposition of a gate dielectric (AlN, Al2O3 or SiO2) on recent GaN-on-Si patenting activity also includes an IP
the AlGaN barrier (with or without recess). The buffer collaboration with automotive player Renault regarding
region may include a first carbon-doped buffer layer power GaN device technology (Figure 3b).
for increasing the breakdown voltage and a second “Following the R&D collaboration between STMicro-
p-type buffer layer for limiting the degradation of electronics and CEA since 2018, and the recent
dynamic on-resistance due to the first buffer layer. announcement of partnership between STMicroelec-
It can be combined with the presence of a sloped field tronics and TSMC, we expect an acceleration of their
plate in order to further reduce dynamic on-resistance respective patenting activity on power GaN-on-silicon in
phenomenon, implemented with the advantageous the next months,” says Remi Comyn of Knowmade. ■
method described in US patent 10,050,136. www.tsmc.com
Previously — in 2018 — STMicroelectronics started a www.st.com
joint R&D program with The French Alternative Energies www.knowmade.com/downloads/gan-power-rf-patent-monitor
Figure 3: (a) Method for forming an implanted area under the gate region, for a normally-off heterojunction
transistor (US patent 10,164,081). (b) III-N heterojunction transistor with a vertical structure (WO patent
application 2018/100262).
R
esearchers based in Germany and Italy have ε form of Ga2O3 decomposes above 700°C. This
been exploring the growth of ε-polytype gallium restricts the thermal budget of processes involving the
oxide (ε-Ga2O3) combined with gallium nitride material.
(GaN) on sapphire substrates with a view to deploy- The team from Fraunhofer Institute for Applied Solid
ment in high-electron-mobility transistors (HEMTs) State Physics (IAF) in Germany, University of Parma in
[Stefano Leone et al, Journal of Crystal Growth, Italy, Institute of Materials for Electronics and Magnetism
vol534, p125511, 2020]. (IMEM-CNR) in Italy and Albert-Ludwigs Universität
GaN-based high-frequency and high-voltage power Freiburg in Germany focused on growth using
devices are moving to wider commercial deployment metal-organic chemical vapor deposition (MOCVD)
in AC–DC inverters, power supplies, 600V switches, since it is the technique most favored in manufacturing.
and the generation of communications and radar The researchers claim that their work is the first inves-
radio signals. The combination of GaN with ferroelectric tigation of GaN/ε-Ga2O3 MOCVD.
ε-Ga2O3 could lead to interesting further electronic The team employed two separated MOCVD reactors for
opportunities. deposition of ε-Ga2O3 and GaN. The material surfaces
The ε-Ga2O3 material also has a strong spontaneous were exposed to air on transfer between the chambers.
charge polarization, arising from the crystal structure The GaN deposition used trimethyl-gallium (TMGa) and
and stronger ionic character of the chemical bond. ammonia (NH3) precursors in hydrogen carrier gas.
Such polarization could give rise to two-dimensional The substrate was mainly on-axis sapphire: (001)
electron gas (2DEG) HEMT channels with very high aluminium oxide (Al2O3). The ε-Ga2O3 was deposited in
carrier density. There are, of course, also strain- a cold-wall system at 610°C. The precursors for this
dependent piezoelectric effects to be expected. were TMGa and water (H2O) in hydrogen carrier gas.
Ferroelectricity has mainly been deployed in non-volatile The GaN growth rate at 1050°C was around
memory devices up to now, but recent research has 1µm/hour. The ε-Ga2O3 deposition was at about half
also used the property to create ‘negative capacitance’ that rate, 500nm/hour. Some samples included a
gate stacks. Such negative capacitance enables the 10nm silicon nitride (SiN) passivation layer for studying
subthreshold swing to go lower than the standard electronic properties towards the fabrication of HEMTs.
thermal limit of 60mV/decade. Such sharply switching The SiN was deposited using inductively coupled
devices are of interest in silicon electronics for plasma CVD, using silane (SiH4) and NH3.
low-voltage operation and low power consumption. The ε-Ga2O3 polytype has an orthorhombic (pseudo-
Of course,
GaN-based
electronics
is not so
interested
in low volt-
age.
One factor
that has to
be consid-
ered is
that the
ε polytype
crystal
structure is
more stable Figure 1. SEM studies of 5-minute ε-Ga2O3 MOCVD on (left) on-axis and (right) 4° off-cut GaN on
and the sapphire.
Figure 2. (left) Capacitance versus voltage and conductance/angular frequency (G/ω) versus voltage and
(right) CV-derived carrier density versus depth profile.
hexagonal) crystal structure with nominal 8.8% lattice SiN/ε-Ga2O3 barrier thickness of 25nm. The SiN passi-
mismatch with GaN. The researchers also investigated vation was 10nm.
depositing the ε-Ga2O3 before the GaN — the drawback The growth time of the ε-Ga2O3 was 17 minutes.
being that ε-Ga2O3 begins a transition to β-Ga2O3 at 700°C, Thinner layers with shorter growth times down to
which completes at 900°C. Thus, with ε-Ga2O3-first 3 minutes were less uniform and consequently per-
deposition the researchers reduced the GaN growth formed less well in CV measurements. Difficulties in
temperature to 690°C. Although the GaN-on-ε-Ga2O3 making Ohmic contacts has inhibited the performance
(GaN/ε-Ga2O3) surface was smooth, there were sev- of Hall measurements and hence the assessment of
eral defects visible in microscopic inspection. carrier mobility. Sheet resistance values were relatively
Depositing the GaN at high temperature (1050°C) high: 1300–2200Ω/square and 3300Ω/square for
converted the ε material to β. according to x-ray analysis. on- and off-axis samples, respectively.
By contrast, the low-temperature GaN/ε-Ga2O3 The sheet carrier density was estimated to be
remained in the ε phase. The crystal quality of the 6.4x1012/cm2, using the CV data. This value was well
overlying GaN is described as “poor” in both cases, on short of theoretical expectations of 1.2x1014/cm2,
the basis of large full-width at half-maximum (FWHM) using Schrödinger–Poisson modeling. The modeled
values for various x-ray rocking curve peaks. The low- values for AlN and Al0.25Ga0.75N barriers are
temperature sample was particularly poor. 6.5x1013/cm2 and 1.1x1013/cm2, respectively. The
Although the growth of ε-Ga2O3 on GaN was better, higher expectation for ε-Ga2O3 barriers rests on a
the deposition tended to begin with 3D islands that higher spontaneous charge polarization of the crystal
later began to coalesce. Such behavior could lead to structure and the more ionic character of the chemical
decent quality in thick layers, but the researchers were bonds.
more interested in creating thin ε-Ga2O3 on GaN The suppression of the 2DEG sheet carrier density in
heterostructures with a view to fabrication of HEMTs. the experimental samples relative to theoretical expec-
To encourage 2D layer-by-layer growth of ε-Ga2O3 the tations could be due to factors such as non-optimized
team tried using 4° off-cut (0001) sapphire substrates, morphology and high defect densities. Despite this,
giving the GaN surface a step-and-terrace texture. the team sees their results as being “very promising”.
“The coalescence in this sample seems to be much One key component in future HEMT development
more effective than in the on-axis samples,” the would be the fabrication of low-contact-resistance
researchers observe from scanning electron microscope Ohmic source-drain electrodes without exceeding the
(SEM) studies (Figure 1). 700°C thermal limit imposed by the ε-to-β polytype
Capacitance-voltage (CV) analysis of the materials phase transition of the Ga2O3. The team points hope-
detected 2DEG behavior only when the sample was fully to recent work using titanium/gold annealed
capped with SiN passivation. However, there was for three hours at 300°C, which gave low reported
a high level of hysteresis in the curves, ~0.9V, contact resistance on ε-Ga2O3. ■
suggesting the presence of defects or ionized states. https://doi.org/10.1016/j.jcrysgro.2020.125511
A SiN/ε-Ga2O3/GaN structure was found to have a www.imem.cnr.it
carrier density profile consistent with a combined Author: Mike Cooke
T
he ever-growing mobile data transfers in the AlN-based nitrides as the piezo-active layer. Within the
wake of 5G require the use of more and higher five years of the project, the researchers succeeded in
frequency ranges, all of which need to be growing highly crystalline AlScN layers and realizing
accommodated within a single mobile device. The surface acoustic wave (SAW) resonators that meet the
demands on radio frequency (RF) components are increasing requirements of the industry.
hence constantly increasing. The Fraunhofer Institute for For growth of the material, which is also promising
Applied Solid State Physics IAF of Freiburg, Germany for other power electronic applications, a modern
has developed novel, compact and energy-efficient magnetron-sputtering infrastructure was established
high-frequency/high-bandwidth RF filters to meet at Fraunhofer IAF. The project was funded by a
those needs (‘Enhanced electromechanical coupling in ‘Fraunhofer Attract’ excellence stipend program and
SAW resonators based on sputtered non-polar was successfully completed in January under the
– –
Al0.77Sc0.23N (1120)1120 thin films’, Appl. Phys. Lett. leadership of Dr Agne Zukauskaite.
116, 101903 (2020)). During the project ‘PiTrans —
AlScN — Development of novel piezoelectric materials’ Potential and challenges of AlScN
(running from 2015 to 2020) the researchers managed AlScN remains the most promising new material to
to grow aluminum scandium nitride (AlScN) with the replace conventional aluminum nitride (AlN) in RF filter
required industrial specifications and to realize novel applications inside mobile phones. By introducing
electroacoustic devices for smartphones. scandium (Sc) into AlN, the electromechanical coupling
The amount of RF components built into a single and piezoelectric coefficient of the material is increased,
smartphone has increased significantly over the past enabling a more efficient mechanical-to-electric energy
years and there is no end in sight. Predicting this trend conversion. This allows the production of much more
in 2015, the PiTrans project set out to develop and efficient RF devices. However, the instability of the
produce improved RF piezo-transducers with ternary piezoelectric AlScN crystal phase has so far been a
problem for industrial use of the material,
as segregation of wurtzite-type AlN and
cubic ScN usually occurs during growth.
“Back in 2015, we knew the potential of
AlScN, but we needed to find the right condi-
tions to grow it in a stable and scalable
process,” recalls Zukauskaite.
suppliers’ directory
Index
1 Bulk crystal source materials p88 14 Chip test equipment p91
2 Bulk crystal growth equipment p88 15 Assembly/packaging materials p92
3 Substrates p88 16 Assembly/packaging equipment p92
4 Epiwafer foundry p89 17 Assembly/packaging foundry p92
5 Deposition materials p89 18 Chip foundry p92
6 Deposition equipment p90 19 Facility equipment p92
7 Wafer processing materials p90 20 Facility consumables p92
8 Wafer processing equipment p90 21 Computer hardware & software p92
9 Materials and metals p91 22 Used equipment p92
10 Gas & liquid handling equipment p91 23 Services p92
11 Process monitoring and control p91 24 Consulting p93
12 Inspection equipment p91 25 Resources p93
13 Characterization equipment p91
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CrystAl-N GmbH
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