1100 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO.

5, MAY 2006

Design of Charge Pump Circuit With

Consideration of Gate-Oxide Reliability
in Low-Voltage CMOS Processes
Ming-Dou Ker, Senior Member, IEEE, Shih-Lun Chen, Student Member, IEEE, and Chia-Shen Tsai

Abstract—A new charge pump circuit with consideration of gate-

oxide reliability is designed with two pumping branches in this
paper. The charge transfer switches in the new proposed circuit
can be completely turned on and turned off, so its pumping ef-
ficiency is higher than that of the traditional designs. Moreover,
the maximum gate-source and gate-drain voltages of all devices in
the proposed charge pump circuit do not exceed the normal oper-
ating power supply voltage (VDD). Two test chips have been imple-
mented in a 0.35- m 3.3-V CMOS process to verify the new pro-
posed charge pump circuit. The measured output voltage of the
new proposed four-stage charge pump circuit with each pumping
capacitor of 2 pF to drive the capacitive output load is around 8.8 V
under 3.3-V power supply (VDD = 3 3 V), which is limited by
the junction breakdown voltage of the parasitic pn-junction in the
given process. The new proposed circuit is suitable for applications
in low-voltage CMOS processes because of its high pumping effi-
ciency and no overstress across the gate oxide of devices.
Index Terms—Body effect, charge pump circuit, gate-oxide reli-
ability, high-voltage generator, low voltage.

Fig. 1. Four-stage (a) diode and (b) Dickson charge pump circuits.
I. INTRODUCTION
HARGE pump circuits have been often used to generate
C dc voltages those are higher than the normal power supply
voltage (VDD) or lower than the ground voltage (GND) of the
enough, and can be ignored from (1). Because is
usually with the same voltage level as the normal power supply
chip. Charge pump circuits are usually applied to the nonvolatile voltage (VDD), the voltage fluctuation of each pumping node
memories, such as EEPROM or flash memories, to write or can be simply expressed as
to erase the floating-gate devices [1]–[4]. In addition, charge
pump circuits had been used in some low-voltage designs to
VDD (2)
improve the circuit performance [5], [6]. The four-stage diode
charge pump circuit using the pn-junction diodes as the charge
Hence, the output voltage of the four-stage charge pump circuit
transfer devices is shown in Fig. 1(a). The charges are pushed
with diodes can be expressed as
from the power supply (VDD) to the output node ( ), stage
by stage. Thus, the output voltage of the charge pump circuit
can be pumped high. The voltage fluctuation of each pumping VDD (3)
node can be expressed as
where is the cut-in voltage of the pn-junction diode. How-
(1) ever, it is difficult to implement the fully independent diodes in
the common silicon substrate. In other words, the charge pump
circuit with diodes shown in Fig. 1(a) cannot be easily integrated
where is the voltage amplitude of the clock signals, into the standard CMOS process. Therefore, most charge pump
is the pumping capacitance, is the parasitic capacitance circuits are based on the circuit proposed by Dickson [7]–[9].
at each pumping node, is output current, and is the clock Fig. 1(b) shows the four-stage Dickson charge pump circuit,
frequency. If and are small enough and is large where the diode-connected MOSFETs are used to transfer the
charges from the present stage to the next stage. Thus, it can be
Manuscript received June 17, 2005; revised November 4, 2005. easily integrated into standard CMOS processes. However, the
The authors are with the Nanoelectronics and Gigascale Systems Laboratory, voltage difference between the drain terminal and the source ter-
Institute of Electronics, National Chiao-Tung University, 1001 Ta-Hsueh Road,
Hsinchu, Taiwan 30050, R.O.C. (e-mail: mdker@ieee.org). minal of the diode-connected MOSFET is the threshold voltage
Digital Object Identifier 10.1109/JSSC.2006.872704 when the diode-connected MOSFET is turned on. Therefore,
0018-9200/$20.00 © 2006 IEEE
KER et al.: DESIGN OF CHARGE PUMP CIRCUIT WITH CONSIDERATION OF GATE-OXIDE RELIABILITY IN LOW-VOLTAGE CMOS PROCESSES 1101

Fig. 2. (a) Circuit and (b) corresponding voltage waveforms of the four-stage Wu and Chang charge pump circuit.

the output voltage of the four-stage Dickson charge pump cir- enlarged. The auxiliary MOSFETs used to dynamically control
cuit has been derived as the body terminals of the diode-connected MOSFETs [11] may
also generate the substrate current in the floating-well devices.
Four-phase clock generator was applied in the charge pump
circuits to improve pumping efficiency [12]–[15], but the com-
VDD (4)
plex clock generator would consume more power. In [16], [17],
an extra small charge pump circuit, which has more pumping
where denotes the threshold voltage of the diode-con- stages than the main charge pump circuit, was used to control
nected MOSFET . Traditionally, the bulk terminals of the the main charge pump circuit, so the pumping efficiency of the
diode-connected MOSFETs in the Dickson charge pump circuit main charge pump circuit can be enhanced. However, the charge
are connected to ground (GND). The threshold voltage pump circuits [16], [17] occupy larger silicon area than others
of the diode-connected MOSFET becomes larger due to the because of the extra charge pump circuits. In addition, the extra
body effect when the voltage on each pumping node is pumped small charge pump circuit consumes extra power. In [18], the
higher. Therefore, the pumping efficiency of the Dickson charge charge sharing concept was used in the charge pump circuit to
pump circuit is degraded by the body effect when the number of reduce the power consumption. However, the charge sharing
pumping stages is increased. concept requires the special clock generator. The four-stage
Several modified charge pump circuits based on the Dickson charge pump circuit reported by Wu and Chang [19] is shown
charge pump circuit were reported to enhance the pumping in Fig. 2(a). The charge transfer switch (CTS) controlled by
efficiency [10]–[18]. In the triple-well process, the floating-well the dynamic control circuit in the Wu and Chang charge pump
technique [10] or the source-bulk connected devices were used circuit is used to transfer the charges from the present stage
to eliminate the body effect issue on the diode-connected MOS- to the next stage without suffering the limitation of threshold
FETs in the Dickson charge pump circuit. But, the floating-well voltage. Fig. 2(b) shows the corresponding voltage waveforms
technique may generate substrate current in the floating-well of the four-stage Wu and Chang charge pump circuit. When
devices to influence other circuits in the same chip. The the clock signal CLK is low and the clock signal CLKB is
source-bulk connected technique increases the parasitic ca- high during the time interval T1 in Fig. 2(b), the voltage on
pacitance at each pumping node due to the large bulk-to-well node 1 is VDD and the voltage on node 2 is VDD. Because
pn-junction capacitance, so the pumping capacitors have to be transistor MN1 is turned off and transistor MP1 is turned on,
1102 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 5, MAY 2006

Fig. 3. (a) Circuit and (b) corresponding waveforms of the new proposed charge pump circuit with four pumping stages.

the charge transfer switch, MS1, can be completely turned on With the advanced CMOS processes, the thickness of the
to transfer charges from the power supply (VDD) to node 1. gate oxide becomes thinner so the operation voltage of tran-
During the time interval T2, the voltage on node 2 can be sistor must be lowered due to the reliability issue [20]. Thus,
pumped as high as VDD to turn on transistor MN1 and to the gate-oxide reliability issue [21] must be also considered into
turn off transistor MP1. Thus, the charge transfer switch, MS1, the design of charge pump circuits, especially in the low-voltage
can be completely turned off to prevent the charges back to the CMOS processes. In this paper, a new charge pump circuit that
power supply (VDD). The operation of next stages in Wu and has better pumping efficiency but without the gate-oxide relia-
Chang’s charge pump circuit is similar to that of the first stage. bility issue in low-voltage processes is proposed [22]. The new
Because the CTSs can be completely turned on or turned off by proposed charge pump circuit has been successfully verified in
the dynamic control circuits, the pumping efficiency has been a 0.35- m 3.3-V CMOS process.
enhanced with ideal output voltage of VDD. However, the
output stage (MDO) of Wu and Chang’s charge pump circuit II. NEW PROPOSED CHARGE PUMP CIRCUIT
is still a diode-connected MOSFET, so it also suffers the body The circuit and the corresponding voltage waveforms of the
effect issue. Besides, because the maximum voltage difference new proposed charge pump circuit with four stages are shown
of each stage is VDD, all devices of Wu and Chang’s in Fig. 3(a) and (b). To avoid the body effect, the bulks of the
charge pump circuit suffer the high-voltage overstress on their devices in the proposed charge pump circuit are recommended
gate oxides. to be connected to their sources respectively if the given process
KER et al.: DESIGN OF CHARGE PUMP CIRCUIT WITH CONSIDERATION OF GATE-OXIDE RELIABILITY IN LOW-VOLTAGE CMOS PROCESSES 1103

provides the deep n-well layer. Clock signals CLK and CLKB
are out-of-phase but with the amplitudes of VDD. As shown
in Fig. 3(a), there are two charge transfer branches, branch A
and branch B, in the new proposed charge pump circuit. Branch
A is comprised of transistors MN1, MN2, MN3, MN4, MP1,
MP2, MP3, and MP4 with the capacitors C1, C2, C3, and C4.
Branch B is comprised of transistors MN5, MN6, MN7, MN8,
MP5, MP6, MP7, and MP8 with the capacitors C5, C6, C7, and
C8. The control signals of branches A and B are intertwined.
Besides, clock signals of branches A and B are out-of-phase.
When the clock signals of the first and the third pumping stages
in the branch A are CLK, those in the branch B are CLKB. Simi-
larly, when the clock signals of the second and the forth pumping
stages in the branch A are CLKB, those in the branch B are CLK.
Thus, branches A and B can see as two independent charge
pump circuits but their output nodes are connected together. Be-
cause the clock signals of the branch A and those of the branch
B are out-of-phase, the voltage waveforms of nodes 1–4 and Fig. 4. Simulated waveforms on CLK, CLKB, nodes 1–8, and V in the new
proposed four-stage charge pump circuit.
those of nodes 5–8 are also out-of-phase. Hence, branches A
and B can pump the output voltage to high, alternately. The de-
tailed operations of the new proposed charge pump circuit are
to cut off the path from the output node back to node 8. On the
described below.
other hand, is VDD during the time interval T2. Hence,
A. First Pumping Stage the transistor MP4 is turned off and the current path from the
output node back to node 4 is cut off. In addition, the transistor
As illustrated in Fig. 3(b), the clock signal CLK is low and
MP8 is turned on to transfer the charges from node 8 to the
the clock signal CLKB is high during the time interval T1. At
output node.
this moment, the voltage difference between node 1 and
As shown in Fig. 3(b), the gate-source voltage ( ) and gate-
node 5 is VDD. Therefore, transistor MN1 is turned on to
drain voltage ( ) of all MOSFETs in the new proposed charge
transfer the charges from the power supply (VDD) to node 1,
pump circuit do not exceed VDD. Thus, there is no high-voltage
but the transistor MN5 is turned off to cut off the path from
overstress on the gate oxide of the devices in the new proposed
node 5 back to the power supply. Similarly, becomes VDD
charge pump circuit.
during the time interval T2. Transistor MN1 is turned off to cut
off the leakage path from node 1 back to the power supply, but
the transistor MN5 is turned on to transfer the charges from the III. VERIFICATIONS AND DISCUSSIONS
power supply to node 5.
A. Simulations and Comparisons
B. Second and Third Pumping Stages A 0.18- m 1.8-V CMOS device model is used to verify the
In the second stage, when the clock signal CLK is low and design of the new proposed charge pump circuit in HSPICE
the clock signal CLKB is high during the time interval T1, simulation. Fig. 4 shows the simulated voltage waveforms of
and the voltage difference between node 2 and node 6 the new proposed four-stage charge pump circuit with each
are VDD and VDD, respectively. Therefore, transistors MP5 pumping pumping capacitor of 1 pF and 5- A output current.
and MN6 are turned on to transfer the charges from node 5 to The expected waveforms shown in Fig. 3(b) are similar to
node 6, but transistors MP1 and MN2 are turned off to cut off the simulated waveforms shown in Fig. 4. Ideally, the output
the path from node 2 back to node 1. Similarly, and voltage of the new proposed four-stage charge pump circuit
are VDD and VDD during the time interval T2, respectively. with 1.8-V power supply voltage VDD V should be
Transistors MP5 and MN6 are turned off in order to cut off the as high as 9 V . However, due to the parasitic
path from node 6 back to node 5, but transistors MP1 and MN2 capacitance at each pumping node and the loading of the output
are turned on to transfer the charges from node 1 to node 2. The current, the simulated output voltage of the new proposed
operation of the third pumping stage is similar to that of the charge pump circuit is around 8.39 V.
second pumping stage. Fig. 5 shows the simulated output voltages of the proposed
charge pump circuit under different output currents and power
C. Output Stage supply voltages (VDD). When the output current is increased,
As shown in Fig. 3(a), the output nodes of braches A and B the output voltages of the proposed charge pump circuit under
are connected together. When the clock signal CLK is low and different power supply voltages (VDD) are decreased. If the new
the clock signal CLKB is high during the time interval T1, the proposed charge pump circuit only drives the capacitive load,
voltage difference between node 4 and node 8 is VDD. the output voltages of the proposed charge pump circuit under
Therefore, transistor MP4 is turned on to transfer the charges different power supply voltages (VDD) are close to VDD.
from node 4 to the output node, but transistor MP8 is turned off If the supply voltage is too low and the output current is too
1104 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 5, MAY 2006

Fig. 6. Simulated output voltages of the Dickson, Wu and Chang, and the pro-
Fig. 5. Simulated output voltages of the new proposed four-stage charge pump posed charge pump circuits with four stages under different output currents with
circuit under different output currents and power supply voltages (VDD). 1.8-V power supply (VDD = 1:8 V).

high, the proposed charge pump circuit cannot pump the output
voltage high.
The simulated output voltages of the Dickson charge pump
circuit [7], Wu and Chang’s charge pump circuit [18], and the
new proposed charge pump circuit with different output cur-
rents are compared in Fig. 6. Actually, the pumping capacitors
of a charge pump circuit take a great part in silicon area. For fair
comparison, the total pumping capacitors of these charge pump
circuits must be equaled. Therefore, the pumping capacitors in
the proposed charge pump circuit, in Wu and Chang’s charge
pump circuit, and in the Dickson charge pump circuit are set
to 1 pF, 1.6 pF , and 2 pF ,
respectively. As shown in Fig. 6, the output voltages of the
proposed charge pump circuit with different output currents are
much higher than those of other charge pump circuits. Espe- Fig. 7. Simulated output voltages of the Dickson, Wu and Chang, and the pro-
posed charge pump circuits with four stages under different supply voltages
cially, with the higher output current of 30 A, the proposed (VDD) without output current loading.
charge pump circuit still has the better pumping performance
than others. Since the proposed charge pump circuit has two
pumping branches pushing the charges to the output node al- Branches A and B in the new proposed charge pump circuit
ternately, the degradation of the output voltage is smaller while can pump the output voltage alternately, but Wu and Chang’s
the output current increases. In addition, the MOSFET switches charge pump circuit and the Dickson charge pump circuit only
in the new proposed charge pump circuit are fully turned on to pump the charges to the output node per clock cycle. The sim-
transfer the charges, but all MOSFET switches in the Dickson ulated output waveforms of these charge pump circuits with
charge pump circuit and the output stage of Wu and Chang’s 20- A output current are shown in Fig. 8, where is the
charge pump circuit are diode-connected transistors, which amplitude of the output voltage ripple. As shown in Fig. 8,
have the threshold voltage drop problem. Thus, the proposed the output voltage ripple of the proposed charge pump circuit
charge pump circuit has better pumping performance, as shown (0.166%) is much smaller than those of Wu and Chang’s charge
in Fig. 6. pump circuit (0.457%) and the Dickson charge pump circuit
Fig. 7 compares the simulated output voltages of the Dickson, (0.762%). Therefore, the output voltage of the new proposed
Wu and Chang, and the new proposed charge pump circuits charge pump circuit is more stable than those of the other charge
under different power supply voltages (VDD) without output pump circuits. If the output voltage ripple is still large, a low-
current loading. As shown in Fig. 7, the output voltages of these pass filter should be connected to the output node of the charge
three charge pump circuits are degraded when the power supply pump circuit to filter the voltage ripple [23].
voltage is decreased. However, the new proposed charge pump
circuit still has higher output voltages under the lower power B. Silicon Verifications
supply voltage because the proposed charge pump circuit has In this work, two test chips have been fabricated in a 0.35- m
better pumping efficiency. Thus, the proposed charge pump cir- 3.3-V CMOS process to verify the proposed charge pump cir-
cuit is more suitable in low-voltage processes than the prior de- cuit. Fig. 9 shows the simulated output voltages of proposed
signs. charge pump with each pumping capacitor of 2 pF, the Dickson
KER et al.: DESIGN OF CHARGE PUMP CIRCUIT WITH CONSIDERATION OF GATE-OXIDE RELIABILITY IN LOW-VOLTAGE CMOS PROCESSES 1105

Fig. 9. Simulated output voltages of different four-stage charge pump circuits

in the 0.35-m 3.3-V CMOS process under different output currents with the
power supply voltage (VDD) of 3.3 V.
Fig. 8. Simulated output waveforms of the Dickson, Wu and Chang, and the
proposed charge pump circuits of four stages with 20-A output current and
1.8-V power supply (VDD = 1:8 V).
charge pump circuits with each pumping capacitor of 2 pF
under 2-V power supply VDD V , respectively. Similarly,
charge pump circuit with each pumping capacitor of 4 pF, the measured output voltage of the proposed four-stage charge
and Wu and Chang’s charge pump circuit with each pumping pump circuit in Fig. 12 is also limited by the breakdown voltage
capacitor of 3.2 pF in the 0.35- m 3.3-V CMOS process. As of the parasitic pn-junction diode at low output current.
shown in Fig. 9, the proposed charge pump circuit has better
pumping performance. The photographs of these two test chips C. Discussion
are shown in Fig. 10(a) and (b). These two test chips include the Gate-oxide reliability is a time-dependent issue [24], [25].
proposed four-stage charge pump circuit with each pumping The time period during the voltage overstress on the gate oxide
capacitors of 2 pF, the proposed two-stage charge pump cir- is accumulated to induce the oxide breakdown. Hence, the DC
cuit with each pumping capacitor of 2 pF, Wu and Chang’s stress is more harmful to the gate oxide than the short AC stress
four-stage charge pump circuit with each pumping capacitor of (transient stress). The diode-connected MOSFET in the Dickson
2 pF, Wu and Chang’s four-stage charge pump circuit with each charge pump circuit is used to transfer charges from the present
pumping capacitor of 3.2 pF, the Dickson four-stage charge stage to the next stage. When the diode-connected MOSFET
pump circuit with each pumping capacitor of 2 pF, the Dickson is turned off to prevent the charges flowing back to the pre-
four-stage charge pump circuit with each pumping capacitor of vious stage, the voltage across the gate oxide of the diode-con-
4 pF, the proposed four-stage charge pump circuit with each nected MOSFET is around VDD , where is the
pumping capacitor of 4 pF, and the proposed three-stage charge threshold voltage of the diode-connected MOSFET. The diode-
pump circuit with each pumping capacitor of 2 pF. To drive ca- connected MOSFET will suffer serious gate-oxide overstress, so
pacitive load, the measured output voltage of the new proposed the gate oxide of the diode-connected MOSFET may be dam-
four-stage charge pump circuit with each pumping capacitor aged after operation. In Wu and Chang’s charge pump circuit,
of 2 pF is around 8.8 V under 3.3-V power supply voltage not only these diode-connected MOSFETs but also the charge
VDD V . Fig. 11 shows the measured output voltages transfer switches (CTSs) and their control circuits will suffer se-
of the four-stage charge pump circuits with different output rious high-voltage overstress on the gate oxide. In the proposed
currents. The measured results in Fig. 11 is little lower than the charge pump circuit, the gate-oxide reliability issue has been
simulated results in Fig. 9 because of the parasitic resistance considered. The gate-to-source voltages ( ) and gate-to-drain
and capacitance from the test chips, the bonding wires, and the voltages ( ) of devices in the proposed charge pump circuit do
packages. The parasitic resistance and capacitance may results not exceed VDD whenever it is in the normal operation, start-up,
in the overlapping clock signals, which will lower the pumping or turn-off states. Therefore, the proposed charge pump circuit
efficiency. However, similar to the simulation results, the is better for applications in low-voltage CMOS processes.
proposed charge pump circuit has better pumping performance As shown in Figs. 11 and 12, the output voltage of the
than others, as shown in Fig. 11. Besides, the output voltage proposed charge pump circuit will be limited by the breakdown
( 9 V) of the proposed charge pump circuit is limited by the voltages of the parasitic pn-junctions. As the CMOS process is
breakdown voltage of the parasitic drain-to-bulk pn-junction scaled down, the breakdown voltages of the parasitic pn-junc-
diode under the low output current. If the output voltage of tions become lower. Thus, the output voltage limitation of the
the charge pump circuit is larger than the breakdown voltage charge pump circuit will become more serious. In [26], the
of the pn-junction diode, the charges leak through this diode charge pump circuit is designed in the SOI process without
and the output voltage of the charge pump circuit is kept at the limitation of the breakdown voltages of the pn-junctions.
the breakdown voltage. Fig. 12 compares the measured output However, the SOI process is more expensive than the bulk
voltages of the proposed two-stage, three-stage, and four-stage CMOS process. The charge pump circuit consisting of the
1106 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 5, MAY 2006

Fig. 10. Photographs of charge pump circuits in (a) chip 1, and (b) chip 2, fabricated in the 0.35-m 3.3-V CMOS process.

polysilicon diodes, which is fully compatible to the standard

bulk CMOS process, may be a good candidate to implement the
charge pump circuit without the limitation of the breakdown
voltages of the parasitic pn-junctions in the future [27].

IV. CONCLUSION
A new charge pump circuit realized with only low-voltage
devices without suffering the gate-oxide reliability issue has
been presented. Because the charge transfer switches of the new
proposed charge pump circuit can be fully turned on and turned
off, as well as the output stage does not have the threshold
drop problem, its pumping efficiency is higher than that of the
prior designs. The gate-drain and the gate-source voltages of
all devices in the proposed charge pump circuit do not exceed
VDD, so the proposed charge pump circuit does not suffer
Fig. 11. Measured output voltages of different charge pump circuits with 3.3-V
power supply (VDD = 3:3 V), where the stage number is 4. the gate-oxide reliability problem. Two test chips have been
implemented in a 0.35- m 3.3-V CMOS process. The exper-
imental results have shown that the new proposed four-stage
charge pump circuit with each pumping capacitor of 2 pF to
drive the capacitive load is around 8.8 V under 3.3-V power
supply VDD V . With the higher pumping gain and no
overstress across the gate oxide, the new proposed charge pump
circuit is more suitable for applications in low-voltage CMOS
integrated circuits to generate the specified high voltage.

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Yamada, Y. Ohshima, M. Oshikiri, Y. Hiura, T. Yamane, and K. Dr. Ker has served as a member of the Technical Program Committee, Sub-
Toshikawa, “A 16-Mb flash EEPROM with a new self-data-refresh Committee Chair, and Session Chair of numerous international conferences. He
for a sector erase operation,” IEEE J. Solid-State Circuits, vol. 29, pp. is currently serving as Associate Editor for the IEEE TRANSACTIONS ON VERY
461–469, Apr. 1998. LARGE SCALE INTEGRATION (VLSI) SYSTEMS. He was elected as the first Pres-
[15] H. Lin and N.-H. Chen, “New four-phase generation circuits for low- ident of the Taiwan ESD Association in 2001. He has also been the recipient
voltage charge pumps,” in Proc. IEEE Int. Symp. Circuits Syst., 2001, of numerous research awards presented by ITRI, the National Science Council,
vol. I, pp. 504–507. and National Chiao-Tung University, and the Dragon Thesis Award presented
[16] S.-Y. Lai and J.-S. Wang, “A high-efficiency CMOS charge pump by the Acer Foundation. In 2003, he was selected as one of the Ten Outstanding
circuit,” in Proc. IEEE Int. Symp. Circuits Syst., 2001, vol. IV, pp. Young Persons in Taiwan, R.O.C., by the Junior Chamber International (JCI).
406–409. One of his inventions received the Taiwan National Invention Award in 2005.
[17] H. Lin, K.-H. Chang, and S.-C. Wong, “Novel high positive and nega-
tive pumping circuits for low supply voltage,” in Proc. IEEE Int. Symp.
Circuits Syst., 1999, vol. I, pp. 238–241.
[18] C. Lauterbach, W. Weber, and D. R̋merRomer, “Charge sharing con- Shih-Lun Chen (S’02) was born in Taipei, Taiwan,
cept and new clocking scheme for power efficiency and electromag- R.O.C., in 1976. He received the B.S. and M.S.
netic emission improvement of boosted charge pumps,” IEEE J. Solid- degrees from the Department of Electronic Engi-
State Circuits, vol. 35, pp. 719–723, May 2000. neering, Fu-Jen Catholic University, Hsinchuang,
[19] J.-T. Wu and K.-L. Chang, “MOS charge pump for low-voltage opera- Taiwan, R.O.C., in 1999 and 2001, respectively.
tion,” IEEE J. Solid-State Circuits, vol. 33, pp. 592–597, Apr. 1998. He is currently working toward the Ph.D. degree at
[20] Semiconductor Industry Association, International Technology the Institute of Electronics, National Chiao-Tung
Roadmap for Semiconductors 2004. University, Hsinchu, Taiwan, R.O.C.
[21] B. Kaczer, R. Degraeve, M. Rasras, K. Van de Mieroop, P. J. Roussel, His current research includes high-speed and
and G. Groeseneken, “Impact of MOSFET gate oxide breakdown on mixed-voltage I/O interface circuit design in
digital circuit operation and reliability,” IEEE Tran. Electron Devices, deep-submicron CMOS processes.
vol. 49, pp. 500–506, Mar. 2002.
[22] M.-D. Ker, S.-L. Chen, and C.-S. Tsai, “A new charge pump circuit
dealing with gate-oxide reliability issue in low-voltage processes,” in
Proc. IEEE Int. Symp. Circuits Syst., 2004, vol. I, pp. 321–324.
[23] R. Perigny, U.-K. Moon, and G. Temes, “Area efficient CMOS charge Chia-Shen Tsai was born in Taichung, Taiwan,
pump circuits,” in Proc. IEEE Int. Symp. Circuits Syst., 2001, vol. I, pp. R.O.C., in 1979. He received the B.S. degree from
492–495. the Department of Electronics Engineering and
[24] E. R. Minami, S. B. Kuusinen, E. Rosenbaum, P. K. Ko, and C. Hu, the M.S. degree from the Institute of Electronics,
“Circuit-level simulation of TDDB failure in digital CMOS circuits,” National Chiao-Tung University, Hsinchu, Taiwan,
IEEE Tran. Semiconduct. Manufact., vol. 8, no. 3, pp. 370–377, Aug. R.O.C., in 2001 and 2003, respectively.
1995. In 2003, he joined Realtek Semiconductor Corp.
[25] R. Moazzami and C. Hu, “Projecting oxide reliability and optimizing in Hsinchu, Taiwan, R.O.C., as a Design Engineer.
burn-in,” IEEE Tran. Electron Devices, vol. 37, no. 7, pp. 1642–1650, His main research includes the I/O interface circuit
Jul. 1990. design in CMOS processes.