UNIT I (Contd..

SAP I
(Simple as Possible Computers)
 Introduction
• The Simple-As-Possible (SAP)-1 computer is a very basic model of a
microprocessor explained by Albert Paul Malvino.
• The SAP-1 design contains the basic necessities for a functional
Microprocessor
• The SAP (Simple-As-Possible) computer has been designed for
beginners.
• Its primary purpose is to develop a basic understanding of how a
microprocessor works, interacts with memory and other parts of
the system like input and output. The instruction set is very limited
and is simple
• SAP-1 is the first stage in the evolution toward modern computers.
• SAP-1 is a big step for beginners
 The features in SAP-1 computer are:
• W bus – A single 8 bit bus for address and data transfer.
• 16 Bytes memory (RAM)
• Registers are accumulator and B-register each of 8 bits.
• Program counter – initializes from 0000 to 1111 during
program execution.
• Memory Address Register (MAR) to store memory
addresses.
• Adder/ Subtracter for addition and subtraction instructions.
• A Control Unit
• A Simple Output.
• 6 machine state reserved for each instruction
• The instruction format of SAP-1 Computer is
 Micro program

• each SAP-1 block has some control lines:

– each three-state driver has an enable line which connects the driver to the bus
– o the program counter also has a count line which, when high, increments the
contents on the next low-to-high clock transition
– all registers have a load line (active low)
– the ALU has a subtract line which is high for subtraction and low for addition
• implementing the SAP-1 instructions means raising and lowering these
control lines at the appropriate times
• these 12 control lines are the micro program word
• controller must, on each clock cycle, produce 12 bits
• some of these bits are on-off (e.g. three-state output lines) and have a
"default off" state
• some of these bits are A/B (e.g. the add-subtract line) and have a "default
don't care"
• some bits are active high, some are active low
 Controller Implementation
• How to generate micro words?
• if a bit is only on during one cycle, connect it to the
corresponding ring counter bit
• if a bit is only on for an instruction, connect it to that
instruction (as decoded by a 4-bit 1-of-16 decoder)
• if a bit is only on for an instruction and a cycle, connect
it to the AND of the ring counter bit and the decoder
output
• if a bit is on for multiple instruction and/or cycles, work
out the truth table and use AND/OR or multiplexers to
implement it
• alternative: use a ROM
 Program Counter
• The program is stored at the beginning of the memory with the first instruction at
binary address 0000, the second instruction at 0001, the third at address 0010 and so
on.
• The program counter which is part of the control unit, counts from 0000 to 1111. Its
job is to send to the memory the address of the next instruction to be fetched and
executed.
• The program counter is reset to 0000 before each computer run.
• When the computer run begins, the program counter sends the address 0000 to the
memory.
• The program counter is then incremented to get 0001.
• After the first instruction is fetched and executed, the program counter sends address
0001 to the memory.
• Again the program counter is incremented. After the second instruction is fetched and
executed, the program counter sends address 0010 to the memory.
• So this way, the program counter keeps track of the next instruction to be fetched and
executed.
• The program counter is like someone pointing a finger at a list of instructions saying
do this first, do this second, do this third, etc.
• This is why the program counter is called a pointer;
• it points to an address in memory where the instruction or data is being stored
 Input & MAR The RAM
• The Input and MAR includes • The RAM is a 16 X 8 static TTL
the address and data switch RAM.
registers.
• We can program the RAM by
• Switch registers are part of means of the address and data
input unit, allows us to send 4
address bits and 8 data bits to switch registers.
the RAM. • This allows you to store a
• The memory address register program and data in the
(MAR) is the part of SAP-1 memory before a computer run.
memory. • During a computer run, the RAM
• During a computer run, the receives 4-bit addresses from
address in the program the MAR and a read operation is
counter is latched in to the performed.
MAR.
• A bit later, the MAR applies • In this way, the instruction or
this 4-bit address to the RAM data word stored in the RAM is
where a read operation is placed on the W bus for use in
performed. some other part of the
computer.
 Instruction Register Controller – Sequencer(CU)
• The instruction register is the part • Before each computer runs, a CLR signal
of the control unit. is sent to the program counter and CLK
• To fetch an instruction from the signal to the instruction register.
memory the computer does a • This resets the program counter to 0000
memory read operation. and wipes out the last instruction in the
instruction register.
• This places the contents of the
addressed memory location on • A clock signal CLK is sent to all buffer
the W bus. registers; this synchronizes the
operation of the computer ensuring that
• At the same time, the instruction things happen when they are supposed
register is set up for loading on to happen.
the next positive clock edge. • The 12 bits that come out of the
• The content of the instruction controller sequencer form a word
register are split into two nibbles. controlling the rest of the computer (like
The upper nibble goes directly to a supervisor telling others what to do).
the block “Controller – • The 12 wires carrying the control word
Sequencer”. are called the control bus. The control
• The lower nibble is read onto the word has the format of: CON =
W bus when needed. CP EP LM CE L1E1 LA EA SUEULBLO
• This word determines how the registers
will wait to the next positive CLK edge
Accumulator: The accumulator (A) is a buffer register that stores intermediate answers
during a computer run. Accumulator has two outputs, one directly goes to the adder-
subtractor and the other goes to the W bus.
The Adder – Subtractor: SAP-1 uses a 2’s complement adder-subtractor. When SU is low,
the sum out of the adder-subtractor is S = A + B. When SU is high, the difference appears
as A = A + B ’.
B Register: The B register is another buffer register. It is used in arithmetic operations. A
low LB and positive clock edge load the word on the W bus into the B register. The two
state output of the B register drives the adder-subtractor, supplying the number to be
added or subtracted from the content of the accumulator.
Output Register: At the end of the computer run, the accumulator contains the answer to
the problem being solved. At this point, we need to transfer the answer to the outside
world. This is where the output register is used.
When EA is high and LO is low, the next positive clock edge loads the accumulator content
to the output register. The output register is often called an output port because the
processed data can leave the computer through this register.
Binary Display
The binary display is a row of eight light emitting diodes (LED’s). Because each LED
connects to one flip-flop of the output port, the binary display shows us the content of the
output port. Therefore, after we transferred an answer from the accumulator to the
output port, we can see the answer in binary form.
 SAP – 1 instructions
• Computer Hardware are useless until it is
commended by Program(Instruction)
• There are fixed set of Instructions that are
supported by every microprocessor
• SAP-I Supports given Instruction
– LDA
– ADD
– SUB
– OUT
– HLT
 LDA
• LDA stands for “Load the Accumulator”
• A Complete LDA instruction includes the
hexadecimal address of the data to be loaded
• Eg. LDA 8H (H- symbolize for Hexadecimal)
• It means load the accumulator with the content
of memory location 8H
• Memory words are symbolize by Rn (For SAP –I
R0,R1……..R15 )
• So R8 =1111 0101 then after execution of LDA 8H
• A=1111 0101
 ADD
• A complete ADD instruction includes the address of the word to be added.
• For example, ADD 9H means "add the contents of memory location 9H to
the accumulator contents", the sum replaces the original contents of the
accumulator.
• Suppose decimal 2 is in accumulator and decimal 3 is in memory location
9H. Then
• A = 00000010
• R9 = 00000011
• During the execution of ADD 9H, the following steps happen. First, R9 is
loaded into the B register to get
• B= 00000011 and immediately the adder-subtracter forms the sum of A
and B ;SUM= 00000101
• Second, the sum is loaded into the accumulator to get A = 0000 010 1
• The foregoing routine is used for all ADD instructions, the addressed RAM
word goes to the B register and the adder-subtracter output to the
accumulator.
• This is why the execution of ADD 9H adds R9 to the accumulator contents,
the execution of ADD FH adds Rp to the accumulator contents and so on.
 SUB
• A SUB instruction includes the address of the word to be subtracted.
• For instance, SUB CH means "subtract the contents of memory location CH
from the content of accumulator", the difference out of the adder-subtracter
then replaces the original contents of the accumulator.
• Assume that decimal 7 is in the accumulator and decimal 3 is in memory
location CH. Then
• A = 00000111
• Rc = 0000 0011
• Almost immediately the adder-subtracter forms the difference of A and B:
• B = 00000011
• The execution of SUB CH takes place as follows. First, Rc is loaded into the B
register to get
• DIFF= 0000 0100
• Second, this difference is loaded into the accumulator and
• A = 00000100
• The foregoing routine applies to all SUB instructions, the addressed RAM
word goes to the B register and the adder-subtracter output to the
accumulator.
• This is why the execution of SUB CH subtracts Rc from the content of
accumulator, the execution of SUB EH subtracts RE from the accumulator,
and so on
 OUT and HLT
• OUT
– The instruction OUT tells the SAP-1 computer to transfer the
accumulator contents to the output port.
– After OUT has been executed, you can see the answer to the
problem being solved.
– OUT is complete by itself, that is, you do not have to include an
address when using OUT because the instruction does not involve
data in the memory.
• HLT
– HLT abbreviated as halt.
– It tells the computer to stop processing data.
– HLT marks the end of a program, similar to the way a period marks
end of a sentence.
– We must use a HLT instruction at the end of every SAP-1 program,
otherwise, we get computer trash (meaningless answers caused by
runaway processing).
– HLT is complete by itself i.e. we do not have to include a RAM word
when using HLT because this instruction does not involve the
memory.
 Term Related with Instruction Set
• Memory Reference Instruction:
– LDA, ADD, SUB are called Memory reference Instruction because
they uses memory
– Other Hand OUT and HLT are Non Memory reference Instruction
because they don’t uses memory
• Mnemonics(OPCODE):
– LDA, ADD, SUB, OUT, HLT are Instruction set which are also
called Mnemonics.
– In microprocessor there is unique equivalent binary value
(4bits)for those Mnemonics
– MnemonicsOPCODE
– LDA0000
– ADD0001
– SUB0010
– OUT1110
– HLT1111
 Fetch and execution cycle of SAP-1
instructions
• SAP1 has six T-states (three fetch and three execute
cycles) reserved for each instruction.
• Not all instructions require all the six T-states for
execution.
• The unused T- state is marked as No Operation (NOP)
cycle.
• Each T-state is called a machine cycle for SAP1.
• A ring counter is used to generate a T-state at every
falling edge of clock pulse.
• The ring counter output is reset after the 6th T-state
 Contd..
• FETCH CYCLE – T1, T2, T3 machine cycle
• EXECUTE CYCLE - T4, T5, T6 machine cycle
• Complete code includes opcode and operand
• One instruction is executed in one instruction cycle
• Instruction cycle may consist of many machine cycles
• For SAP-1, Instruction cycle = Machine cycle
• Instruction cycle = Fetch cycle + Execution cycle
• Fetch cycle is generally same for all instructions
 Contd..
Fetch Cycle
• Address state: enable PC to bus three-state output, MAR load line
• Increment state: enable PC increment (and perhaps wait for memory
access time)
• Memory state: enable memory CE, IR load line
• IR is loaded on the low-to-high clock transition, so stabilizes before
state 4 is entered
– t1: MAR ← PC
– t2: PC ← PC +1
– t3: IR ← RAM
Execution Cycle -- LDA
• state 4: enable IR to bus three-state output, MAR load line
• state 5: enable memory CE, accumulator load line
• state 6: enable nothing
– t4: MAR ← (IR (Address of operand))
– t5: Accumulator ← RAM
– t6: nothing
 Contd..
Execution Cycle – ADD
• state 4: enable IR to bus three-state output,
MAR load line
• state 5: enable memory CE, register B load line
• state 6: enable add, ALU to bus three-state
output, accumulator load line
– t4: MAR ← (IR (Address of B))
– t5: B ← RAM
– t6: Accumulator ← Accumulator + B
FETCH CYCLE
 The Sap-1 Microprogram
Microinstructions
• The controller-sequence sends out control words, one during each T- state
or clock cycle.
• These words are like directions telling the rest of the computer what to
do.
• Because it produces a small step in the data processing, each control word
is called a micro-instruction.
Macro-instruction
• The instructions LDA, ADD, SUB are sometimes called macro-instructions.
Each Sap-1 macro-instruction is made up of three micro-instructions (i.e.
T4, T5 and T6 state).
Control Matrix
• The LDA, ADD, SUB and OUT signals from the instruction decoder drive the
control matrix, at the same time, the ring counter signals, T1 to T6, are
driving the matrix.
• The matrix produces CON, a 12-bit micro-instruction that tells the rest of
the computer what to do.
Microprogramming
• The control matrix is one way to generate the microinstructions needed
for each execution cycle.
• With larger instruction sets, the control matrix becomes very complicated
and requires hundreds or even thousands of gates.
• Microprogramming is the alternative. The basic idea is to store
microinstructions in a ROM rather than produce them with a control
matrix.
• This approach simplifies the problem of building a controller-sequencer.
Storing the Micro-Program
• These microinstructions can be stored in control ROM with the fetch
routine at addresses at 0H to 2H, the LDA routine at addresses 3H to
5H,the ADD routine at 6H to 8H.
• To access any routine, we need to supply the correct addresses. For
instance, to get the ADD routine, we need to supply addresses 6H, 7H and
8H.
• To get the OUT routine, we supply addresses CH, DH, EH. Therefore,
accessing any routine requires three steps:
– Knowing the starting address of the routine
– Stepping through the routine addresses
– Applying the addresses to the control ROM
 SAP-II
• SAP 2 computer is designed by A. Malvino which
is far more advanced than the SAP 1 computer.
• SAP 2 is 8 bit computer with 64 Kb (62 Kb RAM
and 2 Kb ROM) memory and 16 bit w-bus used as
both address and data bus.
• SAP 1 is followed by SAP 2 which is superior
model to SAP 1 as many new features are added
in this model.
• The features are implemented through hardware.
Although the operations are more or less same,
the data path is bigger in comparison to SAP
 Component of SAP II
• Input pots:
– SAP-2 has 2 input/output ports: port 1 and port 2.
– A hexadecimal encoder is connected to port 1. It allows us to
enter hexadecimal instructions and data through port 1.
– The hexadecimal keyboard encoder sends a ready signal to bit 0
of port 2.
– This signal indicates when the data in port 1 is valid.
– SERIAL input can be taken from pin 7 of port 2.
• Program Counter (PC)
– Program Counter can store 16-bit address, therefore it can
count from:
– PC = 0000 0000 0000 0000 0000
– To PC = 1111 1111 1111 1111 1111
– i.e., from 0000H to FFFFH.
– The low (CLR)’ signal resets the PC before each computer run, so
the data processing starts with the instruction stored in memory
location 0000H.
 Contd..
• MAR and Memory:
– During the fetch cycle, the MAR receives 16 bit addresses from PC.
– The two state MAR output then addressed memory location. The
memory has 2K ROM with address 0000H too 07FFH.
– The ROM contains a program called monitor that initializes the
computer on power-up, interprets the keyboard inputs and so on.
– The rest of memory is 64 K RAM (62 Kb RAM and 2 Kb ROM) with
addresses from 0800H to FFFFH.
• Memory Data Register (MDR)
– The MDR is an 8-bit register to store 8-bit Op-code.
– An 8-bit Op-code can accommodate 256 instructions.
– SAP-2 has only 42 instructions are identical with 8080/8085
instructions.
• Controller-Sequencer
– The controller-sequencer produces the control word or micro-
instructions that coordinates and direct the computer.
– SAP-2 has bigger instruction set; the controller-sequencer has more
hardware.
– The control word (CON) or micro-instructions determine how the
registers react to the next positive edge dock
 Contd..
• IR(Instruction Register)
– It is a Part of control unit .
– Memory read operation performed by computer to fetch an instruction from
memory, this places the contents of the addressed memory location on W bus
– It’s Contents split into 2 nibbles. SAP 2 use 8 bits for op code which can
accommodate 256 instructions
• Accumulator
– The two-state output of the accumulator goes to the ALU; the three-state output to
the W-bus.
– Therefore, the 8-bit word in the accumulator continuously drives the ALU, but this
same word appears on the bus when EA is active.
• ALU and Flags
– The ALUs are commercially available as integrated circuit (IC).
– These ALUs have 4 or more control bits that determine arithmetic and logic
operation performed on word A and B.
– The ALU used in SAP-2 includes arithmetic and logic operation. Flag is a flip-flop
that keeps track of a changing condition during computer run.
– The SAP-2 has two flags:
– Sign Flag: The sign flag is set when the accumulator contents become negative
during the execution of some instructions.
– Zero Flag: The zero flag is set when the accumulator contents are zero.
 Contd..
• TMP, B & C Register
– These registers are used for holding data during ALU operations.
– It provides flexibility to the programmers in moving data between the
registers.
– In general B register is used to store second operand while C register is
used as counter.
– TMP register is used internally and not accessible to programmers.
• Output Ports
– SAP-2 has two output ports: port 3 and port 4.
– The contents of the accumulator can be loaded into port 3, which
drives the hexadecimal display.
– The contents of the accumulator can also be sent to port 4.
– The pin 7 of port 4 sends ACKNOWLEDGE signal to the hexadecimal
encoder.
– This ACKNOWLEDGE signal and READY signal are part of a concept
called handshaking.
– The SERIAL OUT signal from pin 0 of port 4 converts parallel data in
the accumulator into serial output data.
 Comparison between Sap 1 and Sap 2
SAP 1 SAP 2

Full Form Simple As Possible 1 Simple as Possible 2

Logical operations Cannot be handled Can be handled

Addresses 8 bits 16 bits

Opcodes 4 bits 8 bits
Instructions Fixed length Variable length.

Carries out logical

Carries out simple operations too and
Adder/substactor unit operations like addition therefore also known as
and subtraction ARITHMETIC/LOGIC
UNIT
 Bigger due to extra
Size of control sequencer Smaller
registers
Number of instructions Comparatively lesser Comparatively greater

Register to hold the data

being added or subtracted B TMP
from the accumulator

JM, JZ and JNZ –

Jump instructions Not available conditional jumps
JMP – unconditional jumps

Includes instructions like

Includes instruction – LDA, ADD, SUB, INR, JMP,
Instructions
ADD, SUB, OUT and HLT DCR, ANA, ORA, XRA,
ANI, ORI, XRI, etc.

Display to show outputs in

Binary Hexadecimal
the LEDs
Instruction Set of SAP II
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