MANISH MALLAN

Tel : 1-214-709-1182
Email : manish.mallan@gmail.com

Professional Summary: 5.5 Years of experience in design verification of

complex SoC’s.

• Experience in processor-based verification using C and assembly.

• Experience with industry standard verification languages such as Spec-
man E, Systemverilog.
• Experience in power management verification using Power-aware RTL
(PARTL), Power-aware GLS (PAGLS) & Power aware emulation using
Quickturn Palladium Emulation system & CPF (common power format).
Familiar with advance Low Power Methodologies.
• Experience in developing verification environment for complex designs us-
ing scripting languages.
• Familiar with STA and physical design flow.
• Worked on full life cycle of Projects, from reviews of requirements and de-
signs, through the development and testing process to implementation.
• Excellent communication and Inter-personnel skills, ability to master new
concepts.

Presently working as Project Lead (VLSI) at MindTree Consulting Ltd.

Role: Team Member in Texas Instruments ODC from Oct 2005 to date.

SIGNIFICANT RESPONSIBILITIES :

•Module level verification of Memory Adapter using Specman & AXI-4

evc's. This IP sits between ARM A15 (Eagle) and EMIF.
• Power Management Verification of Monica application co-processor
(based on OMAP 4 architecture). Apart from using Power-aware RTL,
used Cadence Palladium-II and CPF (Common Power Format) based
methodology.
• Power Management Verification of RapuYama application processor.
• Module level verification of PSCON (Power Sequence Controller) using
Sytemverilog and PSL.
• Integration Verification of various modules including Jpeg HWA (Hard-
ware Accelerator), Efuse, Security Hardware, ULPD (Ultra Low Power
Down) for Locosto SoC. Also did Power Management Verification us-
ing Power-aware RTL and Power-aware GLS.
• Module level verification of CJM (Camera Jpeg Master) using Spec-
man/E.
DETAILED WORK EXPERIENCE :

Current Project Description:

Verification of Memory Adapter using Specman & AXI-4 evc's. The IP is part
of TI's next generation OMAP. The verification included creation of test cases
to check various sub-modules of the IP & to create bfm's in e for verifying
custom interfaces. The IP used the latest AXI protocol which includes cache
coherency extensions. The project is being executed from Dallas, Texas.

Project Description:
Creation of Verification environment for UMA3x DSP subsystem. Working as
a Team lead from Nov 2009 to date. The objective of the project is to create a
verification environment which does not use any of TI’s in-house regression
system. The environment is a mix of Specman/E & DSP assembly, with over
1000 test cases.

Project Description:
Worked as a Verification Engineer for Monica Multi-processor
(ARM cortex & C64M) SOC chip based on OMAP 4 architecture for
Wireless applications from Mar 2009 to Nov 2009.
Completed activities :-.
• Verification of PRCM (Power Reset Clock Manager) using C &
Specman E at system level.
• Power aware use cases were written in C to check various data
paths.
• Test cases were also simulated on Power aware RTL.
• Working on verifying the design using Quickturn Palladium-II emu-
lation system. The test cases are run on power aware setup created
using Common Power Format (CPF). Test cases were specifically
written to target multiple power domains. Systemverilog assertions
were also written to check for specific events.

Project Description:
Worked as a Verification Engineer for RapuYama Multi-processor
(ARM11 & UMA) SOC chip for Wireless applications from Oct 2008 to
Mar 2009.
Completed activities :-.
• Integration verification of OHCI based USB-FS Host using Specman
E & C.
• Power Management Verification using PARTL.
• Module level verification of PSCON (Power sequence controller) us-
ing System Verilog and PSL. The testbench was written in sys-
temverilog. The assertions were written in PSL.

Project Description:
Worked as a Verification Engineer for LocostoC021 Multi-processor
(ARM7 & C5x) SOC chip for Wireless applications from Oct 2005 to
Oct 2008.
Part of team working for RTP (Ready To Production) of this device.
Completed Activites :-
Physical Design :
• Implemented couple of ECO’s using Magma.
• Did timing closure using Primetime & Primetime-SI.
• Did DRC’s cleanup using Magma. Various checks both for reliability
and physical verification were also run.

Verification :
Post Silicon activities (for Previous release) :
• Created test case to replicate silicon bug concerning USB.
• Created test case for JPEG module, which became basis for silicon
validation for the same.
• Did prime-power analysis for desense problem faced in silicon. It in-
cluded creating different scenarios & generating primepower report
& finally generating Power Spectral density using Matlab. The aim
was to correlate these with silicon & fix the problem for current re-
lease.

GLS setup:
• Automated the GLS setup flow using Perl. The script compiles the
GLS database, emails users how to run & starts regression.
 • Maintaining GLS regression

Completed functional & integration verification of following modules:

• JPEG Hardware Accelerator:
• Test cases were written C to verify different data paths.
• A perl script was written to convert uncompressed image
data to format which could be used by camera bfm to drive
data into system.

• Security Hardware:
• Test cases were written in C. Various scenarios for accessi-
bility of secure peripherals was implemented.
• Dedicated test cases were also written for sub-modules like
PRRM, which controls reset to secure peripherals & RAM's &
EMPU, which controls read/write access to different memo-
ries.

• Power Management Verification :

• Various scenarios of sleep-wakeup were implemented using
C & TCL.
• Test cases were also simulated on Power Aware RTL &
Power Aware Gate Level Simulations.

• ULPD :
• Test cases were written in C to verify gauging, which makes
sure that when chip is in sleep, gsm time keeping is accurate
at low frequency clock.

• EFUSE :
• Test cases were written in C to verify the fuse chain.
• FUSE rom image was created for the test cases.
• A perl script was written which archives C test cases output log
files, which can be used in future regression runs.

Previous Employment :
Role: Team Member in OSCOE (Open Source Centre Of Excellence) from
Sept 2004 to Jul 2005 at ATC, TCS.
Project Briefing:
• Helped in setting up a network boot server. So, that people not hav-
ing access to GNU/linux can give it a try. The server had both in-
stallation cd’s as well as GNU/linux live cd distributions modified to
boot from network using TFTP and NFS, with full gui.
• Made a live cd based on Red Hat 8.0 for a TCS product , so that it
could be compiled on any machine just by booting through cd. A
LiveCD is an operating system (usually containing other software as
well) stored on a bootable CD-ROM or DVD-ROM that can be exe-
cuted from it, without installation on a hard drive .
• Wrote a perl script for a machine translator ANUSARAKA designed
by University of Hyderabad. The script was designed to select a
POS (part of speech) from the various available implementations
and give result in xml format
EDUCATIONAL QUALIFICATION:
B.E (Electronics & Electrical communications, 2004) –Thapar Institute of
Engineering & Technology (TIET), Patiala
CGPA – 9.23/10
• Class XII (Punjab State) year of passing: 2000.
Institution: D.A.V College, Amritsar
Marks obtained: 65.66 %
CET rank: 99
• Class X (CBSE) year of passing: 1998.
Institution: D.A.V Public School, Amritsar
Marks obtained: 83.6%

TRAINING COURSES UNDERTAKEN:

Hardware Training
- Worked on design of “Sequence Detector” as a part of hardware training at
MindtTree. It was implemented in verilog.

Continuous Learning Program

- Attended program on Defect Analysis & Resolution (DAR) as part of
requirement of the organization at TCS – Hyderabad - Jan 2005

Initial Learning Program (ILP) at CMC Hyderabad from 29/July/2004 –22/

Sept/ 2004.
- Courses Covered
Software Engineering, Requirements Engineering, Operating Systems,
Data Structures, JAVA, Networking & ISecurity
Integrated Quality Management Systems
Project on Pharmacy System – using J2EE, SQL
Life skills (soft skills)
Learnt Japanese as part of foreign language curriculum.

Attended short term course on CMOS VLSI at Thapar Institute of

Engineering & Technology , Patiala

`TECHNICAL SKILLS:

Programming knowledge: VHDL, Verilog, C, Perl, Tcl, Assembly language.

Operating Systems: GNU/linux, Windows
Modeling and Analysis: Matlab

PROJECTS UNDERTAKEN DURING ENGINEERING:

2nd sem: - Training in manufacture of PCB (Printed circuit board).

- Simulation of circuits using ORCAD CAPTURE and CADSTAR.
 - Design of a super heterodyne reciever.
4th sem: - Made a Digital Heart Beat Counter.
5th sem: - Made a setup to show MOSFET switching.
th
6 sem: - Project at Alstom Projects Ltd., Noida.
The project related to understanding of SCADA systems. It also
included testing of RTU (remote terminal units) which
implements SCADA to automate control of
electrical networks.
7th sem: - Designed a 8 bit Boothe multiplier using VHDL.
EXTRA CURRICULAR ACTIVITIES:
• Hobbies – Reading novels & listening to music, playing chess.

ACHIEVEMENTS:
• Received scholarship during 9th from MATA BAINTI DEVI TRUST.
• Received scholarship during engg. degree programme.
• Awarded Spot Award by MindTree for contribution to Locosto Project.
• Awarded cash prize by Texas Instruments for contribution to Locosto
Project.

SKILLS:
• Loads of patience, and capability to follow procedure and guidelines.
• Good command over English.
• Good writing and communication skills in English.
• Ability to lead and also be a team player.

PERSONAL DETAILS:
Name : Manish Mallan
Date of Birth : 28, August 1981
Sex: Male
Present Address: Dallas, Texas
Permanent Address: 50, Golden Avenue, Amritsar -143001
Mobile: 1-214-709-1182
Email: manish.mallan@gmail.com
Visa: L1