a Ultrafast 4 ns

Single Supply Comparators

AD8611/AD8612
FEATURES PIN CONFIGURATIONS
4 ns Propagation Delay at 5 V
Single Supply Operation: 3 V to 5 V
100 MHz Input 8-Lead Narrow Body SO
Latch Function (SO-8)

APPLICATIONS Vⴙ OUT
High-Speed Timing ⴙIN OUT
ⴚIN GND
Clock Recovery and Clock Distribution Vⴚ LATCH
Line Receivers AD8611
Digital Communications
Phase Detectors
High-Speed Sampling 8-Lead MSOP
Read Channel Detection (RM-8)
PCMCIA Cards
Zero Crossing Detector Vⴙ 1 8 OUT
High-Speed A/D Converter ⴙIN
AD8611
OUT
ⴚIN GND
Upgrade for LT1394 and LT1016 Designs Vⴚ 4 5 LATCH

GENERAL DESCRIPTION
The AD8611/AD8612 are single and dual 4 ns comparators with 14-Lead TSSOP
latch function and complementary output. (RU-14)
Fast 4 ns propagation delay makes the AD8611/AD8612 a good
QA 1 14 QB
choice for timing circuits and line receivers. Propagation delays
for rising and falling signals are closely matched and track over QA 2 13 QB

temperature. This matched delay makes the AD8611/AD8612 a GND 3

AD8612
12 GND

good choice for clock recovery, since the duty cycle of the output LE A 4 TOP VIEW 11 LE B
will match the duty cycle of the input. (Not to Scale) 10 V+
Vⴚ 5

The AD8611 has the same pinout as the LT1016 and LT1394, IN Aⴚ 6 9 IN Bⴚ

with lower supply current and a wider common-mode input range, IN A+ 7 8 IN B+

which includes the negative supply rail.

The AD8611/AD8612 is specified over the industrial (–40°C to
+85°C) temperature range. The AD8611 is available in both 8-lead
MSOP and narrow SO-8 surface mount packages. The AD8612
is available in 14-lead TSSOP surface-mount package.

REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2000

This datasheet has been downloaded from http://www.digchip.com at this page

AD8611/AD8612–SPECIFICATIONS
ELECTRICAL SPECIFICATIONS (@ V+ = 5.0 V, V– = VGND = 0 V, TA = 25ⴗC unless otherwise noted)
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS 1 7 mV
–40°C ≤ TA ≤ +85°C 8 mV
Offset Voltage Drift ∆VOS/∆T 4 µV/°C
Input Bias Current IB VCM = 0 V –6 –4 µA
IB –40°C ≤ TA ≤ +85°C –7 –4.5 µA
Input Offset Current IOS VCM = 0 V ±4 µA
Input Common-Mode Voltage Range VCM 0.0 3.0 V
Common-Mode Rejection Ratio CMRR 0 V ≤ VCM ≤ 3.0 V 55 85 dB
Large Signal Voltage Gain AVO RL = 10 kΩ 3,000 V/V
Input Capacitance CIN 3.0 pF
LATCH ENABLE INPUT
Logic “1” Voltage Threshold VIH 2.0 1.65 V
Logic “0” Voltage Threshold VIL 1.60 0.8 V
Logic “1” Current IIH VLH = 3.0 V –1.0 –0.3 µA
Logic “0” Current IIL VLL = 0.3 V –5 –2.7 µA
Latch Enable
Pulsewidth tPW(E) 3 ns
Setup Time tS 0.5 ns
Hold Time tH 0.5 ns
DIGITAL OUTPUTS
Logic “1” Voltage VOH IOH = 50 µA, ∆VIN > 250 mV 3.0 3.35 V
Logic “1” Voltage VOH IOH = 3.2 mA, ∆VIN > 250 mV 2.4 3.4 V
Logic “0” Voltage VOL IOL = 3.2 mA, ∆VIN > 250 mV 0.25 0.4 V
DYNAMIC PERFORMANCE
Input Frequency fMAX 400 mV p-p sine wave 100 MHz
Propagation Delay tP 200 mV Step with 100 mV Overdrive1 4.0 5.5 ns
–40°C ≤ TA ≤ +85°C 5 ns
Propagation Delay tP 100 mV Step with 5 mV Overdrive 5 ns
Differential Propagation Delay
(Rising Propagation Delay vs.
Falling Propagation Delay) ∆tP 100 mV Step with 100 mV Overdrive1 0.5 2.0 ns
Rise Time 20% to 80% 2.5 ns
Fall Time 80% to 20% 1.1 ns
POWER SUPPLY
Power Supply Rejection Ratio PSRR 4.5 V ≤ V+ ≤ 5.5 V 55 73 dB
V+ Supply Current2 I+ 5.7 10 mA
–40°C ≤ TA ≤ +85°C 10 mA
Ground Supply Current2 IGND VO = 0 V, RL = ∞ 3.5 7 mA
–40°C ≤ TA ≤ +85°C 7 mA
V– Supply Current2 I– 2.2 4 mA
–40°C ≤ TA ≤ +85°C 5 mA
NOTES
1
Guaranteed by design.
2
Per comparator.
Specifications subject to change without notice.

–2– REV. 0
 AD8611/AD8612
ELECTRICAL SPECIFICATIONS (@ V+ = 3.0 V, V– = VGND = 0 V, TA = 25ⴗC unless otherwise noted)
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS 1 7 mV
Input Bias Current IB VCM = 0 V –6 –4.0 µA
IB –40°C ≤ TA ≤ +85°C –7 –4.5 µA
Input Common-Mode Voltage Range VCM 0 1.0 V
Common-Mode Rejection Ratio CMRR 0 V ≤ VCM ≤ 1.0 V 55 dB
OUTPUT CHARACTERISTICS
Output High Voltage VOH IOH = –3.2 mA, VIN > 250 mV 1.21 V
Output Low Voltage VOL IOL = +3.2 mA, VIN > 250 mV 0.3 V
POWER SUPPLY
Power Supply Rejection Ratio PSRR 2.7 V ≤ V+ ≤ 6 V 46 dB
Supply Currents VO = 0 V, RL = ∞
V+ Supply Current2 I+ 4.5 6.5 mA
–40°C ≤ TA ≤ +85°C 10 mA
Ground Supply Current2 IGND 2.5 3.5 mA
–40°C ≤ TA ≤ +85°C 5.5 mA
V– Supply Current2 I– 2 3.5 mA
–40°C ≤ TA ≤ +85°C 4.8 mA
DYNAMIC PERFORMANCE
Propagation Delay tP 100 mV Step with 20 mV Overdrive3 4.5 6.5 ns
NOTES
1
Output high voltage without pull-up resistor. It may be useful to have a pull-up resistor to V+ for 3 V operation.
2
Per comparator.
3
Guaranteed by design.
Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS

Package Type ␪JA2 ␪JC Unit
Total Analog Supply Voltage . . . . . . . . . . . . . . . . . . . . . 7.0 V
Digital Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V 8-Lead SO (R) 158 43 °C/W
Input Voltage1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 4 V 8-Lead MSOP (RM) 240 43 °C/W
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ± 5 V 14-Lead TSSOP (RU) 240 43 °C/W
Output Short-Circuit Duration to GND . . . . . . . . . Indefinite
NOTES
Storage Temperature Range 1
The analog input voltage is equal to ± 4 V or the analog supply voltage, whichever
R, RU, RM Packages . . . . . . . . . . . . . . . –65°C to +150°C is less.
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C 2
θJA is specified for the worst-case conditions, i.e., θJA is specified for device in socket
Junction Temperature Range for P-DIP and θJA is specified for device soldered in circuit board for SOIC and
TSSOP packages.
R, RU, RM Packages . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering, 10 sec) . . . . . . . 300°C

ORDERING GUIDE

Temperature Package Package Branding

Model Range Description Option Information
AD8611ARM –40°C to +85°C 8-Lead Micro SOIC RM-8 G1A
AD8611AR –40°C to +85°C 8-Lead Small Outline IC SO-8
AD8612ARU –40°C to +85°C 14-Lead Thin Shrink Small Outline RU-14

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. WARNING!
Although the AD8611/AD8612 features proprietary ESD protection circuitry, permanent dam-
age may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper
ESD SENSITIVE DEVICE
ESD precautions are recommended to avoid performance degradation or loss of functionality.

REV. 0 –3–
AD8611/AD8612
8 18
V+ = 5V
V+ = 5V TA = 25ⴗC
7
OVERDRIVE > 10mV
14 OVERDRIVE = 5mV
PROPAGATION DELAY – ns

PROPAGATION DELAY – ns
6
␶PDⴚ
12
5
␶PDⴚ ␶PD+
4 8
␶PD+
3
6

2
2
1

0 0
ⴚ50 ⴚ25 0 25 50 75 100 0 0.5 1.0 1.5 2.0 2.5
TEMPERATURE – ⴗC SOURCE RESISTANCE – k⍀

Figure 1. Propagation Delay Over Temperature Figure 4. Propagation Delay vs. Source Resistance

18 8
V+ = 5V TA = 25ⴗC
16 TA = 25ⴗC 7 STEP = 100 mV
␶PDⴚ ␶PD+ OVERDRIVE > 10 mV
14

PROPAGATION DELAY – ns
PROPAGATION DELAY – ns

12
␶PD+ 5
10 ␶PDⴚ
4
8
3
6
2
4

2 1

0 0
0 5 10 15 20 25 2 3 4 5 6
OVERDRIVE – mV SUPPLY VOLTAGE – V

Figure 2. Propagation Delay vs. Overdrive Figure 5. Propagation Delay vs. Supply Voltage

8 35
TA = 25ⴗC
V+ = 5V ␶PDⴚ STEP = 100 mV
7 TA = 25ⴗC 30
OVERDRIVE = 50 mV
OVERDRIVE > 10mV
PROPAGATION DELAY – ns

PROPAGATION DELAY – ns

6 25
␶PD+
5 ␶PD+
20

4
15
3
10
2

5
1
␶PDⴚ
0 0
0 20 40 60 80 2 3 4 5 6
CAPACITANCE – pF COMMON-MODE VOLTAGE – V

Figure 3. Propagation Delay vs. Load Capacitance Figure 6. Propagation Delay vs. Common-Mode Voltage

–4– REV. 0
 AD8611/AD8612
1.2 0.40
VS = 3V +25ⴗC
0.35
1.0 +85ⴗC
ⴚ40ⴗC
0.30

LOAD CURRENT – V
0.8 ⴚ40ⴗC
0.25
VS = 5V
VOS – mV

0.6 0.20
+85ⴗC

0.15
0.4 +25ⴗC
0.10
0.2
0.05

0 0
ⴚ60 ⴚ40 ⴚ20 0 20 40 60 80 100 0 2 4 6 8 10 12
TEMPERATURE – ⴗC SINK CURRENT – mA

Figure 7. Offset Voltage vs. Temperature Figure 10. Output Low Voltage vs. Load Current
(Sinking) Over Temperature

40 4.0

V+ = 5V
35 TA = 25ⴗC 3.8

+85ⴗC

OUTPUT HIGH VOLTAGE – V

30 3.6

25 3.4
ISY+ – mA

+25ⴗC
20 3.2
ⴚ40ⴗC
15 3.0

10 2.8

5 2.6

0 2.4
1 10 100 0 2 4 6 8 10 12
INPUT FREQUENCY – MHz LOAD CURRENT – mA

Figure 8. Supply Current vs. Input Frequency Figure 11. Output High Voltage vs. Load Current
(Sourcing) Over Temperature

2.0 8
V+ = 5V
1.8
7
1.6
6
1.4 VS = 5V
5
TIMING – ns

1.2
ISY – mA

1.0 4

0.8 SETUP TIME VS = 3V

3
0.6
2
0.4
HOLD TIME
1
0.2

0 0
ⴚ50 ⴚ25 0 25 50 75 100 ⴚ60 ⴚ40 ⴚ20 0 20 40 60 80 100
TEMPERATURE – ⴗC TEMPERATURE – ⴗC

Figure 9. Latch Setup and Hold Time Over Temperature Figure 12. Supply Current vs. Temperature

REV. 0 –5–
AD8611/AD8612
0
V+ = 5V
TA = 25ⴗC
ⴚ0.5

ⴚ1.0

ⴚ1.5 VIN

VOLTAGE
IGND – mA

ⴚ2.0
VS = 3V 0V
ⴚ2.5 VOUT

ⴚ3.0
VS = 5V
ⴚ3.5
VIN TRACE – 10mV/DIV
ⴚ4.0
VOUT TRACE – 1V/DIV

ⴚ4.5
ⴚ50 0 50 100
TEMPERATURE – ⴗC TIME – 2ns/DIV

Figure 13. IGND vs. Temperature Figure 16. Falling Edge Response

0
V+ = 5V VOUT
TA = 25ⴗC
ⴚ0.5

ⴚ1.0 VOLTAGE
ISY – mA

VS = 3V
ⴚ1.5 0V

ⴚ2.0 VS = 5V VIN

ⴚ2.5
VIN TRACE – 10mV/DIV
VOUT TRACE – 1V/DIV
ⴚ3.0
ⴚ60 ⴚ40 ⴚ20 0 20 40 60 80 100
TEMPERATURE – ⴗC TIME – 4ns/DIV

Figure 14. ISY– vs. Temperature Figure 17. Response to a 50 MHz 100 mV Input Sine Wave

V+ = 5V VOUT
TA = 25ⴗC
VOLTAGE

0V
VIN

VIN TRACE – 10mV/DIV

VOUT TRACE – 1V/DIV

TIME – 2ns/DIV

Figure 15. Rising Edge Response

–6– REV. 0
 AD8611/AD8612
Optimizing High-Speed Performance common-mode voltage range to the comparator. Note that sig-
As with any high-speed comparator or amplifier, proper design and nals much greater than 3.0 V will result in increased input
layout should be used to ensure optimal performance from the currents and may cause the comparator to operate more slowly.
AD8611/AD8612. Excess stray capacitance or improper grounding The input bias current to the AD8611 is 7 µA maximum over
can limit the maximum performance of high-speed circuitry. temperature (–40°C to +85°C). This is identical to the maximum
Minimizing resistance from the source to the comparator’s input is input bias current for the LT1394, and half of the maximum IB for
necessary to minimize the propagation delay of the circuit. Source the LT1016. Input bias currents to the AD8611 and LT1394 flow
resistance, in combination with the equivalent input capacitance of out from the comparator’s inputs, as opposed to the LT1016
the AD8611/AD8612 creates an R-C filter that could cause a whose input bias current flows into its inputs. Using low value
lagged voltage rise at the input to the comparator. The input resistors around the comparator and low impedance sources
capacitance of the AD8611/AD8612 in combination with stray will minimize any potential voltage shifts due to bias currents.
capacitance from an input pin to ground results in several pico- The AD8611 is able to swing within 200 mV of ground and within
farads of equivalent capacitance. Using a surface-mount package 1.5 V of positive supply voltage. This is slightly more output voltage
and a minimum of input trace length, this capacitance is typically swing than the LT1016. The AD8611 also uses less current than
around 3 pF to 5 pF. A combination of 3 kΩ source resistance the LT1016, 5 mA as compared to 25 mA of typical supply current.
and 3 pF of input capacitance yields a time constant of 9 ns, which
is slower than the 4 ns propagation delay of the AD8611/AD8612. The AD8611 has a typical propagation delay of 4 ns, compared to
Source impedances should be less than 1 kΩ for best performance. the LT1394 and LT1016, whose propagation delays are typically
7 ns and 10 ns, respectively.
Another important consideration is the proper use of power supply
bypass capacitors around the comparator. A 1 µF bypass capacitor Maximum Input Frequency and Overdrive
should be placed within 0.5 inches of the device between each The AD8611 can accurately compare input signals up to 100 MHz
power supply pin and ground. Another 10 nF ceramic capacitor with less than 10 mV of overdrive. The level of overdrive required
should be placed as close as possible to the device in parallel with increases with ambient temperature, with up to 50 mV of overdrive
the 1 µF bypass capacitor. The 1 µF capacitor will reduce any recommended for a 100 MHz input signal and an ambient tempera-
potential voltage ripples from the power supply, and the 10 nF ture of +85°C.
capacitor acts as a charge reservoir for the comparator during It is not recommend to use an input signals with a fundamental
high-frequency switching. frequency above 100 MHz as the AD8611 could draw up to 20 mA
A continuous ground plane on the PC board is also recommended of supply current and the outputs may not settle to a definite
to maximize circuit performance. A ground plane can be created by state. The device will return to its specified performance once
using a continuous conductive plane over the surface of the circuit the fundamental input frequency returns to below 100 MHz.
board, only allowing breaks in the plane for necessary traces and Output Loading Considerations
vias. The ground plane provides a low inductive current return The AD8611 can deliver up to 10 mA of output current without
path for the power supply, thus eliminating any potential differ- increasing its propagation delay. The outputs of the device should
ences at different ground points throughout the circuit board not be connected to more than 40 TTL input logic gates or drive
caused from “ground bounce.” A proper ground plane will also less than 400 Ω of load resistance.
minimize the effects of stray capacitance on the circuit board. The AD8611 output has a typical output swing between ground
Upgrading the LT1394 and LT1016 and 1 V below the positive supply voltage. Decreasing the output
The AD8611 single comparator is pin-for-pin compatible with load resistance to ground will lower the maximum output voltage
the LT1394 and LT1016 and offers an improvement in propa- due to the increase in output current. Table I shows the typical
gation delay over both comparators. These devices can easily be output high voltage versus load resistance to ground.
replaced with the higher performance AD8611, but there are differ-
ences and it is useful to check that these ensure proper operation. Table I. Maximum Output Voltage vs. Resistive Load
The five major differences between the AD8611 and the LT1016 Output Load V+ ⴚ VOUT, HI
include input voltage range, input bias currents, propagation delay, to Ground (typ)
output voltage swing, and power consumption. Input common-
mode voltage is found by taking the average of the two voltages 300 Ω 1.5 V
at the inputs to the comparator. The LT1016 has an input voltage 500 Ω 1.3 V
range from 1.25 V above the negative supply to 1.5 V below the 1 kΩ 1.2 V
positive supply. The AD8611 input voltage range extends down to 10 kΩ 1.1 V
the negative supply voltage to within 2 V of V+. If the input > 20 kΩ 1.0 V
common-mode voltage could be exceeded, input signals should
be shifted or attenuated to bring them into range, keeping in Connecting a 500 Ω–2 kΩ pull-up resistor to V+ on the output
mind the note about source resistance in Optimizing High-Speed will help increase the output voltage closer to the positive rail;
Performance. in this configuration, however, the output voltage will not reach
its maximum until at least 20 ns to 50 ns after the output voltage
Example: An AD8611 power from a 5 V single supply has its switches. This is due to the R-C time constant between the pull-up
noninverting input connected to 1 V peak-to-peak high-frequency resistor and the output and load capacitances. The output pull-up
signal centered around 2.3 V and its inverting input connected to a resistor will not improve propagation delay.
fixed 2.5 V reference voltage. The worst-case input common-mode
voltage to the AD8611 is 2.65 V. This is well below the 3.0 V input

REV. 0 –7–
AD8611/AD8612
The AD8611 is stable with all values of capacitive load; however, SIGNAL
COMPARATOR
loading an output with greater than 30 pF will increase the propa-
gation delay of that channel. Capacitive loads greater than 500 pF
will also create some ringing on the output wave. Table II shows R1 R2
VREF
propagation delay versus several values of load capacitance. The
loading on one output of the AD8611 does not affect the propaga- CF
tion delay of the other output. Figure 18. Configuring the AD8611/AD8612 with
Hysteresis
Table II. Propagation Delay vs. Capacitive Load
Here, the input signal is connected directly to the inverting input
CL ␶PD Rising ␶PD Falling of the comparator. The output is fed back to the noninverting
input through R1 and R2. The ratio of R1 to R1 + R2 establishes
< 10 pF 3.5 ns 3.5 ns the width of the hysteresis window with VREF setting the center of
33 pF 5 ns 5 ns the window, or the average switching voltage. The Q output will
100 pF 8 ns 7 ns switch low when the input voltage is greater than VHI, and will
390 pF 14.5 ns 10 ns not switch high again until the input voltage is less than VLO as
680 pF 26 ns 15 ns given in Equation 1:

VHI = ( V+ − 1.5 − VREF )

Using the Latch to Maintain a Constant Output R1
+ VREF (1)
The latch input to the AD8611/AD8612 can be used to retain R1 + R2
data at the output of the comparator. When the latch voltage goes
R2
high, the output voltage will remain in its previous state, indepen- VLO = VREF ×
dent of changes in the input voltage. R1 + R2
The setup time for the AD8611/AD8612 is 0.5 ns and the hold Where V+ is the positive supply voltage.
time is 0.5 ns. Setup time is defined as the minimum amount of The capacitor CF is optional and can be added to introduce a
time the input voltage must remain in a valid state before the pole into the feedback network. This has the effect of increasing
latch is activated for the latch to function properly. Hold time is the amount of hysteresis at high frequencies, which is useful when
defined as the amount of time the input must remain constant comparing relatively slow signals in high-frequency noise envi-
after the latch voltage goes high for the output to remain latched ronments. At frequencies greater than fP, the hysteresis window
its voltage. approaches VHI = V+ – 1.5 V and VLO = 0 V. For frequencies less
The latch input is TTL and CMOS compatible, so a logic high is than ƒP, the threshold voltages remain as in Equation 1.
a minimum of 2.0 V and a logic low is a maximum of 0.8 V. The Clock Timing Recovery
latch circuitry in the AD8611/AD8612 has no built-in hysteresis. Comparators are often used in digital systems to recover clock
Input Stage and Bias Currents timing signals. High-speed square waves transmitted over a distance,
The AD8611 and AD8612 use a bipolar PNP differential input even tens of centimeters, can become distorted due to stray capaci-
stage. This enables the input common-mode voltage range to extend tance and inductance. Poor layout or improper termination can also
from within 2.0 V of the positive supply voltage to 200 mV below the cause reflections on the transmission line, further distorting the
negative supply voltage. Therefore, using a single 5 V supply, the signal waveform. A high-speed comparator can be used to recover
input common-mode voltage range is –200 mV to +3.0 V. Input the distorted waveform while maintaining a minimum of delay.
common-mode voltage is the average of the voltages at the two Figure 19 shows the AD8611 used to recover a 65 MHz, 100 mV
inputs. For proper operation, the input common-mode voltage peak-to-peak distorted clock signal into a 4 V peak-to-peak square
should be kept within the common-mode voltage range. wave. The lower trace is the input to the AD8611 and the upper
The input bias current for the AD8611/AD8612 is 4 µA, which trace is the Q output from the comparator. The AD8611 is powered
is the amount of current that flows from each input of the com- from a 5 V single supply.
parator. This bias current will go to zero on an input that is high
and will double on an input that is low, which is a characteristic
common to any bipolar comparator. Care should be taken in
VOUT
choosing resistances to be connected around the comparator as
2V/DIV
large resistors could cause significant voltage drops due to the
input bias current.
The input capacitance for the AD8611/AD8612 is typically 3 pF.
This is measured by inserting a 5 kΩ source resistance in series 20mV/DIV
VIN
with the input and measuring the change in propagation delay.
Using Hysteresis
Hysteresis can easily be added to a comparator through the addi-
tion of positive feedback. Adding hysteresis to a comparator offers
an advantage in noisy environments where it is not desirable for
the output to toggle between states when the input signal is close
TIME – 10ns/DIV
to the switching threshold. Figure 18 shows a simple method for
configuring the AD8611 or AD8612 with hysteresis. Figure 19. Using the AD8611 to Recover a Noisy Clock Signal

–8– REV. 0
 AD8611/AD8612
A 5 V High-Speed Window Comparator 5V
5V
A window comparator circuit is used to detect when a signal is 1k⍀
5V
between two fixed voltages. The AD8612 can be used to create R1
VHI VOUT
6 10
a high-speed window comparator, as shown in Figure 20. Here, 1 1k⍀
A1 Q1 Q2
the reference window voltages are set as: R2 7
3
4 AD612 500⍀
R2 R4
VHI = VLO =
R1 + R2 R 3 + R4
VIN Q1, Q2 = 2N3960
The output of the A1 comparator will go high when the input
signal exceeds VHI, and the output of A2 will go high only when
5V
VIN drops below VLO. When the input voltage is between VHI and 9
AD612
VLO, both comparator outputs will be low, turning off both Q1 and R3 14 1k⍀
VLO 8 A2
Q2, thus driving VOUT to a high state. If the input signal goes 12
500⍀
11
outside of the reference voltage window, then VOUT will go low. R4 5

To ensure a minimum of switching delay, high-speed transistors

PINS 2 AND 13 ARE NO CONNECTS
are recommended for Q1 and Q2. Using the AD8612 with
2N3960 transistors provides a total propagation delay from Figure 20. A High-Speed Window Comparator
VIN to VOUT of less than 10 ns.

Table III. Window Comparator Output States

VOUT Input Voltage

= 200 mV VIN < VLO
+5V VLO < VIN < VHI
= 200 mV VIN > VHI

REV. 0 –9–
AD8611/AD8612
SPICE Model
* AD8611 SPICE Macro-Model Typical Values
* 1/2000, Ver. 1.0
* TAM / ADSC
*
* Node assignments
* non-inverting input
* | inverting input
* | | positive supply
* | | | negative supply
* | | | | Latch
* | | | | | DGND
* | | | | | | Q
* | | | | | | | QNOT
* | | | | | | | |
.SUBCKT AD8611 1 2 99 50 80 51 45 65
*
* INPUT STAGE
*
*
Q1 4 3 5 PIX
Q2 6 2 5 PIX
IBIAS 99 5 800E-6
RC1 4 50 1E3
RC2 6 50 1E3
CL1 4 6 3E-13
CIN 1 2 3E-12
VCM1 99 7 DC 1.9
D1 5 7 DX
EOS 3 1 POLY(1) (31,98) 1E-3 1
*
* Reference Voltages
*
EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5
RREF 98 0 100E3
*
* CMRR=66dB, ZERO AT 1kHz
*
ECM1 30 98 POLY(2) (1,98) (2,98) 0 0.5 0.5
RCM1 30 31 10E3
RCM2 31 98 5
CCM1 30 31 15.9E-9
*
* Latch Section
*

–10– REV. 0
 AD8611/AD8612
RX 80 51 100E3 RB4 60 62 2000
E1 10 98 (4,6) 1 CB3 99 61 0.5E-12
S1 10 11 (80,51) SLATCH1 CB4 62 51 1E-12
R2 11 12 1 RO3 66 64 1
C3 12 98 5.4E-12 D5 64 65 DX
E2 13 98 (12,98) 1 RO4 67 65 500
R3 12 13 500 EO3 63 51 (20,51) 1
* EO4 97 60 (20,51) 1
* Power Supply Section *
* * MODELS
GSY1 99 52 POLY(1) (99,50) 4E-3 -2.6E-4 *
GSY2 52 50 POLY(1) (99,50) 3.7E-3 -.6E-3 .MODEL PIX PNP(BF=100,IS=1E-16)
RSY 52 51 10 .MODEL NOX NPN(BF=100,VAF=130,IS=1E-14)
* .MODEL DX D(IS=1E-14)
* Gain Stage Av=250 fp=100MHz .MODEL SLATCH1 VSWITCH(ROFF=1E6,RON=500,
* +VOFF=2.1,VON=1.4)
G2 98 20 (12,98) 0.25 .ENDS AD8611
R1 20 98 1000
C1 20 98 10E-13
E3 97 0 (99,0) 1
E4 52 0 (51,0) 1
V1 97 21 DC 0.8
V2 22 52 DC 0.8
D2 20 21 DX
D3 22 20 DX
*
* Q Output
*
Q3 99 41 46 NOX
Q4 47 42 51 NOX
RB1 43 41 2000
RB2 40 42 2000
CB1 99 41 0.5E-12
CB2 42 51 1E-12
RO1 46 44 1
D4 44 45 DX
RO2 47 45 500
EO1 97 43 (20,51) 1
EO2 40 51 (20,51) 1
*
* Q NOT Output
*
Q5 99 61 66 NOX
Q6 67 62 51 NOX
RB3 63 61 2000

REV. 0 –11–
AD8611/AD8612
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

8-Lead micro SO 8-Lead Small Outline IC

(RM-8) (SO-8)

C3862–2.5–4/00 (rev. 0) 01541

0.122 (3.10) 0.1968 (5.00)
0.114 (2.90) 0.1890 (4.80)

8 5
8 5 0.1574 (4.00) 0.2440 (6.20)
0.122 (3.10) 0.199 (5.05) 0.1497 (3.80) 1 4 0.2284 (5.80)
0.114 (2.90) 0.187 (4.75)
1 4
PIN 1 0.0688 (1.75) 0.0196 (0.50)
x 45°
PIN 1 0.0098 (0.25) 0.0532 (1.35) 0.0099 (0.25)
0.0256 (0.65) BSC 0.0040 (0.10)
0.120 (3.05) 0.120 (3.05)
0.112 (2.84) 0.112 (2.84) 8°
0.0500 0.0192 (0.49) 0° 0.0500 (1.27)
0.043 (1.09) SEATING (1.27) 0.0098 (0.25)
0.006 (0.15) PLANE BSC 0.0138 (0.35) 0.0075 (0.19)
0.037 (0.94) 0.0160 (0.41)
0.002 (0.05) 33ⴗ
0.018 (0.46) 27ⴗ 0.028 (0.71)
SEATING 0.008 (0.20) 0.011 (0.28)
PLANE 0.003 (0.08) 0.016 (0.41)

14-Lead Thin Shrink Small Outline

(RU-14)

0.201 (5.10)
0.193 (4.90)

14 8
0.177 (4.50)
0.169 (4.30)

0.256 (6.50)
0.246 (6.25)

1 7

PIN 1
0.006 (0.15)
0.002 (0.05) 0.0433
(1.10)
MAX 0.028 (0.70)
8ⴗ
0.0256 0.0118 (0.30) 0ⴗ 0.020 (0.50)
SEATING (0.65) 0.0079 (0.20)
PLANE 0.0075 (0.19)
BSC 0.0035 (0.090)

PRINTED IN U.S.A.

–12– REV. 0