NuMicro

Architecture, System, Tools, CMSIS

NuMicro@nuvoton.com

1
 Agenda
• Block Diagram
• System Memory Map
• Power Management
• Reset Source
• Clock Control
• Interrupt
• CMSIS

2
 Product Positioning
NUC150/NUC170*2
Up to 512KB Up to 64KB 1x12-bit Ethernet Motor Cortex-M0
Flash ROM SRAM ADC MAC PWM
UART
NUC140 Connectivity Line
Up to 128KB Up to 16KB SPI
CAN LIN USB
Flash ROM SRAM
I2C
NUC130 Automotive Line ＊1
I2S
Up to 128KB Up to 16KB
CAN LIN
Flash ROM SRAM 8-channel PWM
NUC120 USB Line NUC122/NUC123 12-bit ADC
Up to 128KB Up to 16KB Up to 68KB Flash
USB Comparators
Flash ROM SRAM
20KB RAM
32-bit Timers
NUC100 Advance Line
Up to 128KB Up to 16KB Watchdog
Flash ROM SRAM
Internal 22MHz RC
M051 Base Line
＊1
Up to 64KB Up to 4KB Real Time Clock
Flash ROM SRAM
＊1
DMA
Mini51 Mini Line ＊1 : Denoted without supported
Up to 16KB Up to 2KB GPIO
in M051 or Mini51 series
Flash ROM SRAM *2 : Developing
 Product Positioning
Future products with higher density and more functionalities Cortex-M0
Up to 256KB Up to 32KB 16/24-bit 42MHz
OPAMP
Flash ROM SRAM ADC UART (x5)

Nano130 LCD + USB Advanced Line SPI (x3)

Up to 128KB Up to 16KB Touch LCD
USB I2C (x2)
Flash ROM SRAM Key x16 4x40,6x38

Nano120 USB Line I2S

Up to 128KB Up to 16KB Touch PWM (x8)

USB
Flash ROM SRAM Key x16
Smart Card (x3)
Nano110 LCD Line ( ISO7816-3)

Up to 128KB Up to 16KB Touch LCD 12-bit ADC (x12)

Flash ROM SRAM Key x16 4x40,6x38
12-bit DAC (x2)
Nano100 Base Line
32-bit Timers
Up to 128KB Up to 16KB Touch
Flash ROM SRAM Key x16 Watchdog
Ultra Low Power Consumption 12MHz +/-0.25% RC OSC
•Single Power Supply : Operating Voltage @ 1.8V ~ 3.6V 10KHz RC OSC
•Normal mode : 200uA / MHz @ CPU runs 12MHz, 3.3V
Real Time Clock
•Idle mode : 75uA / MHz @ 12MHz, CPU stop, 3.3V
•Power down mode : CPU and all clocks stop, RAM retention.
- 2..0uA @ 32.768KHz RTC turn on PDMA
- 0.8uA @ 32.768KHz RTC turn off
•Wake up time from power down mode : < 7us GPIO

4
 NuMicro Family System Introduction
• The NUC 100 series IC embed Cortex –M0 core (Up to 50Mhz)
• 32K/64K/128KB Flash memory for program memory (APROM)
• Configurable data flash address and size for 128kB system, fixed 4kB data flash for the 32kB and 64kB
system
• 4kB flash for ISP loader
• 4K/8K/16K embedded SRAM
• The M051 series IC embed Cortex-M0 core (Up to 50Mhz)
• 8KB/16KB/32KB/64KB Flash memory for program memory (APROM)
• 4KB Flash memory for data memory (DataFlash)
• 4KB Flash memory for loader (LDROM)
• 4KB SRAM for internal scratch-pad RAM (SRAM)
• The Mini51 series IC embed Cortex-M0 core (Up to 24Mhz)
• 4KB/8KB/16KB Flash memory for program memory (APROM)
• Configurable Flash memory for data memory (Data Flash)
• 2KB Flash memory for loader (LDROM)
• 2KB SRAM for internal scratch-pad RAM (SRAM)
• Wide operating voltage ranges from 2.5V to 5.5V

5
 NuMicro Family System Introduction
• The Nano series IC embed Cortex-M0 core (Up to 42Mhz)
• 32KB/64KB/123KB Flash memory for program memory (APROM)
• Configurable Flash memory for data memory (Data Flash)
• 4KB Flash memory for loader (LDROM)
• 8KB/16KB SRAM for internal scratch-pad RAM (SRAM)
• Wide operating voltage ranges from 1.8V to 3.6V
• Support ISP (In System Programming) by USB or UART
• Support 2 wire ICP ( In Circuit Programming) update from ICE interface
• Support fast parallel programming mode by external writer
• 2 wire SWD ICE interface

6
 ARM Cortex-M0 Function Block Diagram
4 Break Point
2 Watchpoint

Cortex-M0 components
Cortex-M0 processor Debug
Interrupts Nested
Cortex-M0 Breakpoint
Vectored
and
Interrupt Processor Watchpoint
Controller core unit
(NVIC)

Wakeup
Interrupt Debug
Controller Bus matrix Debugger
Access Port
(WIC) interface
(DAP)

AHB-Lite interface Serial Wire or

JTAG debug port

7
 System Memory Map
0xE000_EFFF
0xE000_E000
Cortex M0 System Register System
Reserved
0x501F_FFFF
AHB peripherals
0x5000_0000
Reserved Peripheral
0x401F_FFFF
APB peripherals
0x4000_0000
Reserved
0x2000_3FFF
0x2000_0000
16KB RAM SRAM
Reserved
0x0010_0FFF
ISP Loader Program Memory (4KB LDROM)
0x0010_0000
Reserved Code
0x0001_EBFF
Application Program Memory (123KB APROM)
0x0000_0000

8
 Power Management (1/2)
• Normal Run Mode
• Flexible system clock source selection
• All peripherals clock can be turned off individually.
• Sleep Mode (IDLE Mode)
• CPU halt, peripheral is probably under running which
depends on your application
• Deep Sleep Mode (Power Down Mode)
• CPU & peripheral are all halt

9
 Power Management (2/2)
• Sleep mode
UNLOCKREG();
CLK->PWRCTL &= ~CLK_PWRCTL_PWRDOWN_EN;
LOCKREG();
__WFI();

• Deep Sleep mode

UNLOCKREG();
CLK->PWRCTL |= CLK_PWRCTL_PWRDOWN_EN | CLK_PWRCTL_DELY_EN;
SCB->SCR |= 0x04;
LOCKREG();
__WFI();

10
 System Reset
• Hardware Reset
• The Power-On Reset
• /RESET pin Reset
• Watchdog Time Out Reset
• Low Voltage Detected Reset
• Brown-Out-Detected Reset
• Software Reset
• CPU_RST
• To write 1 to the CPU_RST( IPRSTC1[1],”IP Reset Source Register”) register
• Just only reset CPU & flash controller
• CHIP_RST
• To write 1 to CHIP_RST( IPRSTC1[0], IP Reset Source Register) register
• To reset the whole chip like “Power-on reset”
• MCU_RST
• Write 1 to the SYSRESETREQ (AIRCR[2], Application Interrupt & Reset Control Register”)
• To reset the
“RSTSRC” whole identify
register chip chip’s reset source from last operation
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 RSTSRC (System Reset Source Register)
Register Address R/W Description Reset Value

RSTSRC 0x5000_0004 R/W System Reset Source Register 0x0000_00xx

These bits are cleared by writing 1 to itself

7 6 5 4 3 2 1 0

RSTS_CPU Reserved RSTS_MCU RSTS_BOD Reserved RSTS_WD RSTS_PAD RSTS_POR

G

CPU_RST Power-on reset

/RESET Pin Reset

MCU_RST
Watchdog Reset

Brown Out Reset

12
 System Reset Source Table List

7 6 5 4 3 2 1 0
Reset Status
Reset Source RSTS_CPU Reserved RSTS_MCU RSTS_BOD Reserved RSTS_WDG RSTS_PAD RSTS_POR

Power-On Reset 0 x 0 0 0 0 1 1

Reset Pin Reset 0 x 0 0 0 0 1 0

Watchdog Time 0 X 0 0 0 1 0 0
Out Reset

Brown-Out 0 X 0 1 0 0 0 0
Reset
Cortex-M0 MCU 0 X 1 0 0 0 0 0
Reset
CHIP_RST 0 X 0 0 0 0 0 1

CPU_RST 1 X 0 0 0 0 0 0

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 Peripheral IP Reset
• Every peripheral has corresponded reset register
• “IPRST_CTL1” & “IPRST_CTL2” register had defined
the corresponded peripheral asynchronous reset
signal

14
IPRST_CTL2 (IP Reset Control Register 2)
Register Offset R/W Description Reset Value

IPRST_CTL2 0x5000_000C R/W IP Reset Control Resister 2 0x0000_0000

31 30 29 28 27 26 25 24

SC1_RST SC0_RST I2S_RST ADC_RST USBD_RST LCD_RST DAC_RST TK_RST

23 22 21 20 19 18 17 16

Reserved Reserved PWM1_RST PWM0_RST Reserved Reserved UART1_RST UART0_RST

15 14 13 12 11 10 9 8

Reserved SPI2_RST SPI1_RST SPI0_RST Reserved Reserved I2C1_RST I2C0_RST

7 6 5 4 3 2 1 0

SC1_RST Reserved TMR3_RST TMR2_RST TMR1_RST TMR0_RST GPIO_RST Reserved

•Set these bit “1” will generate synchronous reset signal to the correspond IP.
•User need to set bit to “0” to release IP from the reset state

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 Clock Control
• Clock Sources Control
• PWRCTL : Enable/Disable LIRC, HIRC, LXT and HXT output.
• PLLCTL : Enable/Disable PLL output.
• CLKSTATUS : Reports clock status.
• IP Clock Control
• AHBCLK, APBCLK : Enable/Disable individual IP clock.
• CLKSEL0, CLKSEL1, CLKSEL2 : Select IP clock source.
• CLKDIV0, CLKDIV1 : Set IP clock divider.
• Clock Monitor
• TESTCLK : Output clock (including clock sources and IP clock)
to pin PC.0.
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Clock System

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 HIRC TRIM
• Trim HIRC to 11.0592MHz, 12MHz or 12.288MHz
according to 32K (LXT).
• IRCTRIMCTL :
31 30 29 28 27 26 25 24

23 22 21 20 19 18 17 16

15 14 13 12 11 10 9 8

ERR_STOP

7 6 5 4 3 2 1 0

TRIM_RETRY_CNT TRIM_LOOP - TRIM_SEL

• [1:0] TRIM_SEL : Will be cleared once error or time-out

occurs. Software need to set and start auto-trim again.

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 HIRC TRIM
• IRCTRIMIEN : Enable/Disable trim failure interrupt.
31 30 29 28 27 26 25 24

23 22 21 20 19 18 17 16

15 14 13 12 11 10 9 8

7 6 5 4 3 2 1 0

32K_ERR_IE TRIM_FAIL_I
- -
N EN

• IRCTRIMINT : Report the trim result.

31 30 29 28 27 26 25 24

23 22 21 20 19 18 17 16

15 14 13 12 11 10 9 8

7 6 5 4 3 2 1 0

32K_ERR_IN TRIM_FAIL_I
- FREQ_LOCK
T NT

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19
 NuMicro NVIC
• NVIC (Nested Vectored Interrupt Controller)
• An integrated part of the Cortex-M0 processor
• It supports 32 peripheral interrupts input
• it supports NMI( Nonmaskable Interrupt) input
• It supports “Tail Chaining” & “Late Arrival”
• Interrupt handler follows the CMSIS coding rule

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C ISR Function Call Name

In “startup_nano1xx.s” vector
table address save peripherals
ISR function address

21
ISR Handler

22
System Peripheral Interrupt Map (16~32)
Interrupt Number
Vector
(Bit in Interrupt Interrupt Name Source IP Interrupt description
Number
Registers)

0 ~ 15 - - - System exceptions
16 0 BOD_OUT Brown-Out Brownout low voltage detected interrupt
17 1 WDT_INT WDT Watch Dog Timer interrupt
18 2 EINT0 GPIO External signal interrupt from PB.14 pin
19 3 EINT1 GPIO External signal interrupt from PB.15 pin
20 4 GPABC_INT GPIO External interrupt from PA[15:0]/PB[13:0]/PC[15:0]
21 5 GPDEF_INT GPIO External interrupt from] PD[15:0]/PE[15:0]/PF[15:0]
22 6 PWM0_INT PWM0 PWM0 interrupt
23 7 PWM1_INT PWM1 PWM1 interrupt
24 8 TMR0_INT TMR0 Timer 0 interrupt
25 9 TMR1_INT TMR1 Timer 1 interrupt
26 10 TMR2_INT TMR2 Timer 2 interrupt
27 11 TMR3_INT TMR3 Timer 3 interrupt
28 12 UART0_INT UART0 UART0 interrupt
29 13 UART1_INT UART1 UART1 interrupt
30 14 SPI0_INT SPI0 SPI0 interrupt
31 15 SPI1_INT SPI1 SPI1 interrupt
32 16 SPI2_INT SPI2 SPI2 interrupt

23
System Peripheral Interrupt Map (33~47)
Interrupt Number
Vector
(Bit in Interrupt Interrupt Name Source IP Interrupt description
Number
Registers)

33 17 IRC_INT IRC IRC TRIM interrupt

34 18 I2C0_INT I2C0 I2C0 interrupt
35 19 I2C1_INT I2C1 I2C1 interrupt
36 20 SC2_INT SC2 Smart Card2 interrupt
37 21 SC0_INT SC0 Smart Card0 interrupt

38 22 SC1_INT SC1 Smart Card1 interrupt

39 23 USB_INT USBD USB FS Device interrupt

40 24 TK_INT TOUCH Touch Key interrupt
41 25 LCD_INT LCD LCD interrupt
42 26 DMA_INT DMA DMA interrupt
43 27 I2S_INT I2S I2S interrupt
Clock controller interrupt for chip wake up from
44 28 PD_WU_INT CLKC
power-down state
45 29 ADC_INT ADC ADC interrupt
46 30 DAC_INT DAC DAC interrupt
47 31 RTC_INT RTC Real time clock interrupt

24
 General Purpose I/O Controller
• GPIO type
• Input only with high impedance
• Push-Pull Output
• Open-Drain Output
• Support Pull-Up Resistor
• 110Kohm ~ 300kohm @1.8V~3.6V
• Support GPIO interrupt for each I/O PIN
• Level trigger or Edge trigger
 Input Mode
• Just input mode
• Output is tri-state ( high impedance) without drive
capability
 Push-Pull Output
CMOS Output

VDD

Port Pin

Port Latch N
Data

Input Data
 Open-Drain Output
• Only with NMOS sink current capability

Port Pin

Port Latch N
Data

Input Data
 CMSIS
• Cortex Microcontroller Software Interface Standard
• ARM & Tool vendor (Keil, IAR..)
• Structure
• Core Peripheral Access Layer (CPAL)
• Middleware Access Layer (MWAL) (ARM is current in
development)
• Device Peripheral Access Layer (DPAL)
• Provide definitions for all device peripherals

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 CMSIS Coding Rule
• ANSI standard types defined in the ANSI C header file
<stdint.h> are used
• For each exception/interrupt
• An exception/interrupt handler rule
• exception: the postfix _Handler
• interrupts: the postfix _IRQHandler
• A # define of the interrupt number with postfix _IRQn
• A default exception/interrupt handler (weak definition) that
contains an endless loop

31
 What CMSIS Files Do You Need For NUC100 Series?
• nano1xx.h(device.h)
• Interrupt Number Definition
• Device Peripheral Access Layer
• Provides definitions for all device peripherals. It contains all data structures and the
address mapping for the device specific peripherals
• To define the peripherals for the actual device. It can use several other include
files to define the peripherals of the actual devices
• startup_nano1xx.s(startup_device.s)
• Cortex-M0 startup code and the complete Interrupt Vector Table
• system_nanoxx.c(system_device.c)

• core_cm0.h
IC Vendor Offer 3files
• core_cm0.c

ARM offer 2 files

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 NUC100 Interrupt Number Definition
typedef enum IRQn
{
/****** Cortex-M0 Processor Exceptions Numbers **************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt
*/
/****** NANO1xx Specific Interrupt Numbers ******************************************************/
BOD_IRQn = 0, /*!< Brownout low voltage detected interrupt */
WDT_IRQn = 1, /*!< Watch Dog Timer interrupt */
EINT0_IRQn = 2, /*!< External signal interrupt from PB.14 pin */
EINT1_IRQn = 3, /*!< External signal interrupt from PB.15 pin */
GPABC_IRQn = 4, /*!< External signal interrupt from PA[15:0]/PB[13:0]/PC[15:0] */ The interrupt number is
GPDEF_IRQn = 5, /*!< External interrupt from PD[15:0]/PE[15:0]/PF[15:0] */ defined in the
PWM0_IRQn = 6, /*!< PWM 0 interrupt */
PWM1_IRQn = 7, /*!< PWM 1 interrupt */ “nano1xx.h” file
TMR0_IRQn = 8, /*!< Timer 0 interrupt */
TMR1_IRQn = 9, /*!< Timer 1 interrupt */
:
:
:
I2C0_IRQn = 18, /*!< I2C0 interrupt */
I2C1_IRQn = 19, /*!< I2C1 interrupt */
SC2_IRQn = 20, /*!< Smart Card 2 interrupt */
SC0_IRQn = 21, /*!< Smart Card 0 interrupt */
SC1_IRQn = 22, /*!< Smart Card 1 interrupt */
USBD_IRQn = 23, /*!< USB FS Device interrupt */
TK_IRQn = 24, /*!< Touch key interrupt */
LCD_IRQn = 25, /*!< LCD interrupt */
PDMA_IRQn = 26, /*!< PDMA interrupt */
I2S_IRQn = 27, /*!< I2S interrupt */
PDWU_IRQn = 28, /*!< Power Down Wake up interrupt */
ADC_IRQn = 29, /*!< ADC interrupt */
DAC_IRQn = 30, /*!< DAC interrupt */
RTC_IRQn = 31 /*!< Real time clock interrupt */
} IRQn_Type;

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 startup_NUC1xx.s (1/2)
_Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved These exception names
DCD 0 ; Reserved are fixed and define the
DCD 0 ; Reserved start of the vector table
DCD 0 ; Reserved for a Cortex-M0
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler

34
 startup_NUC1xx.s (2/2)
;External Interrupts
DCD BOD_IRQHandler
DCD WDT_IRQHandler
DCD EINT0_IRQHandler
DCD EINT1_IRQHandler
DCD GPABC_IRQHandler
DCD GPDEF_IRQHandler
DCD PWM0_IRQHandler These interrupt names are
DCD PWM1_IRQHandler fixed and define the start of the
DCD TMR0_IRQHandler vector table for a Cortex-M0
DCD TMR1_IRQHandler
DCD TMR2_IRQHandler
DCD TMR3_IRQHandler
:
:
:
DCD SC2_IRQHandler
DCD SC0_IRQHandler
DCD SC1_IRQHandler
DCD USBD_IRQHandler
DCD TK_IRQHandler
DCD LCD_IRQHandler
DCD PDMA_IRQHandler
DCD I2S_IRQHandler
DCD PDWU_IRQHandler
DCD ADC_IRQHandler
DCD DAC_IRQHandler
DCD RTC_IRQHandler

35
 PWRCTL Register
(Bit Field Definition)
31 30 29 28 27 26 25 24

RESERVED

23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8

PD_WAIT_CPU

7 6 5 4 3 2 1 0

PWR_DOWN PD_WU_STS WINT_EN WU_DLY OSC10K_EN OSC22M_EN XTL32K_EN XTL12M_EN

/*---------------------------- Clock Controller ------------------------------*/

#define CLK_PWRCTL_HXT_EN ((uint32_t)0x00000001)
#define CLK_PWRCTL_LXT_EN ((uint32_t)0x00000002)
#define CLK_PWRCTL_HIRC_EN ((uint32_t)0x00000004)
#define CLK_PWRCTL_LIRC_EN ((uint32_t)0x00000008)
#define CLK_PWRCTL_DELY_EN ((uint32_t)0x00000010)
#define CLK_PWRCTL_WAKEINT_EN ((uint32_t)0x00000020)
#define CLK_PWRCTL_PWRDOWN_EN ((uint32_t)0x00000040)
#define CLK_PWRCTL_HXT_SELXT ((uint32_t)0x00000100)
#define CLK_PWRCTL_HXT_GAIN ((uint32_t)0x00000200)
#define CLK_PWRCTL_LXT_SCNT ((uint32_t)0x00000400)

36
Group Registers for fixed CLK_BA BaseAddr
(SYSCLK_T Data Type)

Register Offset

PWRCTL CLK_BA + 00
typedef struct
{ AHBCLK CLK_BA + 04
__IO uint32_t PWRCTL;
__IO uint32_t AHBCLK; APBCLK CLK_BA + 08
__IO uint32_t APBCLK;
__IO uint32_t CLKSTATUS; CLKSTATUS CLK_BA + 0C
__IO uint32_t CLKSEL0;
__IO uint32_t CLKSEL1; CLKSEL0 CLK_BA + 10
__IO uint32_t CLKSEL2;
__IO uint32_t CLKDIV0; CLKSEL1 CLK_BA + 14
__IO uint32_t CLKDIV1
__IO uint32_t PLLCTL; CLKSEL2 CLK_BA + 18
__IO uint32_t FRQDIV;
__IO uint32_t TESTCLK; CLKDIV0 CLK_BA+ 1C
__IO uint32_t WK_INTSTS;
} CLK_TypeDef; CLKDIV1 CLK_BA+ 20

PLLCTL CLK_BA + 24

FRQDIV GCR_BA + 28

WK_INTSTS GCR_BA + 30

37
 To Access Register
#define AHBPERIPH_BASE 0x50000000
#define CLK_BASE (AHBPERIPH_BASE + 0x00200)
#define CLK ((CLK_TypeDef*) CLK_BASE)

AHB Modules Space (0x5000_0000 – 0x501F_FFFF)

0x5000_0000 – 0x5000_01FF GCR_BA System Global Control Registers

0x5000_0200 – 0x5000_02FF CLK_BA Clock Control Registers

0x5000_0300 – 0x5000_03FF INT_BA Interrupt Multiplexer Control Registers

0x5000_4000 – 0x5000_7FFF GPIO_BA GPIO Control Registers

0x5000_8000 – 0x5000_BFFF PDMA_BA SRAM_APB DMA Control Registers

0x5000_C000 – 0x5000_FFFF FMC_BA Flash Memory Control Registers

CLK -> PWRCTL |= CLK_PWRCTL_HXT_EN;

38
 Cortex-M0 Core Registers Access
(core_cm0.h)
Function Definition Core Register Description

void __enable_irq (void) PRIMASK = 0 Global Interrupt enable (using the instruction CPSIE i)

void __disable_irq (void) PRIMASK = 1 Global Interrupt disable (using the instruction CPSID i)

void __set_PRIMASK (uint32_t PRIMASK = value Assign value to Priority Mask Register (using the instruction MSR)
value)

uint32_t __get_PRIMASK return PRIMASK Return Priority Mask Register (using the instruction MRS)
(void)

void __set_CONTROL CONTROL = value Set CONTROL register value (using the instruction MSR)
(uint32_t value)

uint32_t __get_CONTROL return CONTROL Return Control Register Value (using the instruction MRS)
(void)

void __set_PSP (uint32_t PSP = Set Process Stack Pointer value (using the instruction MSR)
TopOfProcStack) TopOfProcStack

uint32_t __get_PSP (void) return PSP Return Process Stack Pointer (using the instruction MRS)

void __set_MSP (uint32_t MSP = Set Main Stack Pointer (using the instruction MSR)
TopOfMainStack) TopOfMainStack

uint32_t __get_MSP (void) return MSP Return Main Stack Pointer (using the instruction MRS)

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 Cortex-M0 Instruction Access
Function Name CPU Instruction Description

void __WFI (void) WFI Wait for Interrupt

void __WFE (void) WFE Wait for Event

void __SEV (void) SEV Set Event

void __ISB (void) ISB Instruction Synchronization Barrier

void __DSB (void) DSB Data Synchronization Barrier

void __DMB (void) DMB Data Memory Barrier

uint32_t __REV (uint32_t value) REV Reverse byte order in integer value.

uint32_t __REV16 (uint16_t value) REV16 Reverse byte order in unsigned short
value.
sint32_t __REVSH (sint16_t value) REVSH Reverse byte order in signed short
value with sign extension to integer.

40
 NVIC Setup Function Call
Function Name Parameter Description
void NVIC_SetPriorityGrouping (uint32_t Priority Grouping Value Set the Priority Grouping (Groups .
PriorityGroup) Subgroups)
void NVIC_EnableIRQ (IRQn_Type IRQn) IRQ Number Enable IRQn
void NVIC_DisableIRQ (IRQn_Type IRQn) IRQ Number Disable IRQn
uint32_t NVIC_GetPendingIRQ (IRQn_Type IRQ Number Return 1 if IRQn is pending else 0
IRQn)
void NVIC_SetPendingIRQ (IRQn_Type IRQn) IRQ Number Set IRQn Pending
void NVIC_ClearPendingIRQ (IRQn_Type IRQn) IRQ Number Clear IRQn Pending Status
void NVIC_SetPriority (IRQn_Type IRQn, IRQ Number, Priority Set Priority for IRQn
uint32_t priority)
uint32_t NVIC_GetPriority (IRQn_Type IRQn) IRQ Number Get Priority for IRQn
uint32_t NVIC_EncodePriority (uint32_t IRQ Number, Priority Group, Encode priority for given group,
PriorityGroup, uint32_t PreemptPriority, Preemptive Priority, preemptive and sub priority
uint32_t SubPriority) Sub Priority
NVIC_DecodePriority (uint32_t Priority, uint32_t IRQ Number, Priority, Decode given priority to group,
PriorityGroup, uint32_t* pPreemptPriority, pointer to Priority preemptive and sub priority
uint32_t* pSubPriority) Group, pointer to
Preemptive Priority,
pointer to Sub Priority
void NVIC_SystemReset (void) (void) Resets the System

41
 Q&A

Thank You

42