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Rachit Agarwal - RTL PDF

This document contains a resume for Rachit Agarwal summarizing his professional experience and skills. He has over 8 years of experience in RTL design, FPGA, wireless communications and embedded systems. Some of his projects include designing FPGA IP cores for signal processing algorithms, communication protocols and standards. He is proficient in VHDL, Verilog and tools like Xilinx ISE and Vivado.

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Gaurav Pratap
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155 views5 pages

Rachit Agarwal - RTL PDF

This document contains a resume for Rachit Agarwal summarizing his professional experience and skills. He has over 8 years of experience in RTL design, FPGA, wireless communications and embedded systems. Some of his projects include designing FPGA IP cores for signal processing algorithms, communication protocols and standards. He is proficient in VHDL, Verilog and tools like Xilinx ISE and Vivado.

Uploaded by

Gaurav Pratap
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Rachit Agarwal Mobile: +91- 8800776757

Immediate Joiner E-mail: rachitagarwal37@yahoo.co.in

PROFESSIONAL SUMMARY
 8+ years of relevant experience of in the field of RTL Design, FPGA, Wireless communication
and Embedded Systems.
 Experience in Design, Development and Testing of Micro architecture on FPGA and
Embedded systems.
 Worked during various phases of System Development Life Cycle of project such as
Investigation, Analysis, Design, Implementation, Diagnostics and Testing/ Debugging.
 Experience in developing FPGA-IP of Various Interfacing protocols from Specifications and
Standards.
 Excellent Problem solving and Debugging skills.
 Experience in CDC, STA, ECO process, tool flows and System Analysis.
 Working experience in tools as Xilinx ISE, VIVADO and Altera-Quartus.
 RTL Design for OFDM (Orthogonal Frequency Division Multiplexing) physical layer 1.
 Programming Language knowledge of RTL Coding VHDL, Verilog, MATLAB, C, and Assembly.
 Working experience in writing RTL coding interfaces of PCIe, McBSP, EMIF, SPORT, I2C, UART
and SPI Communication bus.
 Experience in Cryptographic Algorithms (3-DES, AES) development on FPGA platforms.
 Experience in RTL code development of Avionics Communication Standards (ARINC 429, MIL-
STD 1553 B) on FPGA platforms.
 Experience in FPGA based Tactical navigation communication standards DME-TACAN.
 Basic Knowledge of LTE , 4G communication standards, Xilinx Zynq SOC.
 Experience in interfacing with RF chips (Synthesizer chip, ADC, DAC, Modulator, Demodulator,
Comparator, RF Detector, RF Switches, Amplifiers and Attenuators).
 Excellent communicator with strong interpersonal, documentation and presentation skills, able
to build internal and external relationships, work with minimal direction and make the
difference to the bottom line.

TECHNICAL SKILLS:
Programming Language: VHDL, Verilog, MATLAB, Simulink, C, C++, Assembly.
Debugger Tools:
 Synthesis : Xilinx ISE,VIVADO, Altera (Quartus 8.1).
 Simulator : ModelSim, ISE-SIM.
 Debugging and Testing : ChipScope Pro Analyzer , ILA.
 System Design : Matlab Simulink, Xilinx System Generator,MATLAB.
 C/C++ Coding : TI Code composer studio, Keil, Eclipse, VisualDSP.

RTOS: Integrity, VDSP Kernel.


Debugger Tools: Agilent16802A Logic-Analyzer, Agilent Vector signal
generator , Agilent Spectrum analyzer.
Processors and Controllers: TI OMAP L138 (ARM 9), TI DM6446 (ARM 9), 8051, TI
MSP4302274, ADSP BF537, ADSP BF561, ADSP 21060
(SHARC).

PROFESSIONAL EXPERIENCE:
 Professional Freelancer working from April 2019 till now.
 Team Lead in WESEE, Ministry Of Defence from June 2010 to March 2019.
 Senior Software engineer in EmWiB Technologies Pvt Ltd fom April 2006 to May 2010.

Projects Undertaken In Weapons and Electronics Engineering Establishment


(WESSE), Ministry Of Defence.

1. Design of Squelch module for audio detection : FPGA-IP


Squelch logic modifications in AMSSB waveform on FPGA platform for SDR-AR. Squelch is
intelligent to differentiate between noise and voice speech
 Created micro architecture for Squelch using MATLAB.
 Implemented RTL design on Xilinx FPGA using VIVADO.
2. Design of Timing Synchronization Module for Boundary detection. : FPGA-IP
This algorithm uses correlation algorithm for frame boundary detection and timing
synchronization error.
 Created micro architecture for Synchronization using MATLAB.
 Implemented RTL design on Xilinx FPGA using VIVADO.
3. Design of McBSP and EMIF Module for interfacing between FPGA and DSP: FPGA-IP
RTL code for McBSP and EMIF interface used in waveform development on DLRFU unit
and SDR –TAC platforms. McBSP interface is used to provide interface between FPGA and
DSP. processor. EMIF module provides interface between FPGA and ARM.
 Implemented RTL design on Xilinx FPGA using VIVADO.
4. Design of DDC and DUC Module for Decimation/Interpolation: FPGA-IP
Both DUC and DDC is programmable for IF frequency output for DUC and IF input frequency
for DDC. Both DUC and DDC configured to integrate with Low data rate waveform, High data
rate waveform and Voice waveform.
 Created MATLAB Simulink architecture for DDC/DUC using Xilinx System Generator.
 Implemented RTL design on Xilinx FPGA Virtex 6.
5. Design of OFDM Physical layer 1 MODEM for V/UHF band : FPGA-IP
This parallel tone modem is to provide the reliable and robust waveform to perform the
talks in V/UHF band. This design is based on DOD MIL-STD 188-110 b.
 Tone detection in CSMA, Doppler correction, Timing Synchronization and DQPSK
Modulation/Demodulation algorithms are developed.
 CSMA algorithm design and development for V/UHF MODEM on FPGA.
 Created MATLAB Simulink Design architecture for Transmitter and receiver using
Xilinx System Generator.
 Implemented RTL design on Xilinx FPGA Virtex 6.

6. Design of High Speed OFDM Physical layer 1 MODEM for V/UHF band: MATLAB-IP
A MATLAB design and development of transmitter and receiver OFDM waveform, designed
to work in VHF/UHF band, providing high bit rate of 96 kbps (MIL-STD 188-110C) standard
using 25 KHz wideband port of Radio..
 Created MATLAB Design architecture for Transmitter and receiver using Xilinx
System Generator.
 Cyclic Shift PTS PAPR algorithm is used to mitigate the effect of PAPR in OFDM.
7. Optimization of Wireless OFDM Modem (MIL-STD 188-110A standard)
To increase the reliability of communication over wireless network especially in HF
environment where noise factor is more prominent. These modules which are optimized and
developed
 Tone detection in CSMA algorithm
 Doppler correction algorithm
 Timing Synchronization algorithm
 DQPSK Modulation/Demodulation
8. HARQ IP design and development .
Hybrid Automatic repeat request is a feature used for positive and negative
acknowledgement.
 It is developed on application layer .
9. MELP based Digital Voice application.
Mixed excitation linear predictive coding is to provide the high level audio compression to
send the data digitally by embedding it into waveform as data for security and reliability.
 It is developed on ARM processor.
10. Digital Broadcast Radio modem System development for indian navy emergency group.
11. Working Experience of Testing, installation, Ground Trials, Harbor Trials, Sea Trials done on
all Navy platforms such as War Ships , Helicopters, Aircrafts and Submarines at all
Indian Naval Base stations.

Projects Undertaken in EmWiB Technologies Pvt. Ltd, Hyderabad


1. RTL Design & Development of PCI Based MIL-STD 1553 B Bus Simulator : FPGA-IP

 PCI Card to provide two MIL-STD1553B channels functionalities through PCI


PLX9030 by using Altera-cyclone3 FPGA.
2. RTL Design & Development for 802.16d standard of WiMAX : FPGA-IP

 RTL Design and Coding for Mapper-Demapper,


 RTL Design and Coding for Randomizer
 RTL Design and Coding for MD5(message digest) ,
 RTL Design and Coding for Cryptographic algorithms AES ( Advanced Encryption
Standard).
 RTL Design and Coding for Cryptographic algorithms Triple DES( Data Emcryption
Standard).
3. RTL Design and Development of DME-TACAN : FPGA-IP

This is Distance measurement and Tactical Navigation Equipment to provide the distance
and direction information to aircraft in the air.
 RTL Design and Coding for Ground Station Simulator using RF components
(Synthesizers(ADF4113),Mixed Signal Processor ADC/DAC AD9860 Modulator,
Demodulator, Comparator, RF Detector, RF Switches, Attenuators, and Amplifiers
etc) .
4. RTL Design & Development of ARINC-429 Simulator : FPGA-IP

 It uses Altera-cyclone3 FPGA, USB-FTDI245R.


5. Embedded Design & Development of Motion Sensor Accelerometer
 It uses FreeScale MMA7660 accelerometer, TI-MSP4302274, SPLC501C LCD display.
6. Embedded Design & Development of MIL-STD1553B Compact Bus Simulator

 It uses ADSP BF537, FTDI 245R (USB Controller), HOLT- 6110.


EDUCATION
 Completed PG Diploma in VLSI in 2006 from University of Pune.
 B.Tech. completed in 2005 in Electronics and Communication, from Kurukshetra University,
Haryana, securing 68 % marks.
 SSC with 78% and Intermediate with 67% from U.P Board.

REFERENCE:
Available on request.
Relocate to Anywhere.

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