Scribd
Upload
52 views

Verilog

This document describes the difference between blocking and non-blocking statements in SystemVerilog, how inertial delay differs from transport delay, and provides solutions for questions about conditional signal assignments, always blocks, and implementing a state machine for an electronic lock system using behavioral VHDL constructs. It also includes a state diagram and simulation results.

Uploaded by

Muhammad Moin
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
52 views

Verilog

This document describes the difference between blocking and non-blocking statements in SystemVerilog, how inertial delay differs from transport delay, and provides solutions for questions about conditional signal assignments, always blocks, and implementing a state machine for an electronic lock system using behavioral VHDL constructs. It also includes a state diagram and simulation results.

Uploaded by

Muhammad Moin
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 8

[DOCUMENT TITLE]

[Document subtitle]

[DATE]
[COMPANY NAME]
[Company address]
Q1 (a) What is the difference between blocking and non-blocking statements in System
Verilog?
Solution: Blocking Statement: A blocking statement should be executed before the execution of
the statements that follow it in a sequential block, for example
a=b ;
Nonblocking Statements: Nonblocking statements allow us to schedule assignments
without blocking the procedural flow, for example.
module block_nonblock();
reg a, b, c, d , e, f ;

// Blocking assignments
initial begin
a = #10 1'b1;// The simulator assigns 1 to a at time 10
b = #20 1'b0;// The simulator assigns 0 to b at time 30
c = #40 1'b1;// The simulator assigns 1 to c at time 70
end

// Nonblocking assignments
initial begin
d <= #10 1'b1;// The simulator assigns 1 to d at time 10
e <= #20 1'b0;// The simulator assigns 0 to e at time 20
f <= #40 1'b1;// The simulator assigns 1 to f at time 40
end

end module;

Q1 (b) How does inertial delay differ from transport delay?


Solution: Inertial delay models only propagate signals to an output after the input signals have
remained unchanged (been stable) for a time period equal to or greater than the
propagation delay of the model. Transport delay models propagate all signals to an
output after any input signals change
Q1(c) What is the output of S, after the following command?
assign S = 8’b10;

Solution: The simulator assigns 10 to S at time 8.

Q1(d) What would be the synthesis result of the following statement? assign
y = x ? (a + b):(c + d) ;
y =a + b;
x =c +d;

Q2 Write the equivalent always statement for the following conditional signal assignment
statement?
module examQ2 (en,sel,a,b,x,y,f);
output logic f;
input en, sel,a,b,x,y;
assign f = (en && ~sel) ? (a & b): ((en && sel) ? (x + y): 0);
end module
Solution: The equivalent always statement will be
always @( sel∨en∨a∨b∨x∨ y )
Q3 Two students came up with the following System Verilog codes (A and B) for the same
problem. Briefly explain whether they would produce the same behavior or not. Note
that both codes have the same entity?

Solution: Both the Verilog codes (A or B) will not produce the same behavior. As always@
blocks are used to describe events that should happen under certain conditions.
Elements in an always@ block are set/updated in sequentially and in parallel,
depending on the type of assignment used. There are two types of assignments: <=
(non-blocking) and = (blocking).
Below the structure of always@ block is given
1. always @ ( ... sensitivity list ... ) begin
2. ... elements ...
3. End
As in code B negedge reset is missing in always @ (Step 4). So, in the output the same
behavior cannot be observed either.
Q4 A System Verilog module is shown below which uses blocking and non-blocking
statements.
module Q4;
int a, b,c;
logic clk;
initial begin b = 0;
a = 0; clk = 0;
end
always #50 clk = ~clk;
always @(posedge clk) begin
a <= b + 2;
b <= a + 3;
c = b + a;
end
end module
Solution:
(a) What are the initial values for clk, a, b and c?
The initial values of clk, a ,b and c are zero
(b) After the first rising edge of the clk, what is value of c at the end of this always
block?
The value of c at the end of this always block will be five
(c) After the next rising edge of the clk, what is value of c at the end of this always
block?
The value of c at the end of this always block will be ten.
Q5 A simple synchronous electronic lock system has three external inputs (clk, input and
lock) and one output (locked). The lock can be opened using an internally known
combination C3C2C1C0. The state of the lock is indicated by the output locked. Once
unlocked (locked = 0) the lock should remain unlocked until the lock input is true. Once
locked, the lock will remain locked until it has seen the initiation sequence “000"
followed by the correct combination C3 = 0; C2 =1; C1 = 1; C0 = 0 on the input?

(a) List the inputs and outputs required for this controller.
The input of the controller is given as
clk, input and lock
which will be written as
input clk, input, lock;
The input of the controller is given as
locked
which will be written as
output locked;

(b) Construct a Mealy type state diagram that describes the operation of the controller

0/1 0/0 1/1 1/0 1/ 1 1/0 0/0

C0- C1 C2 C3
0/1
(b) Implement the state diagram in (b) using behavioral style VHDL constructs. A state
machine template is available in Appendix. You should ensure that your code is well
commented.

Solution:

module mealyFSM(in, clk, rst, out);


input in, clk, rst;
output logic out;
enum {S0,S1,S3} cstate, nstate;
// state transition logic
always_comb
begin
case (cstate)
when A0 => if x = '0' then
z < = '0';
next_state < = A1;
else
next_state < = A0;
z < = '1';
end if;
when A1 => if x = '1' then
z < = '0';
next_state < = A2;
else
next_state < = A0;
z < = '1';
end if;

when A2 => if x = '1' then


z < = '0';
next_state < = A3;
else
next_state < = A0;
z < = '1';
end if;
when A2 => if x = '0' then
z < = '0';
next_state < = A3;
else
next_state < = A0;
z < = '1';
end if;
when A3 => if x = '1' then
z < = '0';
next_state < = A3;
else
next_state < = A0;
z < = '1';
end if;

default: nstate <= S0;


endcase
end
// state register
always_ff @(posedge clk or rst)
if (rst)
cstate <= S0;
else
cstate <= nstate;
// output logic
always_comb
begin
case (cstate)
S0: A0;
S1: A1;
S2: A2;
S3: A3;
endcase
end
endmodule
(c) Simulate the design taking into account the possible input scenarios. Save a
screenshot of your simulation file in the same folder.

You might also like

pFad - Phonifier reborn

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.

Note: This service is not intended for secure transactions such as banking, social media, email, or purchasing. Use at your own risk. We assume no liability whatsoever for broken pages.


Alternative Proxies:

Alternative Proxy

pFad Proxy

pFad v3 Proxy

pFad v4 Proxy