SNC7001A

16-bit Processor

======== CONTENTS ========

1. INTRODUCTION....................................................................................................................................... 4

2. FEATURES ................................................................................................................................................. 4

3. PIN ASSIGNMENTS.................................................................................................................................. 5

4. MEMORY ................................................................................................................................................... 6

4.1 INTERNAL RE-BOOT PROGRAM RAM................................................................................................... 7

4.2 INTERNAL USER RAM.......................................................................................................................... 7
4.3 EXTERNAL PROGRAM MEMORY ........................................................................................................... 8

5. SYSTEM CLOCK....................................................................................................................................... 8

6. I/O PORT..................................................................................................................................................... 8

7. TIMER/COUNTER .................................................................................................................................. 10

8. INTERRUPT ............................................................................................................................................. 11

9. EXTERNAL STORAGE DEVICES........................................................................................................ 12

9.1 EXTENSION BUS ................................................................................................................................. 12

9.2 SPI FLASH CONTROLLER .................................................................................................................... 12
9.3 NAND FLASH / SD CARD INTERFACE ................................................................................................ 12

10. AUDIO CODEC ................................................................................................................................... 12

10.1 ADC................................................................................................................................................... 12
10.2 AUDIO DAC ....................................................................................................................................... 12

11. 10-BIT SAR ADC ................................................................................................................................. 13

12. CMOS IMAGE SENSOR (CIS).......................................................................................................... 13

13. LCD INTERFACE ............................................................................................................................... 13

14. COMMUNICATION INTERFACE................................................................................................... 13

14.1 USB INTERFACE ................................................................................................................................. 13

14.2 UART INTERFACE .............................................................................................................................. 13
14.3 I2S INTERFACE ................................................................................................................................... 13
14.4 MSP INTERFACE ................................................................................................................................ 14
14.5 SPI INTERFACE ................................................................................................................................... 14

Ver 1.5 1 2013/11/07

 SNC7001A
16-bit Processor

15. MULTI FUNCTION OF I/O ............................................................................................................... 15

16. REGULATOR ...................................................................................................................................... 17

17. ABSOLUTE MAXIMUM RATING .................................................................................................. 17

18. ELECTRICAL CHARACTERISTICS .............................................................................................. 17

19. BONDING INFORMATION .............................................................................................................. 19

20. REFERENCE SCHEMATIC.............................................................................................................. 20

Ver 1.5 2 2013/11/07

 SNC7001A
16-bit Processor

AMENDENT HISTORY
Version Date Description
Ver 1.0 2011/11/11 First Issue
Ver 1.1 2011/11/21 Modify NAND flash IF function, it is “Read only” mode
Ver 1.2 2011/12/19 a. Modify CS2 mapping address from 8M to 4M bits
b. Modify SD-Audio DAC SNR from 90dB to 80dB
Ver 1.3 2012/04/16 a. Update typo at GPIO number at P4 (page 6)
b. Adds contents at Electrical Characteristics chapter
Ver 1.4 2012/06/15 a. Adds testing temperature.
b. Adds Chap 19 : Reference Schematic
Ver 1.5 2013/11/07 Add Chap 17: Absolute Maximum Rating

Ver 1.5 3 2013/11/07

 SNC7001A
16-bit Processor

1. Introduction
The SNC7001A is a 16-bit DSP processor. It runs at 48MHz with 48MIPS high performance
processing speed. Therefore, the SNC7001A is applicable to process voice recognition and
picture display related algorithms. The memory includes a 32KW Program RAM and 16KW
Working RAM. The 32KW Program RAM supports re-bootable function in order to develop
more complex application programs.
Peripherals embedded in the SNC7001A include NAND FLASH with ECC controller (read
only), SD/MMC controller, USB device, LCD Interface, UART interface, MSP, SPI
master/slave interface, CMOS Image Sensor controller, PWM Output, Audio ADC and DAC,
I2S and SAR ADC.

2. Features
♦ Built-in 16-bit DSP core
♦ 48 MIPS CPU Performance under 48MHz, 1 Clock per 1 Instruction.
♦ Clock Type:
− 48MHz for system clock
− 32768Hz for system clock
♦ High Speed Clock Source (pumping from 12MHz
48MHz by PLL circuit)
− 12MHz crystal oscillator
− 12MHz IHRC
♦ Low Speed Clock Source:
− 32768Hz crystal oscillator
− 32768Hz external Rosc
♦ Operation Mode:
− Normal mode (hi-speed clock enable)
− Slow mode 1 ( hi-speed clock enable, PLL disable, slow-speed clock disable)
− Slow mode 2 (hi-speed clock disable, slow-speed clock enable)
− Watch mode (chip entry power-down mode and wake-up per 0.5/1 sec
automatically)
− Power-down mode (both hi-speed and low-speed clock disable)
♦ Three 16-bit Timers, 1 Watch Dog Timer, 1 RTC
− Timers with Individual pre-scalar and auto-reload function
− Event Counter (Combine Timer and Input Pin P0.0~P0.2)
− Watch Dog Timer (WDT) with 0.25/0.5/1/2-sec period
− RTC with 0.5/1-sec period
♦ Interrupt Sources
− 1 for ADC, 3 for Timers, 1 for RTC, 1 for SPI, 1 for AD, 1 for DA, 1 for I2S, 1 for MSP
− 3 for External (P0.0~P0.2), 1 for USB, 1 for NAND Flash, 4 for DMA
♦ 32K * 16 Internal Program RAM (need boot form external flash storage)
♦ Total 16K*16 Internal RAM memory configuration for Program and working RAM
− Mode 0: 8K*16 Program RAM + 8K*16 Working RAM
− Mode 1: 4K*16 Program RAM + 12K*16 Working RAM
− Mode 2: 12K*16 Program RAM + 4K*16 Working RAM (default)
− Mode 3: 16K*16 Working RAM

Ver 1.5 4 2013/11/07

 SNC7001A
16-bit Processor
♦ Support Barrel Shifter and 16×16 to 32-bit multiplier
♦ DMA provided (USB/NandFlash/SD/LCD/SPI)
♦ Built-in ICE Debug Function

3. Pin Assignments
Symbol Descriptions No. of Pin Pin Count
VDDA_LDO Power for Regulator 1 1
VDDAL_LDO Regulator voltage output 1 2
VSSA_LDO Regulator Ground 1 3
VDD Power + for core 5 8
VSS Power - for core 5 13
VDDDP Power for IO 6 19
VSSDP GND for IO 7 26
VDD_DAC Power for Audio DAC 2 28
VSS_DAC GND for Audio DAC 2 30
VCOM Audio DAC Common mode output 1 31
DAC_VMID Audio DAC VMID output 1 32
VDDA_DRV Audio DAC Driver Power 2 34
VSSA_DRV Audio DAC Driver GND 2 36
VOUTP Audio DAC output (+) 1 37
VOUTN Audio DAC output (-) 1 38
ADC_VMID SD ADC VMID output 1 39
MICBIAS SD ADC Microphone Bias Voltage output 1 40
FMIN SD ADC FM signal input pin 1 41
AUX SD ADC AUX signal input pin 1 42
VDDA_ADC Power for SD ADC 2 44
VSSA_ADC GND for SD ADC 2 46
MIC_N SD ADC MIC difference input (-) 1 47
MIC_S SD ADC MIC single input 1 48
MIC_P SD ADC MIC difference input (+) 1 49
VDDA_SAR Power for SAR ADC 2 51
VSSA_SAR GND for SAR ADC 2 53
AVREFH Reference Voltage for SAR ADC 1 54
AIN[3:0] SAR ADC Anlong input pin 4 59
VO1 Thermal DAC Output 1 60
XIN_12M High speed clock crystal input 1 61
XOUT_12M High speed clock crystal output 1 62
XIN_32K Low speed clock crystal input 1 63
XOUT_32K Low speed clock crystal output 1 64
CKSEL Crystal/RC-type oscillator select for high 1 65
speed clock
RSTB Chip reset 1 66
TEST For test only 1 67
PHY_DM USB Data + 1 68
PHY_DP USB Data - 1 69
VDDA_PHY USB power + (3.3V) 2 71

Ver 1.5 5 2013/11/07

 SNC7001A
16-bit Processor
VDDAL_PHY USB power + (1.8V) 2 73
VSSA_PHY USB power - 2 75
P0.0~P0.15 General I/O port P0.0~P0.15 16 91
P1.0~P1.15 General I/O port P1.0~P1.15 16 107
P2.0~P2.15 General I/O port P2.0~P2.15 16 123
P3.0~P3.15 General I/O port P3.0~P3.15 16 139
P4.0~P4.11 General I/O port P4.0~P4.11 12 151
ICE ICE Interface 5 156
CODE_SEL Standalone Boot Path Select 1 157

4. Memory
There are 32KW Program Boot RAM and 16KW User RAM in SNC7001A. It boots program
code into Program Boot RAM from an external storage device and then begins to run at
program address 0x0000. The SNC7001A has 16KW RAM which has four modes of
configuration (Mode 0~Mode 3) to select the Program RAM and Working RAM size for
different application.

0x0000

Re-boot SPI
P-RAM Flash
(32KW)

NOR
0x7FFF
Arbiter Flash
0x0000

User
Mask
RAM
ROM
(16KW)

0x3FFF

Ver 1.5 6 2013/11/07

 SNC7001A
16-bit Processor
4.1 Internal Re-boot Program RAM
There is 32KW of SNC7001A boot program RAM. User built-in his own program and
SNC7001A algorithm library in the boot program RAM for his application. After reset, it will
boot user’s code into internal 32KW P-RAM from external storage (SPI Flash, NOR Flash or
Mask ROM) automatically. During operation mode, user can also reload other code into the
internal P-RAM at address 0x0800 ~ 0x7FFF. This area can be thought of as (warm) “Re-boot
area“. If the user wants to execute a (cold) Re-boot action, the DSP program counter MUST
be set to 0x0000 ~ 0x07FF area until the true Re-boot action is finished.

Address Range Size Usage DSP DMA

(word)
0x000000 ~
2K Program RAM R --
0x0007FF
0x000800 ~
30K Program RAM R R/W
0x007FFF

4.2 Internal User RAM

Total 16K*16 Internal RAM memory configuration for Program and Working RAM
− Mode 0: 8K*16 Program RAM + 8K*16 Working RAM
− Mode 1: 4K*16 Program RAM + 12K*16 Working RAM
− Mode 2: 12K*16 Program RAM + 4K*16 Working RAM (default)
− Mode 3: 16K*16 Working RAM

Mode 0 Mode 1

0x0000 0x0000

WRAM
8KW address
WRAM
12KW
address
0x1FFF
0x200000

PRAM 0x2FFF
8KW address 0x200000
PRAM
4KW address
0x201FFF 0x200FFF

Ver 1.5 7 2013/11/07

 SNC7001A
16-bit Processor
Mode 2 Mode 3

0x0000 0x0000
WRAM
4KW address
0x1FFF
0x200000

WRAM
16KW
address
PRAM
12KW address

0x201FFF 0x3FFF

4.3 External Program Memory

Size
Address Range Usage DSP DMA
(word)
0x400000 ~ CS1 SPI Flash
8M R R/W
0xBFFFFF /CS1 NOR Flash
0xC00000~
4M CS2 NOR Flash R R/W
0xFFFFFF

5. System Clock
SNC7001A is a dual clock system that provides high-speed clock (12MHz crystal up to 48MHz)
and low-speed clock (12MHz or 32768Hz). The SNC7001A uses an internal PLL to up sample
clock speed to 48MHz.

6. I/O Port
SNC7001A provides a total of 76 I/O pins (P0.0~P4.11) and 4 inputs pins (P4.12~P4.15,
which shares with SAR ADC pins). The input pull-high resistor of each pin can be individually
programmed by port pull-high register and the direction of I/O port is selected by port direction
register. The I/O port P0.0~P0.15 and P1.0~P1.15 can wake up the chip from the standby
mode.
These 76 programmable I/O pins and 4 input pins provide not only a simply input/output
function but also can configure to be chip select pins of extension bus and multi-function
peripheral interfaces. For details please refer to the following sections. Analog input pins
(AIN0~AIN3) of SAR ADC can be selected to act as digital input only, please refer Figure-2.
The internal structure of I/O pins is showed in Figure-1.

Ver 1.5 8 2013/11/07

 SNC7001A
16-bit Processor

Pull-Up
Resister
In/Out
Pull-Up Control
Select

I/O
PAD

Data Gate
to internal
bus

In/Out
Control

I/O Configuration of Port0.0 ~ Port4.11

Figure-1

Configuration of Port4.12 ~ Port4.15

Figure-2

Ver 1.5 9 2013/11/07

 SNC7001A
16-bit Processor

7. Timer/Counter
SNC7001A provides three 16-bit timer/event counters (T0/T1/T2). Each timer is 16-bit
binary up-count timer with pre-scalar and auto-reload function.

/2 (16-bit)
TnC Time Out
/4
16-bit
system clock /2 /8 MUX Up-Counter
comparator

/512
clear
Enable
Pre-scalar

Auto-reload

Figure-3

Ver 1.5 10 2013/11/07

 SNC7001A
16-bit Processor

8. Interrupt
At the moment when SNC7001A enters the interrupt service routine, the GIE bit (in INTEN)
will be cleared to "0“ for blanking other interrupts. However, during this stage, other enabled
interrupt sources still can issue their requests but the requests are queued in INTRQ. GIE
will be restored to “1” while DSP exits ISR. Then the other valid interrupt can be granted and
served immediately.

Interrupt Vector Priority Entry Location Descriptions

Reset x 0x000000 Reset
reserved 0 0x000010
AD 4 0x000014 AD FIFO full
T0 5 0x000018 T0 overflow
P0.0 (UART RxD) 6 0x00001C Falling/Raising edge of P0.0
T1 7 0x000020 T1 overflow
P0.1 (UART TxD) 8 0x000024 Falling/Raising edge of P0.1
T2 9 0x000028 T2 overflow
P0.2 10 0x00002C Falling/Raising edge of P0.2
reserved 9 0x000030
DA 11 0x000034 DA FIFO empty
SPI 3 0x000038 SPI Interrupt
MSP(I2C) 2 0x00003C MSP Interrupt
I2S 1 0x000040 I2S Interrupt
reserved 0x000044
reserved 0x000048
reserved 0x00004C
USB 12 0x000050 USB Interrupt
CIS_HREF 13 0x000054 CIS HREF Interrupt
RTC 14 0x000058 RTC overflow
NF 15 0x00005C NF Interrupt
DMA_CIS_W 16 0x000060 DMA_CIS_W Interrupt
DMA_NF_RW 17 0x000064 DMA_NF_R & DMA_NF_W Interrupt
SAR_AD 18 0x000068 SAR ADC interrupt
reserved 19 0x00006C
reserved 20 0x000070
reserved 21 0x000074
DMA_DEV_RW 22 0x000078 DMA_DEV_R & DMA_DEV_W nterrupt

Ver 1.5 11 2013/11/07

 SNC7001A
16-bit Processor

9. External Storage Devices

9.1 Extension Bus

SNC7001A contains a built-in standard 8080 micro-controller interface to extend the memory
capability through an extension bus. In addition, the SNC7001A provides a word mode access
bus for external memory devices in order to improve efficiency.
The extension bus also allows users to connect different external devices for various
applications, such as ROM, RAM, LCM, NOR flash etc.
The SNC7001A can connect to up to two different devices with two available chip select pins.
The maximum addressing capability of CS1 is 128M bits and CS2 is 64M bits. User can put his
program into each external memory device.

9.2 SPI Flash Controller

SNC7001A has a built-in SPI Flash controller interface to support 1/2/4 bit read/write mode,
it can run 6/12/24/48 MHz clock frequency. In additional, SNC7001A can run programs from
SPI Flash (at a much reduced rate).

9.3 NAND Flash / SD Card Interface

The flash memory (Mass-storage) interface provides an interface between Mass storage and
SNC7001A DSP core. It supports 2 types of storage memory: NAND Flash (read only) and
SD Card.
- NAND Flash Controller just support read only function, and compatible Xtra-ROM
interface.
- SD Card Controller support SD Card1.0/2.0 commands (SDSC/SDHC)

10. Audio CODEC

10.1 ADC
In SNC7001A, we provide one set of high performance one channel Analog-to-Digital
Converter (ADC) for microphone applications with typical SNR at 90dB. This Analog-to-Digital
Converter has a built-in PGA (-12dB ~ +33dB), BOOST (0 ~ +30dB) and true AGC control. It
supports 8/12/16/22.05/24/32/44.1/48KHz sample rates.

10.2 Audio DAC

In SNC7001A, we provide 2 types DAC outputs for different applications. One is a 16-bit DAC
+ Class AB embedded, and its typical SNR is 80dB. It can drive L/R channel Earphone. The
other one is thermal DAC, and its typical SNR is 65dB. A 16x16 FIFO is used to prevent the
sound glitch when CPU is busy. They all support 8/12/16/ 22.05/24/32/44.1/48KHz sample
rates.

Ver 1.5 12 2013/11/07

 SNC7001A
16-bit Processor
11. 10-bit SAR ADC
SNC7001A has a built-in SAR ADC, which has 4-input sources with up to 1024-step resolution
to transfer analog signal into 10-bits digital data. The sequence of ADC operation is to select
input source (AIN0 ~ AIN3) first, then set CHS and START bit to “1” to start conversion. When
the conversion is complete, the ADC circuit will set START bit to “0” and final value output will
reside in the ADR register. In SNC7001A, we provide an interrupt to inform user program that
the ADC result is ready. However, the interrupt event is optional.

12. CMOS Image Sensor (CIS)

The CIS Interface communication is based on an advanced 12-pin interface - CIS Clock,
VSYNC, HREF, Pixel Clock and eight Data Lines. Frequency of CIS Clock which output to CIS
module can be chosen among 24MHz and 12MHz. VSYNC, HSYNC and Pixel Clock signals
from the CIS Module can be set up for active timing at rising or falling edges. An interrupt flag
will be issued after a line of data is transmitted to Working RAM which informs the system to
access data that is stored at Working RAM.
- Support VGA/ CIF/ QVGA/ QCIF/ QQVGA resolution
- Support CMOS Image Sensor output 16bits RGB565/YUVand 8-bit RGB data formats
- Support Window Setting and Scaling

13. LCD Interface

The SNC7001A has a built-in LCD controller interface which supports up-to 320*240 LCD
Panel and 1/4 bit data bus for monochrome/gray-scale LCD.

14. Communication Interface

14.1 USB Interface
The SNC7001A provides a USB 2.0 High Speed (480MHz) interface (includes 4 endpoint);
user can download/upload data from/to PC through this USB interface. It supports control
transfer, interrupt transfer and bulk transfer. SNC7001 provides twin 512byte buffers for bulk
in/out transition, one 64byte buffer for control transition and one 16byte buffer for interrupt
transition.
EP0: Control transfer
EP1: bulk-in (mass-storage, DSP
PC)
EP2: bulk-out (mass-storage, PC
DSP)
EP3: interrupt-in (HID, DSP
PC)

14.2 UART Interface

Users can download data from PC through this UART interface. The standard UART interface
provides the below baud rates:
1200/2400/4800/9600/19200/38400/51200/57600/102400/115200 bps

14.3 I2S Interface

Built-in an I2S output that supports digital audio data to external audio DAC. Two L/R channel
16x16 FIFO is used to prevent sound glitches when the CPU is busy.

Ver 1.5 13 2013/11/07

 SNC7001A
16-bit Processor

14.4 MSP Interface

The MSP (Main Serial Port) is a serial communication interface for data exchanging from one
MCU to another MCU or other hardware peripherals. These peripheral devices may be serial
EEPROM, A/D converters, Display device, etc. The MSP module can operate in one of two
modes
- Full Master Mode
- Slave Mode (with general address call)

14.5 SPI Interface

The SPI (serial peripheral interface) is a synchronous serial bus that provides good support for
communication with SPI-compatible peripheral devices. The SPI peripheral is a synchronous,
7-wire interface consisting of two data pins (SPITxD and SPIRxD); two additional pins
(SPIED3 and SPIED2) for 4-bit mode access, two slave select pins (/SS1, /SS2); and a
synchronous clock pin (SCLK). The two data pins permit full-duplex and half-duplex operation
to other SPI-compatible devices. The SPI also includes programmable baud rates, clock
phase (CPHA), and clock polarity (CPOL).

Ver 1.5 14 2013/11/07

 SNC7001A
16-bit Processor

15. Multi function of I/O

P0.0 INT0
P0.1 INT INT0
P0.2 INT0
P0.3 PWMIO#0
P0.4 PWMIO#1
PWM
P0.5 PWMIO#2
P0.6 PWMIO#3
P0.7 SPISCK
PORT0
P0.8 SPIMISO
P0.9 SPIMOSI
Comm
P0.10 SPICS#1
SPI
P0.11 SPID2 WS
P0.12 SPID3 SCL
I2S
P0.13 SPICS#2 SD
P0.14 MCLK
P0.15 IR IR_Out
P1.0 CS E-Bus ECS1
P1.1 SCK (CS1/CS2) EA2
P1.2 Program MISO EA3
P1.3 SPI MOSI EA4
P1.4 ED2 EA5
P1.5 ED3 EA6
P1.6 EA7
P1.7 EA8
PORT1
P1.8 EA9
P1.9 EA10
P1.10 EA11
P1.11 ECS2
P1.12 EWR\
P1.13 ERD\
P1.14 EA0
P1.15 EA1
PORT2 P2.0 ED0
P2.1 ED1
P2.2 ED2
P2.3 ED3

Ver 1.5 15 2013/11/07

 SNC7001A
16-bit Processor

P2.4 ED4
P2.5 ED5
P2.6 ED6
P2.7 ED7
ED8
P2.8
(note1)
P2.9 ED9
P2.10 ED10
P2.11 ED11
P2.12 ED12
P2.13 ED13
P2.14 ED14
P2.15 ED15
P3.0 EA12
P3.1 EA13
P3.2 EA14
P3.3 EA15
P3.4 EA16
P3.5 EA17
P3.6 EA18
P3.7 EA19
PORT3
P3.8 EA20
P3.9 EA21
P3.10 EA22
P3.11 NAND NFCS
P3.12 R/B
P3.13 NFALE
P3.14 NFWE CIS VSYNC
P3.15 NFRE HSYNC
PORT4 P4.0 NFWP SDCLK MCLK
P4.1 NFCLE SDCMD PCLK
P4.2 LCDC LCD0 NFD0 SDD0 CISD0
SD
P4.3 LCD1 NFD1 SDD1 CISD1
P4.4 LCD2 NFD2 SDD2 CISD2
P4.5 LCD3 NFD3 SDD3 CISD3
P4.6 LCDA NFD4 CISD4
P4.7 LCDCK NFD5 CISD5
P4.8 LCDLP NFD6 CISD6

Ver 1.5 16 2013/11/07

 SNC7001A
16-bit Processor

P4.9 LCDFP NFD7 CISD7

P4.10 TxD CLK
UART MSP
P4.11 RxD DAT
AIN0
P4.12
(note2)
SAR
P4.13 AIN1
ADC
P4.14 AIN2
P4.15 AIN3
Note1: P2.8~P2.15 (GPIO) are shared pin with 8080 IF high byte (ED8~ED15)
Note2: P4.12~P4.15 (input only) are shared pin with “SAR ADC” AIN0~AIN3.

16. Regulator
The SNC7001 built-in a linear regulator for core power (CVDD) apply. The accuracy output
voltage is 1.8V±0.18V and it can be power downed by software.

17. Absolute Maximum Rating .

Items Symbol Min Max Unit

Supply Voltage VDD -0.3 6.0 V
Input Voltage VIN VSS-0.3 VDD-0.3 V
Operating Temperature TOP 0 55.0 ℃
Storage Temperature TSTG -55.0 125.0 ℃

18. Electrical Characteristics

Item Sym Min. Typ. Max. Unit Condition
. (TA=25 ℃)
Operating Voltage VDD VDD 2.7 3.3 3.6 V
Operating Voltage CVDD CVD 1.62 1.8 1.98 V
D
Standby current ISBY - 30 60 uA VDD=3.3V,No load
SAR ADC ENOB EN 9 bit
OB
SAR ADC INL INL 1 bit
SAR ADC DNL DNL 1 bit
SD-ADC SNR SNR 90 dB
SD-DAC SNR SNR 80 dB
Drive current of P0, IOD - 4 - mA VO=2.4V

Ver 1.5 17 2013/11/07

 SNC7001A
16-bit Processor
P1.6~P1.15, P2, P3,
P4.0~P4.11
Sink current of P0, P1.0, IOS - 4 - mA VO=0.4V
P1.6~P1.15, P2, P3,
P4.0~P4.11
Drive current of P1.1~P1.5 IOD 16 mA VO=2.4V (note1)
Sink Current of P1.1~P1.5 IOS 16 mA VO=0.4V (note1)
Sink Current of P4.12~P4.15 IOS - 4 - mA VO=0.4V (note2)

Note1: P1.1~P1.5 own two option for drive / sink current (16 or 12mA), the default is 16mA
Note2: P4.12~P4.15 (input only) are shared pin with “SAR ADC” AIN0~AIN3.

Ver 1.5 18 2013/11/07

 SNC7001A
16-bit Processor
19. Bonding Information

VDDDP

VDDDP
VSSDP

VSSDP
P2.13

P1.14

P0.15

P0.14
P0.13

P3.12
P3.11

P3.10
P2.12
P2.11

P2.10

P1.13

P1.12

P0.12

P0.11
P0.10

P1.11
P1.10
P1.15

VDD

VDD
P1.5

P4.8
P4.7

P1.4

P4.6
P4.5
P3.9

P3.8
P3.7

P2.9
P2.8
P2.7
VSS

VSS
117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 VSSDP
77 VDDDP
P2.14 118 76 P1.3
P2.15 119 75 P0.9
P3.13 120 74 P0.8
P3.14 121 73 P0.7
P3.15 122 72 P4.4
P4.9 123 71 P4.3
P4.10 124 70 P3.6
P4.11 125 69 P3.5
NC 68 VSS
NC 67 VDD
66 P3.4

126 65 P2.6
VSSA_DAC
64 P2.5
VSSA_DAC 127
63 P2.4
VCOM 128

129
62 P1.9
DAC_VMID
61 P1.8
VDDA_DAC 130
60 VSSDP
VDDA_DAC 131
59 VDDDP
VSSA_DRV 132
58 P1.2
VSSA_DRV 133
57 P0.6
VOUTN 134
56 P0.5
VOUTP 135
55 P0.4
VDDA_DRV 136
54 P4.2
VDDA_DRV 137
(0.00, 0.00) 53 P4.1
52 P3.3
ADC_VMID 138
51 P3.2
MICBIAS 139
50 P3.1
FMIN 140
49 P2.3
AUX 141
48 P2.2
VDDA_ADC 142
47 VSS
VDDA_ADC 143
46 VDD
MIC_N 144
45 P2.1
MIC_S 145
44 P1.7
MIC_P 146
43 P1.6
VSSA_ADC 147
42 P1.1
VSSA_ADC 148
41 VSSDP
40 VDDDP
39 P0.3
38 P0.2
VSSA_SAR 149
37 P0.1
VSSA_SAR 150
36 P4.0
AIN3 151
35 P3.0
AIN2 152
34 P2.0
AIN1 153
33 P1.0
AIN0 154

AVREFH 155

VDDA_SAR 156

VDDA_SAR 157
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
SNOIX
VDDAL_PHY
VDDAL_PHY

VDDAL_LDO

CODE_SEL
VDDA_PHY
VDDA_PHY

VSSA_PHY

XOUT_12M
VSSA_PHY

VDDA_LDO
XOUT_32K

VSSA_LDO

ICE_MOSI
ICE_MISO
ICE_SCK
ICE_CSB
PHY_DM

XIN_12M

LDO_PD
XIN_32K
PHY_DP

ICE_MS
VDDDP

VSSDP
VSSDP

CKSEL

RSTB
TEST

VDD

P0.0
VSS
VO1

SNC7001A
Note: The substrate MUST be connected to GND in PCB layout

Ver 1.5 19 2013/11/07

 SNC7001A
16-bit Processor
20. Reference Schematic

SNC7001A CHIP 1
C1
0.1uF
2 1
C2
0.1uF
2

VDD_33V

VDD_18V

VDD_33V

VDD_18V

VDD_33V
DGND

DGND

DGND

DGND

DGND
P2_13
P1_15

P1_14
P0_15

P0_14
P0_13

P3_12
P3_11
P3_10
P2_12
P2_11
P2_10

P1_13
P1_12

P0_12
P0_11
P0_10

P1_11
P1_10
P1_5

P4_8
P4_7

P1_4

P4_6
P4_5
P3_9
P3_8
P3_7
P2_9
P2_8
P2_7
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
P2.13
P1.15

P1.5
P1.14
P0.15

P0.14
P0.13
P4.8
P4.7
P3.12
P3.11
P3.10
P2.12
P2.11
P2.10

P1.4
P1.13
P1.12

P0.12
P0.11
P0.10
P4.6
P4.5
P3.9
P3.8
P3.7
P2.9
P2.8
P2.7
P1.11
P1.10
VSSDP
VDDDP

VSS

VSSDP
VDDDP

VSS

VSSDP
VDDDP
NC

VDD

VDD

NC
NC
133 88 P1_3
134 NC P1.3 87 P0_9
135 NC P0.9 86 P0_8
136 NC P0.8 85 P0_7
137 NC P0.7 84 P4_4
P2_14 138 NC P4.4 83 P4_3
P2_15 139 P2.14 P4.3 82 P3_6
P3_13 140 P2.15 P3.6 81 P3_5
P3_14 141 P3.13 P3.5 80 DGND
P3_15 142 P3.14 VSS 79 VDD_18V
P4_9 143 P3.15 VDD 78 P3_4
P4_10 144 P4.9 P3.4 77 P2_6
P4_11 145 P4.10 P2.6 76 P2_5
VSSA 146 P4.11 P2.5 75 P2_4
VCOM 147 VSSA_DAC P2.4 74 P1_9
1

C10 DAC_VMID 148 VCOM P1.9 73 P1_8

1

C11 C12 VDDA 149 DAC_VMID P1.8 72 DGND

1uF VSSA 150 VDDA_DAC VSSDP 71 VDD_33V
2

1uF 1uF C13 VOUTN 151 VSSA_DRV VDDDP 70 P1_2

2

VOUTP 152 VOUTN P1.2 69 P0_6

1uF VDDA 153 VOUTP P0.6 68 P0_5
SNC7001A
2

ADC_VMID 154 VDDA_DRV P0.5 67 P0_4

MICBIAS 155 ADC_VMID P0.4 66 P4_2
156 MICBIAS LQFP-176 P4.2 65 P4_1
157 FMIN P4.1 64 P3_3
VDDA 158 AUX & COB-176 P3.3 63 P3_2
1

C15 C16 C17 MIC_N 159 VDDA_ADC P3.2 62 P3_1

160 MIC_N P3.1 61 P2_3
1uF 1uF 1uF MIC_P 161 MIC_S P2.3 60 P2_2
2

1
VSSA 162 MIC_P P2.2 59 DGND C18
VSSA 163 VSSA_ADC VSS 58 VDD_18V
AIN3 164 VSSA_SAR VDD 57 P2_1 0.1uF

2
AIN2 165 AIN3 P2.1 56 P1_7
AIN1 166 AIN2 P1.7 55 P1_6
AIN0 167 AIN1 P1.6 54 P1_1

1
168 AIN0 P1.1 53 DGND C19
VDDA 169 AVREFH VSSDP 52 VDD_33V
170 VDDA_SAR VDDDP 51 P0_3 0.1uF

2
171 NC P0.3 50 P0_2
172 NC P0.2 49 P0_1
173 NC P0.1 48 P4_0
174 NC P4.0 47 P3_0
175 NC P3.0 46 P2_0
176 NC P2.0 45 P1_0
NC P1.0

RESET
VDDAL_LDO
VDDAL_PHY
VDDA_PHY

VDDA_LDO

CODE_SEL
XOUT_12M

VSSA_LDO
VSSA_PHY

XOUT_32K

ICE_MISO
ICE_MOSI
ICE_CSB
ICE_SCK
PHY_DM

XIN_12M
PHY_DP

XIN_32K

LDO_PD

ICE_MS
VDDDP
VSSDP

VSSDP

CKSEL

RSTB
TEST

VDD

P0.0
VO1

VSS
NC
NC
NC
NC
NC
NC
NC

NC
NC
NC
NC
NC
NC
NC
NC
VDD_33V

SNC7001A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
R11 U1
VDDAL_LDO
XOUT_12M

ICE_MISO
ICE_MOSI
VDD_18V

VDD_33V

VDD_33V

VDD_18V

VDD_33V

ICE_CSB
ICE_SCK
XIN_12M
PHY_D+

10K
ICE_MS
PHY_D-

RESET
DGND

DGND

DGND

DGND

DGND
VDDA
VSSA

P0_0

RESET

XTAL
1

1 2 C21

C20 0.1uF
2
1

XOUT_12M
C22 S1 0.1uF Default is floating

XIN_12M
VDDAL_LDO VDD_18V
0.1uF RESET
CLK_SEL
2

C23 C24 Y1 12M

0.1uF 47uF/BC
0 1
2

12M_IHRC 12M_Xtal
1

1
DGND

C25 C26

20pF 20pF
2

POWER
SAR_ADC
ICE_5V BAT_4.5V
U5 FT510Ga_SOT23 R16 0 VDD_33V For SNC7002 IC Digital 3.3V BAT_4.5V
3 2
VI VO
GND

R17
JP2 330 R18
R
1

2 C33 C34
1 D1 R19 0 VDDA For Analog ADC/DAC/PHY/SAR IP 3.3V
10uF/BC 0.1uF AIN2
2

HEADER 2 For Analog DAC DRV 3.3V

BATTARY_4V5 R22 0 VSSA R20
2

DGND R

AIN3
R26 0 +3.3V_Peri_10mil For Peripheral 3.3V
Battery Detect

CIS MCU8080
+3.3V_Peri_10mil
+3.3V_Peri_10mil P3_11
CIS_AVDD R29 0 CIS_VDD R30 0 P3_12
1

C35 C36 C37 C38 C39

CIS_AGND 10uF R31 0 DGND 10uF 0.1uF

P3_13 10uF 0.1uF
2

P3_14 CIS_VSYNC
P3_15 CIS_HSYNC
GND LED_K 1
J6 P4_0 CIS_MCLK +3.3V_Peri_10mil R32 0 LED_A 2
P1_11 ECS2#
P4_8 1 2 P4_9 GND GND 3
P4_6 3 P4_8 P4_9 4 P4_7 Pin21:
P4_1 CIS_PCLK +3.3V_Peri_10mil IO VCC 4
P1_12 WR#
P4_4 5 P4_6 P4_7 6 P4_5 5
DGND 7 P4_4 P4_5 8 CIS_VDD CIS_PD# J8
P4_2 CIS_D0 6
P1_13 RD#
P4_2 9 GND VDD 10 P4_3 P1_11 /CS 7
P3_12 11 P4_2 P4_3 12 P3_11 +3.3V_Peri_10mil 1
P4_3 CIS_D1 RESET R33 0 /RESET 8 J7
P1_14 EA0
P3_14 13 P3_12 P3_11 14 P4_1 Pin21 2 P1_14 RS 9
P4_0 15 P3_14 P4_1 16 P3_15
P4_4 CIS_D2 P1_12 /WR 10
P2_0 ~ ED0 ~
P4_11 17 P4_0 P3_15 18 P4_10 P1_13 /RD 11
CIS_AVDD 19 P4_11 P4_10 20 CIS_AGND HEADER 2
P4_5 CIS_D3 P2_7 DB7 12
P2_7 ED7
Pin21 21 AVDD AGND 22 CIS_AVDD P2_6 DB6 13
P3_13 23 PD/RB2 AVDD 24 Pin24 Pin24:
P4_6 CIS_D4 P2_5 DB5 14
P3_13 RST/RB3 P2_4 DB4 15
CIS_RST# TP1
P4_7 CIS_D5 P2_3 DB3 16
HEADER 12X2 CIS Pin24 1 P2_2 DB2 17
P4_8 CIS_D6 P2_1 DB1 18
P2_0 DB0 19
P4_9 CIS_D7 GND GND 20
+3.3V_Peri_10mil
P4_10 I2C_SCLK
R34 4.7K P4_10
R35 4.7K P4_11 I2C P4_11 I2C_SDA TG144C31

Ver 1.5 20 2013/11/07

 SNC7001A
16-bit Processor

MIC & LINE_IN CKT

DAC Headphone & SNAP01A CKT BAT_4.5V

1
C3
J1 C4 MICBIAS
1 VCOM 0.47uF R1 10uF

2
3 VOUTN 1 2 R2
2.2K
4 20K U2 VSSA J2 C5
2 VOUTP MIC_P 1 2
1 8 O- 1
PJK-684 2 VM O- 7 BAT_4.5V 2 1uF
VIN VDD

1
3 6 O+ C6 R3
4 GND O+ 5 JP1
+
C7 VREF CE HEADER 2 MIC 220PF 47K

2
0.47uF R4 SNAP01A
-

2
1 2 P1_6 C9

1
C8 MIC_N 1 2
20K
1uF R5 1uF R6

2
2.2K
10K
SNAP01 ON : P1_6 = 1
SNAP01 OFF : P1_6 = 0 VSSA
VSSA VSSA

CS1 SPI P1_0 1

U3
8 +3.3V_Peri_10mil ICE Interface
+3.3V_Peri_10mil P1_2 2 CS# VDD 7 P1_5
P1_4 3 SIO1 SIO3 6 P1_1
DGND 4 SIO2 SCLK 5 P1_3
GND SIO0
1

C14
MX25L6445 HEADER 5X2
0.1uF
2

10 9
ICE_CSB 8 7 ICE_MOSI
ICE_SCK 6 5 ICE_MISO
ICE_5V ICE_MS 4 3 RESET
ICE_5V 2 1 DGND
P1_0 SPICS
P1_1 SPISCK J3
Standalone CODE_SEL
P1_2 SPIMISO
0
ICE_CSB

P1_3 SPIMOSI
0 CS1_SPI P1_4 SPIED2 (WP#) USB
P1_5 SPIED3 (HOLD#)
Detected USB Plug in: P0_8=1
VDD_33V USB_5V
Detected USB Not Plug in :P0_8=0
R7
N/C USB_5V
R8
ICE_CSB Default is floating 150K R9 J4
300K
1
R10 PHY_D- 2
1M P0_8 PHY_D+ 3
4 7
R13 5 8
R12 300K 6 9
300K
MINI-B

SD CARD
+3.3V_Peri_10mil X-ROM IF
12 11
10 +3.3V_Peri_10mil +3.3V +3.3V
8 U4
7
6 C27 C28 1 48
R14 R15 10uF 0.1uF 2 NC NC 47
5 10K 10K 3 NC NC 46
4 4 NC NC 45
5 NC NC 44 P4_9
3 NC I/O7
2 SD_CD P1_13 6 43 P4_8
SD_WP P1_14 FM_RB 7 NC I/O6 42 P4_7
1 FM_RE 8 RB# I/O5 41 P4_6
9 FM_CE 9 RE# I/O4 40
10 CE# NC 39
11 NC NC 38 C31
C29 C30 12 NC NC 37
10uF 0.1uF 13 VDD VDD 36 0.1uF
14 VSS VSS 35
J5 SD Card Power Down : P0_13= 0 15 NC NC 34
SD_D2 P4_4 +3.3V_Peri_10mil FM_CLE NC NC
15
14 15 DAT2
9
1 SD_D3 P4_5 SD Card Normal : P0_13 = 1 FM_ALE
16
17 CLE NC
33
32 P4_5
13 14CD/DAT3 2 SD_CMD P4_1 18 ALE I/O3 31 P4_4
13 CMD 3 19 WE# I/O2 30 P4_3
VSS 4 20 NC I/O1 29 P4_2
VDD 5 SD_CLK P4_0 Detected SD Card Plug in: P1_13= 0 21 NC I/O0 28
CLK NC NC
VSS
6
7 SD_D0 P4_2 C32
Detected SD Card Not Plug in : P1_13= 1 22
23 NC NC
27
26
DAT0 NC NC
DetLock

8 SD_D1 P4_3 0.1uF 24 25

DAT1 10 SD_CD NC NC
DetCard 11 MX23J51243 (MX23J1G43)
DetC Detected SD Card Write Protect: P1_14= 0
SD_WP
SD slot
Detected SD Card Not Write Protect :P1_14= 1
12

R23 FM_RB P3_12 +3.3V

R21 1K
P0_13 Q1
8050
P3_11 R24 330 FM_CE
300
P3_13 R25 330 FM_ALE

P3_15 R27 330 FM_RE

P4_1 R28 330 FM_CLE

Ver 1.5 21 2013/11/07

 SNC7001A
16-bit Processor
DISCLAIMER

The information appearing in SONiX web pages (“this publication”) is believed to be

accurate.
However, this publication could contain technical inaccuracies or typographical errors.
The reader should not assume that this publication is error-free or that it will be
suitable for any particular purpose. SONiX makes no warranty, express, statutory
implied or by description in this publication or other documents which are referenced
by or linked to this publication. In no event shall SONiX be liable for any special,
incidental, indirect or consequential damages of any kind, or any damages
whatsoever, including, without limitation, those resulting from loss of use, data or
profits, whether or not advised of the possibility of damage, and on any theory of
liability, arising out of or in connection with the use or performance of this publication
or other documents which are referenced by or linked to this publication.
This publication was developed for products offered in Taiwan. SONiX may not offer
the products discussed in this document in other countries. Information is subject to
change without notice. Please contact SONiX or its local representative for
information on offerings available. Integrated circuits sold by SONiX are covered by
the warranty and patent indemnification provisions stipulated in the terms of sale only.
The application circuits illustrated in this document are for reference purposes only.
SONIX DISCLAIMS ALL WARRANTIES, INCLUDING THE WARRANTY OF
MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. SONIX reserves the right
to halt production or alter the specifications and prices, and discontinue marketing the
Products listed at any time without notice. Accordingly, the reader is cautioned to
verify that the data sheets and other information in this publication are current before
placing orders.
Products described herein are intended for use in normal commercial applications.
Applications involving unusual environmental or reliability requirements, e.g. military
equipment or medical life support equipment, are specifically not recommended
without additional processing by SONIX for such application.

Ver 1.5 22 2013/11/07