THAT Analog Engi ne ®

IC Dynamics Processor

THAT4301

FEATURES APPLICATIONS
• High-Performance Blackmer® • Compressors
Voltage Controlled Amplifier
• Limiters
• High-Performance RMS-Level
• Gates
Detector
• Expanders
• Three General-Purpose Opamps
• De-Essers
• Wide Dynamic Range: >115 dB
• Duckers
• Low THD: <0.03%
• Noise Reduction Systems
• Low Cost
• Wide-Range Level Meters
• DIP & Surface-Mount Packages

Description
THAT 4301 Dynamics Processor, dubbed converter for the VCA, while the other two may
“THAT Analog Engine,” combines in a single IC be used for the signal path or control voltage pro-
all the active circuitry needed to construct a wide cessing.
range of dynamics processors. The 4301 in-
The combination of exponential VCA gain
cludes a high-performance, exponentially-con-
control and logarithmic detector response —
trolled VCA, a log-responding RMS-level sensor “decibel-linear” response — simplifies the math-
and three general- purpose opamps. ematics of designing the control paths of dynam-
The VCA provides two opposing-polarity, ics processors. This makes it easy to design
voltage-sensitive control ports. Dynamic range audio compressors, limiters, gates, expanders,
exceeds 115 dB, and THD is typically 0.003% at de-essers, duckers, noise reduction systems and
0 dB gain. The RMS detector provides accurate the like. The high level of integration ensures ex-
rms-to-dc conversion over an 80 dB dynamic cellent temperature tracking between the VCA
range for signals with crest factors up to 10. One and the detector, while minimizing the external
opamp is dedicated as a current-to-voltage parts count.

18 11 17 14 13 12

20 pin 20 pin
VCC
19
- SYM - Model DIP SO
OA1 IN OUT OA3
Package Package
VCA
20 + +
EC- EC+
15

T H AT 4 3 0 1
16
+
1 IN RMS OUT OA2
IT CT - 4301 4301P20-U 4301W20-U
GND VEE

2 5 4 9 10 8 6 7

Figure 1. Block Diagram Table 1. Ordering Information

THAT Corporation; 45 Sumner Street; Milford, Massachusetts 01757-1656; USA

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Copyright © 2017, THAT Corporation; Doc 600069 Rev 10
THAT4301 Analog Engine® Page 2 of 12 Document 600069 Rev 10
IC Dynamics Processor

SPECIFICATIONS 1 , 2
Absolute Maximum Ratings (T A =25°C) 3
Positive Supply Voltage (VCC) +18 V Power Dissipation (PD) (TA = 75°C) 700 mW
Negative Supply Voltage (VEE) -18 V Operating Temperature Range (TOP) 0 to +70 ºC
Supply Current (ICC) 20 mA Storage Temperature Range (TST) -40 to +125 ºC

Overall Electri cal Characteristi cs

Parameter Symbol Conditions Min Typ Max Units

Positive Supply Voltage VCC +7 — +15 V

Negative Supply Voltage VEE -7 — -15 V

Positive Supply Current ICC — 12 18 mA

Negative Supply Current IEE — -12 -18 mA

VCA Electrical Characteristi cs 4

Parameter Symbol Conditions Min Typ Max Units

Input Bias Current IB(VCA) No Signal — 30 400 pA

Input Offset Voltage VOFF(VCA In) No Signal — ±4 ±15 mV

Input Signal Current IIN(VCA) or IOUT(VCA) — 175 750 µArms

Gain at 0V Control G0 EC+ = EC– = 0.000V -0.4 0.0 +0.4 dB

Gain-Control Constant TA = 25°C (TCHIP @ 55°C)

-60 dB < gain < +40dB
EC+/Gain (dB) EC+ & SYM 6.4 6.5 6.6 mV/dB
EC-/Gain (dB) EC- -6.4 -6.5 -6.6 mV/dB

Gain-Control TempCo ΔEC / ΔTCHIP Ref TCHIP = 27°C — +0.33 — %/°C

Gain-Control Linearity -60 to +40 dB gain — 0.5 2 %

Off Isolation EC+=SYM=-375mV, EC-=+375mV 110 115 — dB

Output Offset Voltage Change ΔVOFF(OUT) Rout = 20kΩ

0 dB gain — 1 3 mV
+15 dB gain — 2 10 mV
+30 dB gain — 5 25 mV

Gain Cell Idling Current IIDLE — 20 — µA

Output Noise en(OUT) 20 Hz - 20 kHz

Rout = 20kΩ
0 dB gain — -96 -94 dBV
+15 dB gain — -85 -83 dBV

Total Harmonic Distortion THD VIN = 0 dBV, 1 kHz

0 dB gain — 0.003 0.007 %

1. All specifications are subject to change without notice.

2. Unless otherwise noted, TA=25ºC, VCC=+15V, VEE=-15V; VCASYM adjusted for min THD @ 1V, 1 kHz, 0 dB gain.
3. If the device is subjected to stress above the Absolute Maximum Ratings, permanent damage may result. Sustained operation at or near the
Absolute Maximum Ratings conditions is not recommended. In particular, like all semiconductor devices, device reliability declines as operating
temperature increases.
4. Test circuit is the VCA section only from Figure 2.
5. Except as noted, test circuit is the RMS-Detector section only from Figure 2.

THAT Corporation; 45 Sumner Street; Milford, Massachusetts 01757-1656; USA

Tel: +1 508 478-9200; Fax +1 508 478-0990; Email: info@thatcorp.com; Web: www.thatcorp.com
Copyright © 2017, THAT Corporation; All rights reserved.
THAT4301 Analog Engine® Page 3 of 12 Document 600069 Rev 10
IC Dynamics Processor

SPECIFICATIONS 1 , 2 (Cont’d.)
VCA Electrical Characteristi cs 4 (Cont’d)
Parameter Symbol Conditions Min Typ Max Units

Total Harmonic Distortion (cont’d.) THD VIN = +10 dBV, 1 kHz

0 dB gain — 0.03 0.07 %
–15 dB gain — 0.035 0.09 %
VOUT = +10 dBV, 1 kHz
+15 dB gain — 0.035 0.09 %

Symmetry Control Voltage VSYM minimum THD -2.5 0 +2.5 mV

RMS Detector Electrical Characteristics 5

Parameter Symbol Conditions Min Typ Max Units

Input Bias Current IB (RMS) No Signal — 30 400 pA

Input Offset Voltage VOFF(RMS In) No Signal — ±4 ±15 mV

Input Signal Current IIN(RMS) — 175 750 µA

Input Current for 0 V Output Iin0 IT= 7.5 µA 6 8.5 12 µA

Output Scale Factor EO / 20log(Iin/Iin0) 31.6nA< IIN< 1mA

TA= 25°C (TCHIP  55°C) 6.4 6.5 6.6 mV/dB

Scale Factor Match (RMS to VCA) -20 dB < VCA Gain < +20 dB
1µA < Iin (DET)<100µA .985 1 1.015

Output Linearity fIN = 1kHz

1µA < Iin< 100µA — 0.1 — dB
100nA < Iin< 316µA — 0.5 — dB
31.6nA < Iin< 1mA — 1.5 — dB

Rectifier Balance fIN = 100 Hz,  = .001 s

1µA< Iin < 100µA –20 — 20 %

Crest Factor 1ms pulse repetition rate

0.2 dB error — 3.5 —
0.5 dB error — 5 —
1.0 dB error — 10 —

Maximum Frequency for 2 dB Additional Error Iin ≥ 10mA — 100 — kHz

Iin ≥ 3mA — 45 — kHz
Iin ≥ 300nA — 7 — kHz

Timing Current Set Range IT 1.5 7.5 15 µA

Voltage at IT Pin IT = 7.5 µA -10 +20 +50 mV

Timing Current Accuracy ICT/IT IT = 7.5 µA 0.90 1.1 1.30

Filtering Time Constant  TCHIP = 55°C (0.026)𝐶𝐼 𝑇 s

𝑇

Output Temp. Coefficient ΔEo / ΔTCHIP Re: TCHIP = 27°C — 0.33 — %/°C

Output Current IOUT –300mV < VOUT< +300mV ±90 ±100 — µA

THAT Corporation; 45 Sumner Street; Milford, Massachusetts 01757-1656; USA

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THAT4301 Analog Engine® Page 4 of 12 Document 600069 Rev 10
IC Dynamics Processor

SPECIFICATIONS 1 , 2 (Cont’d.)
Opamp Electrical Characteristi cs 6
OA1 OA2 OA3
Parameter Symbol Conditions Min Typ Max Min Typ Max Min Typ Max Units

Input Offset Voltage VOS — ±0.5 ±6 — ±0.5 ±6 — ±0.5 ±6 mV

Input Bias Current IB — 150 500 — 150 500 — 150 500 nA

Input Offset Current IOS — 15 50 — 15 50 N/A nA

Input Voltage Range IVR — ±13.5 — — ±13.5 — N/A V

Common Mode Rej. Ratio CMRR RS<10k — 100 — — 100 — N/A

Power Supply Rej. Ratio PSRR VS=±7V to ±15V — 100 — — 100 — — 100 —

Gain Bandwidth Product GBW (@50kHz) — 5 — — 5 — — 5 — MHz

Open Loop Gain AVO RL=10k — 115 — — 110 — — 125 —

RL=2k N/A N/A — 120 —

Output Voltage Swing VO@RL=5kΩ — ±13 — — ±13 — — ±14 — V

VO@RL=2kΩ N/A N/A — ±13 — V

Short Circuit Output Current — 4 — — 4 — — 12 — mA

Slew Rate SR — 2 — — 2 — — 2 — V/µs

Total Harmonic Distortion THD 1kHz, AV=1, RL=10kΩ — 0.0007 0.003 — 0.0007 0.003 — 0.0007 0.003 %
1kHz, AV=–1, RL= 2kΩ N/A N/A — 0.0007 0.003 %

Input Noise Voltage Density en fO=1kHz — 6.5 10 — 7.5 12 — 7.5 12

Input Noise Current Density in fO=1kHz — 0.3 — — 0.3 — — 0.3 —

6. Test circuit for opamps is a unity-gain follower configuration with loaded resistor RL as specified.

+15V
R5

50K VCA SYM

S IG N A L -1 5 V
C2
IN 47pF
C1
R1 R4
300K
20K0 1% R3 R2
47uF

51 20K0 1%

+15V
S IG N A L
C7 OUT
SYM
- -
OA1 IN VCA OUT OA3
100n + EC- EC+ +

C8 VCC T H AT 4 3 0 1
C3
VEE

100n +
47uF
-1 5 V IN RMS OUT OA2
R6 It Ct -
GND
10K0 1%

R7
C6 C4 RMS
2M 00
OUT
1%
22uF 10uF
E c-

-1 5 V

Figure 2. VCA and RMS detector test circuit

THAT Corporation; 45 Sumner Street; Milford, Massachusetts 01757-1656; USA

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THAT4301 Analog Engine® Page 5 of 12 Document 600069 Rev 10
IC Dynamics Processor

REPRESENTATIVE DATA
dB GAIN %THD+N
10

20

0
1

-20

0.1
-40

-60
0.01

-80

V in
-100 mV
0.001 rms
-200 0 200 400 600 0.5 1.0 10

Figure 3. VCA Gain vs. Control Voltage (Ec-) at 25°C Figure 4. VCA 1kHz THD+Noise vs. Input, -15 dB Gain

%THD+N %THD+N
10 10

1 1

0.1 0.1

0.01 0.01

V in V in
0.001 rms 0.001 rms
0.1 1 2 0.5 1.0 10

Figure 5. VCA 1kHz THD+Noise vs. Input, +15 dB Gain Figure 6. VCA 1kHz THD+Noise vs. Input, 0 dB Gain

%THD+N mV Out
1

300

Note: 0 dBr = 85 m V rms

200

0.1 100

-100
0.01

-200
1kHz

-300
10kHz
dBr
0.001 Hz -400 In
20 100 1k 10k 20k -60 -40 -20 0 20 40

Figure 7. VCA THD vs. Frequency, 0 dB Gain, 1Vrms Input Figure 8. RMS Output vs. Input Level, 1 kHz & 10 kHz

mV Error mV Out
30 300
+40 dBr

Note: 0 dBr = 85 m V rms +30 dBr

200
20
+20 dBr

100
+10 dBr
10
0 dBr
0

-10 dBr
0
-100 -20 dBr

-10 -30 dBr

-200
-40 dBr
dBr
-20 In -300 Hz
-60 -40 -20 0 20 40 20 100 1k 10k 100k

Figure 9. Departure from Ideal Detector Law vs. Level Figure 10. Detector Output vs. Frequency at Various Levels

THAT Corporation; 45 Sumner Street; Milford, Massachusetts 01757-1656; USA

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Copyright © 2017, THAT Corporation; All rights reserved.
THAT4301 Analog Engine® Page 6 of 12 Document 600069 Rev 10
IC Dynamics Processor

Theory of Operation
THAT 4301 Dynamics Processor combines THAT associated with OA1, OA2 and the RMS detector has
Corporation’s proven Voltage-Controlled Amplifier been omitted.
(VCA) and RMS-Level Detector designs with three gen-
eral-purpose opamps to produce an Analog Engine
useful in a variety of dynamics processor applications. R5

For details of the theory of operation of the VCA and P o s itiv e C o n tr o l In 50K VCA SYM

RMS-Detector building blocks, the interested reader is C1

C2 47pF

referred to THAT Corporation’s data sheets on the

R1
S ig n a l In R4
300K
2180 Series VCAs and the 2252 RMS-Level Detector. 47uF
20K0 1%
R3 R2

Theory of the interconnection of exponentially-con- 51 20K0 1%

trolled VCAs and log-responding level detectors is cov- - SYM

-
S ig n a l
O ut

ered in THAT Corporation’s design note DN01A OA1 IN VCA OUT OA3

(formerly AN101), The Mathematics of Log-Based Dy-

+ EC- EC+ +

namic Processors. VCC T H AT 4 3 0 1

VEE

The VCA — in Brief IN RMS OUT

+
OA2
It Ct -

THAT 4301 VCA is based on THAT Corporation’s GND

highly successful complementary log-antilog gain cell

topology, as used in THAT 2180-Series IC VCAs.
THAT 4301 is integrated using a fully complementary,
BiFET process. The combination of FETs with high- Figure 11. Driving the VCA via the Positive Control Port
quality, complementary bipolar transistors (NPNs and
PNPs) allows additional flexibility in the design of the While the 4301’s VCA circuitry is very similar to
VCA over previous efforts. that of the THAT 2180 Series VCAs, there are several
important differences, as follows:
Input signals are currents to the VCA IN pin. This
pin is a virtual ground, so in normal operation an in- 1) Supply current for the VCA is fixed internally.
put voltage is converted to input current via an appro- Approximately 2 mA is available for the sum of input
priately sized resistor (R1 in Figure 2, Page 4). Because and output signal currents. (This is also the case in a
dc offsets present at the input pin and any dc offset in 2180 Series VCA when biased as recommended.)
preceeding stages will be modulated by gain changes 2) The signal current output of the VCA is inter-
(thereby becoming audible as thumps), the input pin nally connected to the inverting input of an on-chip
is normally ac-coupled (C1 in Figure 2). opamp. In order to provide external feedback around
The VCA output signal is also a current, inverted this opamp, this node is brought out to a pin.
with respect to the input current. In normal operation, 3) The control-voltage constant is approximately
the output current is converted to a voltage via inverter 6.5 mV/dB, due primarily to the higher internal oper-
OA3, where the ratio of the conversion is determined ating temperature of the 4301 compared to that of the
by the feedback resistor (R2, Figure 2) connected be- 2180 Series.
tween OA3‘s output and its inverting input. The signal
path through the VCA and OA3 is noninverting. 4) The input stage of the 4301 VCA uses integrated
P-channel FETs rather than a bias-current corrected
The gain of the VCA is controlled by the voltage ap- bipolar differential amplifier. Input bias currents have
plied to EC–, EC+, and SYM. Gain (in decibels) is pro- therefore been reduced.
portional to EC+ – EC-, provided EC+ and SYM are at
essentially the same voltage (see below). The constant The RMS Detector — in Brief
of proportionality is –6.5 mV/dB for the voltage at EC–, The 4301’s detector computes rms level by rectify-
and 6.5 mV/dB for the voltage at EC+ and SYM. ing input current signals, converting the rectified cur-
As mentioned, for proper operation, the same volt- rent to a logarithmic voltage, and applying that voltage
age must be applied to EC+ and SYM, except for a small to a log-domain filter. The output signal is a dc voltage
(±2.5 mV) dc bias applied between these pins. This proportional to the decibel-level of the rms value of the
bias voltage adjusts for internal mismatches in the input signal current. Some ac component (at twice the
VCA gain cell which would otherwise cause small dif- input frequency) remains superimposed on the dc out-
ferences between the gain of positive and negative half- put. The ac signal is attenuated by a log-domain filter,
cycles of the signal. The voltage is usually applied via which constitutes a single-pole rolloff with cutoff de-
an external trim potentiometer (R5 in Figure 2), which termined by an external capacitor and a programma-
is adjusted for minimum signal distortion at unity (0 ble dc current.
dB) gain. As in the VCA, input signals are currents to the
The VCA may be controlled via EC-, as shown in RMS IN pin. This input is a virtual ground, so a resis-
Figure 2, or via the combination of EC+ and SYM. This tor (R6 in Figure 2) is normally used to convert input
connection is illustrated in Figure 11. Note that this voltages to the desired current. The level detector is
figure shows only that portion of the circuitry needed capable of accurately resolving signals well below
to drive the positive VCA control port; circuitry 10 mV (with a 10 k input resistor). However, if the

THAT Corporation; 45 Sumner Street; Milford, Massachusetts 01757-1656; USA

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Copyright © 2017, THAT Corporation; All rights reserved.
THAT4301 Analog Engine® Page 7 of 12 Document 600069 Rev 10
IC Dynamics Processor

detector is to accurately track such low-level signals, 1.1 IT. Normally, a resistor is not connected directly to
ac coupling is normally required. the CT pin on the 4301.
The log-domain filter cutoff frequency is usually 3) The 0 dB reference point, or level match, is not
placed well below the frequency range of interest. For adjustable via an external current source. However, as
an audio-band detector, a typical value would be 5 Hz, in the 2252, the level match is affected by the timing
or a 32 ms time constant (). The filter’s time constant current, which, in this case, is drawn from the IT pin
is determined by an external capacitor attached to the and mirrored internally to CT.
CT pin, and an internal current source (ICT) connected
to CT. The current source is programmed via the IT 4) The input stage of the 4301 RMS detector uses
pin: current in IT is mirrored to ICT with a gain of ap- integrated P-channel FETs rather than a bias-current
proximately 1.1. The resulting time constant  is ap- corrected bipolar differential amplifier. Input bias cur-
proximately equal to 0.026 CT/IT. Note that, as a result rents are therefore negligible, improving performance
of the mathematics of RMS detection, the attack and at low signal levels.
release time constants are fixed in their relationship The Opamps — in Brief
to each other.
The three opamps in the 4301 are intended for
The dc output of the detector is scaled with the general purpose applications. All are 5 MHz opamps
same constant of proportionality as the VCA gain con- with slew rates of approximately 2 V/s. All use bipo-
trol: 6.5 mV/dB. The detector’s 0 dB reference (Iin0, lar PNP input stages. However, the design of each is
the input current which causes 0 V output), is deter- optimized for its expected use. Therefore, to get the
mined by IT as follows: most out of the 4301, it is useful to know the major
differences among these opamps.
𝐼𝑖𝑛0 = √9.6𝜇𝐴 𝐼𝑇
OA3, being internally connected to the output of the
The detector output stage is capable of sinking or VCA, is intended for current-to-voltage conversion. Its
sourcing 100 A. input noise performance, at 7.5𝑛𝑉/√𝐻𝑧, complements
Differences between the 4301’s RMS-Level Detec- that of the VCA, adding negligible noise at unity gain.
tor circuitry and that of the THAT 2252 RMS Detector Its output section is capable of driving a 2 k load to
are as follows: within 2 V of the power supply rails, making it possi-
ble to use this opamp directly as the output stage in
1) The rectifier in the 4301 RMS Detector is inter- single-ended designs.
nally balanced by design, and cannot be balanced via
an external control. The 4301 will typically balance OA1 is the quietest opamp of the three. Its input
positive and negative halves of the input signal within noise voltage, at 6.5 𝑛𝑉/√𝐻𝑧, makes it the opamp of
±1.5 %, but in extreme cases the mismatch may reach choice for input stages. Note that its output drive ca-
±15 %. However, a 15 % mismatch will not signifi- pability is limited (in order to reduce the chip’s power
cantly increase ripple-induced distortion in dynamics dissipation) to approximately ±3 mA. It is comfortable
processors over that caused by signal ripple alone. driving loads of 5 k or more to within 1 V of the
power supply rails.
2) The time constant of the 4301’s RMS detector is
determined by the combination of an external capaci- OA2 is intended primarily as a control-voltage pro-
tor (connected to the CT pin) and an internal, program- cessor. Its input noise parallels that of OA3, and its
mable current source. The current source is equal to output drive capability parallels that of OA1.

THAT Corporation; 45 Sumner Street; Milford, Massachusetts 01757-1656; USA

Tel: +1 508 478-9200; Fax +1 508 478-0990; Email: info@thatcorp.com; Web: www.thatcorp.com
Copyright © 2017, THAT Corporation; All rights reserved.
THAT4301 Analog Engine® Page 8 of 12 Document 600069 Rev 10
IC Dynamics Processor

Applications
The circuit of Figure 12 shows a typical application output as “thumps”. Note that C1, in conjunction with
for THAT 4301. This simple compressor/ limiter de- R1, will set the low frequency limit of the circuit.
sign features adjustable hard-knee threshold, com- The VCA output is connected to OA3, configured as
pression ratio, and static gain1. The applications an inverting current-to-voltage converter. OA3‘s feedback
discussion in this data sheet will center on this circuit components (R2, 20 k, and C2, 47 pf) determine the
for the purpose of illustrating important design issues. constant of current-to-voltage conversion. The simplest
However, it is possible to configure many other types way to deal with this is to recognize that when the VCA is
of dynamics processors with THAT 4301. Hopefully, set for unity (0 dB) gain, the input to output voltage gain
the following discussion will imply some of these pos- is simply R2/R1, just as in the case of a single inverting
sibilities. stage. If, for some reason, more than 0 dB gain is re-
quired when the VCA is set to unity, then the resistors
may be skewed to provide it. Note that the feedback ca-
Signal Path pacitor (C2) is required for stability. The VCA output has
As mentioned in the section on theory, the VCA in- approximately 45 pf of capacitance to ground, which
put pin is a virtual ground with negative feedback pro- must be neutralized via the 47 pf feedback capacitor
vided internally. An input resistor (R1, 20k) is across R2.
required to convert the ac input voltage to a current The VCA gain is controlled via the EC– terminal,
within the linear range of the 4301. (Peak VCA input whereby gain will be proportional to the negative of the
currents should be kept under 1 mA for best distor- voltage at EC–. The EC+ terminal is grounded, and the
tion performance.) The coupling capacitor (C1, 47 f) SYM terminal is returned nearly to ground via a small
is strongly recommended to block dc current from resistor (R3, 51 ). The VCA SYM trim (R5, 50 k) al-
preceding stages (and from offset voltage at the input lows a small voltage to be applied to the SYM terminal
of the VCA). Any dc current into the VCA will be mod- via R4 (300 k). This voltage adjusts for small mis-
ulated by varying gain in the VCA, showing up in the matches within the VCA gain cell, thereby reducing

VCA SYM
C1
R1 R5 +15
50K
47uF 20K0 1%

+15
R9 -1 5
TH RESH O LD
10K0 1% R4
CCW
R 11 CR2 300K C2 47pF
C9 22p
R 12 R3
383K 1%
10K
R 10 51 R2
CR1
CW
2M 00 1% 20K0 1%

-1 5 R8
OUT
- SYM -
4k99 1% IN
IN
OA1 VC A OUT OA3
+15 + EC- EC+ +
C7 100n
VCC T H AT 4 3 0 1
C8 100n
VEE
+
C3 IN RM S OUT OA2
-1 5 R6
IT CT -
GND
47uF 10K0 1%
R 16

R7 4k99 1%
C6 2M 00 C4 C5 +15
1% 10uF
R 14 22uF G A IN
1K43 100N CW
C O M P R E S S IO N CW 1% -1 5
R 17 R 18
R 13 10K
10K R 15 590K
CCW
CCW 1%
10K0
1% -1 5

Figure 12. Typical Compressor/Limiter Application Circuit

1. More information on this compressor design, along with suggestions for converting it to soft-knee operation, is given in THAT Design Note DN00A,
Basic Compressor Limiter Design. The designs in DN00A are based on THAT Corporation’s 2180-Series VCAs and 2252 RMS Detector, but are
readily adaptable to the 4301 with only minor modifications. In fact, the circuit presented here is functionally identical to the hard-knee circuit pub-
lished in DN00A.

THAT Corporation; 45 Sumner Street; Milford, Massachusetts 01757-1656; USA

Tel: +1 508 478-9200; Fax +1 508 478-0990; Email: info@thatcorp.com; Web: www.thatcorp.com
Copyright © 2017, THAT Corporation; All rights reserved.
THAT4301 Analog Engine® Page 9 of 12 Document 600069 Rev 10
IC Dynamics Processor

even-order distortion products. To adjust the trim, ap- from the RMS detector drive the output of OA1 posi-
ply to the input a middle-level, middle-frequency sig- tive, reverse biasing CR2 and forward biasing CR1. In
nal (1 kHz at 1 V is a good choice with this circuit) and this case, the junction of R9 and CR2 rests at 0 V, and
observe THD at the signal output. Set the trim for min- no signal level information is passed to the threshold
imum THD. detector’s output.
RMS-Level Detector In order to vary the threshold, R12, the THRESH-
OLD control, is provided. Via R11 (383 k), R12 adds
The RMS detector’s input is similar to that of the up to ±39.2 A of current to OA1‘s summing junction,
VCA. An input resistor (R6, 10 k) converts the ac in- requiring the same amount of opposite-polarity cur-
put voltage to a current within the linear range of the rent from the RMS detector output to counterbalance
4301. (Peak detector input currents should be kept it. At 4.99 k, the voltage across R8 required to pro-
under 1 mA for best linearity.) The coupling capacitor duce a counterbalancing current is ±195 mV, which
(C3, 47 f) is recommended to block dc current from represents a ±30 dB change in RMS detector input
preceding stages (and from offset voltage at the input level.
of the detector). Any dc current into the detector will
limit the low-level resolution of the detector, and will Since the RMS detector’s 0 dB reference level is
upset the rectifier balance at low levels. Note that, as 85 mV, the center of the THRESHOLD pot’s range
with the VCA input circuitry, C3 in conjunction with R6 would be 85 mV, were it not for R10 (2 M), which pro-
will set the lower frequency limit of the detector. vides an offset. R10 adds an extra –7.5 A to OA1‘s sum-
ming junction, which would be counterbalanced by
The time response of the RMS detector is deter- 37.4 mV at the detector output. This corresponds to
mined by the capacitor attached to CT (C4, 10 f) and 5.8 dB, offsetting the THRESHOLD center by this
the size of the current in pin IT (determined by R7, much to 165 mV, or approximately -16 dBV.
2 M and the negative power supply, –15 V). Since the
voltage at IT is approximately 0 V, the circuit of Fig- The output of the threshold detector represents
ure 12 produces 7.5 A in IT. The current in IT is mir- the signal level above the determined threshold, at a
rored with a gain of 1.1 to the CT pin, where it is constant of about 13 mV/dB (from [R9/R8] 6.5 mV/dB).
available to discharge the timing capacitor (C4). The This signal is passed on to the COMPRESSION control
combination produces a log filter with time constant (R13), which variably attenuates the signal passed on
equal to approximately 0.026 CT/IT (~35 ms in the cir- to OA2. Note that the gain of OA2, from the wiper of the
cuit shown). COMPRESSION control to OA2‘s output, is R16/R15
The waveform at CT will follow the logged (decibel) (0.5), precisely the inverse of the gain of OA1. There-
value of the input signal envelope, plus a dc offset of fore, the COMPRESSION control lets the user vary the
about 1.3 V (2 VBE). This allows a polarized capacitor above-threshold gain between the RMS detector out-
to be used for the timing capacitor, usually an electro- put and the output of OA1 from zero to a maximum of
lytic. The capacitor used should be a low-leakage type unity.
in order not to add significantly to the timing current.
The gain control constant of the VCA, 6.5 mV/dB,
The output stage of the RMS detector serves to is exactly equal to the output scaling constant of the
buffer the voltage at CT and remove the 1.3 V dc offset, RMS detector. Therefore, at maximum COMPRES-
resulting in an output centered around 0 V for input SION, above threshold, every dB increase in input sig-
signals of about 85 mV. The output voltage increases nal level causes a 6.5 mV increase in the output of OA2,
6.5 mV for every 1 dB increase in input signal level. which in turn causes a 1 dB decrease in the VCA gain.
This relationship holds over more than a 60 dB range With this setting, the output will not increase despite
in input currents. large increases in input level above threshold. This is
Control Path infinite compression. For intermediate settings of
COMPRESSION, a 1 dB increase in input signal level
A compressor/limiter is intended to reduce its gain will cause less than a 1 dB decrease in gain, thereby
as signals rise above a threshold. The output of the varying the compression ratio.
RMS detector represents the input signal level over a
wide range of levels, but compression only occurs The resistor R14 is included to alter the taper of the
when the level is above the threshold. OA1 is config- COMPRESSION pot to better suit common use. If a
ured as a variable threshold detector to block envelope linear taper pot is used for R13, the compression ratio
information for low-level signals, passing only infor- will be 1:2 at the middle of the rotation. However, 1:2
mation for signals above threshold. compression in an above-threshold compressor is not
OA1 is an inverting stage with gain of 2 above very strong processing, so 1:4 is often preferred at the
threshold and 0 below threshold. Neglecting the action midpoint. R14 warps the taper of R13 so that 1:4 com-
of the THRESHOLD control (R12) and its associated pression occurs at approximately the midpoint of
resistors (R11 and R10), positive signals from the RMS R13‘s rotation.
detector output drive the output of OA1 negative. This
The GAIN control (R18) is used to provide static
forward biases CR2, closing the feedback loop such
that the junction of R9 and CR2 (the output of the gain or attenuation in the signal path. This control
threshold detector) sits at -(R9/R8) RMSOUT. For the cir- adds up to ±130 mV offset to the output of OA2
cuit of Figure 12, this is –2 RMSOUT. Negative signals

THAT Corporation; 45 Sumner Street; Milford, Massachusetts 01757-1656; USA

Tel: +1 508 478-9200; Fax +1 508 478-0990; Email: info@thatcorp.com; Web: www.thatcorp.com
Copyright © 2017, THAT Corporation; All rights reserved.
THAT4301 Analog Engine® Page 10 of 12 Document 600069 Rev 10
IC Dynamics Processor

𝑅16 𝑅16 static gain may be added up to ±20 dB. Audio perfor-
(from −𝑉 + to −𝑉 − ), which is approximately
𝑅17 𝑅17 mance is excellent, with THD running below 0.05% at
±20 dB change in gain of the VCA. C5 is used to atten- middle frequencies even with 10 dB of compression,
uate the noise of OA2, OA1 and the resistors R8 through and an input dynamic range of over 115 dB.
R16 used in the control path. All these active and pas- Perhaps most important, this example design only
sive components produce noise which is passed on to
scratches the surface of the large body of applications
the control port of the VCA, causing modulation of the
circuits which may be constructed with THAT 4301.
signal. By itself, the 4301 VCA produces very little
The combination of an accurate, wide-dynamic-range,
noise modulation, and its performance can be signifi-
cantly degraded by the use of noisy components in the log-responding level detector with a high-quality, expo-
control voltage path. nentially-responding VCA produces a versatile and
powerful analog engine. The opamps provided in the
Overall Result 4301 enable the designer to configure these building
The resulting compressor circuit provides hard- blocks with few external components to construct
knee compression above threshold with three essen- gates, expanders, de-essers, noise reduction systems
tial user-adjustable controls. The threshold of com- and the like.
pression may be varied over a ±30 dB range from For further information, samples and pricing,
about –46 dBV to +14 dBV. The compression ratio please contact us at the address below.
may be varied from 1:1 (no compression) to :1. And,

THAT Corporation; 45 Sumner Street; Milford, Massachusetts 01757-1656; USA

Tel: +1 508 478-9200; Fax +1 508 478-0990; Email: info@thatcorp.com; Web: www.thatcorp.com
Copyright © 2017, THAT Corporation; All rights reserved.
THAT4301 Analog Engine® Page 11 of 12 Document 600069 Rev 10
IC Dynamics Processor

Package Characteristics
Parameter Symbol Conditions Typ Units

Thru Hole Package See below for pinout and dimensions 20 pin DIP

Thermal Resistance θJA DIP package soldered to board 65 ºC/W

Environmental Regulation Compliance Complies with RoHS requirements

Surface Mount Package See below for pinout and dimensions 20 pin SO

Thermal Resistance JA SO package soldered to board 70 ºC/W

Soldering Reflow Profile JEDEC JESD22-A113-D (250 ºC)

Moisture Sensitivity Level MSL 3

Environmental Regulation Compliance Complies with RoHS requirements

D Ø
20 11

1 10
E1 E
L1
A L

D 1
N
e c
L

O P
A2
SE A TING
F G B PLANE
E H
J
A1 A
b x 20

Inches MM
SYM Min Max Min Max Inches MM
A 1.025 1.035 26.04 26.29
SYM Min Max Min Max
B 0.300 BSC 7.62 BSC
A 0.096 0.104 2.43 2.64
C 0.245 0.255 6.23 6.48
A1 0.005 0.012 0.13 0.30
D 0.300 0.325 7.62 8.26
A2 0.089 0.096 2.26 2.44
E 0.100 BSC 2.54 BSC b 0.012 0.020 0.30 0.50
F 0.014 0.022 0.36 0.56 c 0.008 0.030 0.20 0.76
G 0.005 — 0.12 — D 0.502 0.510 12.75 12.95
H 0.045 0.070 1.14 1.78 E1 0.291 0.299 7.39 7.60
J 0.320 0.380 8.12 9.64 E 0.396 0.416 10.05 10.57
L 0.125 0.135 3.18 3.43 e 0.050 TY P 1.27 TY P
N 0.015 0.025 0.38 0.64 L 0.016 0.050 0.41 1.27
O 0. 115 0.150 2.92 3.81 L1 0.051 0.059 1.29 1.50
P 0.008 0.012 0.20 0.30 Ø 0° 8° 0° 8°

Figure 13. 20 pin DIP package outline Figure 14. 20 pin SO package outline

Pin Name Pin Number Pin Name Pin Number

RMS IN 1 OA1 +IN 20
IT 2 OA1 –IN 19
No Internal Connection 3 OA1 OUT 18
RMS OUT 4 VCA IN 17
CT 5 EC- 16
OA2 –IN 6 EC+ 15
OA2 OUT 7 SYM 14
OA2 +IN 8 VCA OUT 13
GND 9 OA3 OUT 12
VEE 10 VCC 11
Table 2. THAT 4301 pin assignments

THAT Corporation; 45 Sumner Street; Milford, Massachusetts 01757-1656; USA

Tel: +1 508 478-9200; Fax +1 508 478-0990; Email: info@thatcorp.com; Web: www.thatcorp.com
Copyright © 2017, THAT Corporation; All rights reserved.
THAT4301 Analog Engine® Page 12 of 12 Document 600069 Rev 10
IC Dynamics Processor

Revision History
Revision ECO Date Changes Page

00 — 6/24/1999 Initial Release —

01 — 7/5/2006 Added C9 to Figure 14; Moved order information chart. 1, 9

Added missing pin numbers to Table 2. Corrected symbols in
02 — 8/24/2007 2, 3, 5
specs.
03 — 1/26/2009 Corrected equation typos in the opamp section. 8

04 2748 12/10/2012 Corrected typo. in the surface mount package diagram. 5

1, 5,
05 2849 1/28/2014 Moved Package Characteristics and Outline drawings to page 11.
11
06 2855 3/10/2014 Corrected pin assignments in Table 2. 11

07 2866 3/31/2014 Added watermark that A version is discontinued. —

08 2867 4/1/2014 Removed 'A' version, Chg'd lead finish, added 20p SO Wide pkg —

09 2977 5/24/2016 Removed "Advanced Information" watermark from Figure 14 11

10 3011 6/1/2017 Corrected x-axis label in figure 10. Document redrawn. —

THAT Corporation; 45 Sumner Street; Milford, Massachusetts 01757-1656; USA

Tel: +1 508 478-9200; Fax +1 508 478-0990; Email: info@thatcorp.com; Web: www.thatcorp.com
Copyright © 2017, THAT Corporation; All rights reserved.