b. V/ith the help of neat diagram, explain the operation of following types of shift registers. Rcg. No.

(i) slso
(ii) SIPO
(iiD PIPO B.Tech. DEGREE EXAMINATION, MAY 2017
(iv) PISO Third i Fourth Semester

32. a. Implement BCD to gray code converter using Programmable Logic Anay @LA). 15EC2O3J -
DIGITAL SYSTEMS
the academic year 201 5 2016 onwards)
(For the candidates admitted during -
Note:
(oR) (D part - A should be answered in OMR sheet within first 45 minutes and OMR sheet should be handed
over to hall invigitator at the end of 45tr minute.
b. Explain the construction and working of the Programmable Logic Devices @LD) with neat (ii) Part - B and Part - C should be answered in answer booklet.
diagram.
Time: Three Hours Max. Marks: 100
****{.
PART-A(20 xl=20 Marks)
Answer ALL Questions

1. Excess-3 code is known as

(A) Weighted code @) Redundancy code
(C) Self complementarY code (D) Algebraic code

2. The logical expression Y - A+ ZB

(A) Y:A (B) Y:A+B
(c) Y:AB (D) Y:B

3. Convert the following binary number into decimal number 10110

(A) 12 (B) 6
(c) 23 @) 22

4. The output of a logic gate is 1 when all its inputs are at logic 0, the gate is either
(A) NOR or an EX-NOR (B) ORor anNOR
(C) EX-ORoTNAND (D) AND orEX-OR

5. Which logic family provide minimum power dissipation?

(A) TTL (B) ECL
(c) RrL (D) cMos

6. Which of the logic family as the fastest switching speed?

(A) TTL (B) ECL
(c) RrL (D) HrL

7. Suppose that the digitat IC family has a fan out of 6. It implies that the gate can supply the
current to of same family
(A) 6 inputs (B) 6 outPuts
(C) 12 inputs (D) 12 outPuts
8. Full Adder (FA) can be implemented with Half Adder (HA) and OR gate 4 bit parallel adder
without any initial carry requires
(A) 8 IIA 3 OR gate (B) 8 IIA 2 OR gate
(C) 7 HA4 ORgate (D) 7 HA3 ORgate

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 9' Which one of the fo[owing set of gates are best suited to parity checking
and generators?
(A) AND, O& NOT 20. PALs tend to execute logic
(B) ElGroR, sioR. (A) SAP
(C) NANDandNoR (D) NANDandAND (c) Pos
(B) SOP
(D) SPD
10' The binary number A=l100 and 8:1001 are applied to the inputs of a comparator
what are
the output levels?
(A) A>B=1, A<B:0, A>B-l (B) A>B:1, A<B{,A:B:0
(C) A>B:0,<B-I,A:B--0 (D) A>B:0, A<B:1, A:B:l
PART-B(5x4-20Marks)
11. is representation of encoder Answer Af{y FM euestions
(A) l:n (B) 2n,n 21. Add
(C) n:2n (D) t:zn (i) (tot), +(rzs),
12.
1!*i: MIIX principle can be demonstrated through the use of a
(A) Single pole relay (iD (:ra),u +(s.a:),u
(B) DPDT switch
(C) Rotary switch 1fry tirea, stepper )) Simplifr AB + ABC + A(B + AB)
13. The storage element for a static RAM is
(A) Diode @) Resistor )?, Realize half adder circuit using NAND gates and give its truth table.
(C) Flip-fiop (D) Capacitor
24. Implement the function using decoder
14. The output this circuit is always F =L(2,3,7)

)s Desigrr and construct MOD5 asynchronous counter.

26. Briefly discuss on fan in and fan out.

(A) A (B) A 27. Differentiate DRAM and SRAM.

(c) I (D) 0
15. In the toggle mode a JK-FF has ' PART-C(5x
Answer ALL
t1-=60Marks)
(A) J:0, K:0 (B) J=1, K:0
euestions
(c) J{, K:l (D) J=1,K=1 28. a. Simpliff the following Boolean function using K-map
F (A, B,C, D) = Z m(0,2,3,6,7,8,1 O,lZ,l3,I 5)
16. How many flip flops are required to build a binary counter circuit to count from
0-1023?
(A) 24 (B) t2
(c) l0 (D) 8 b. simpliff the following Bootean *",,ont3r?, euine Mc-clusky method.
F (A, B, C, D) _ (0,2,3, 6,7,g,10,12,13)
17. Anibbleisequalto
(A) 8 (B) 4 29. a. Explain the working principle of two input NAND gate totem pole circuit.
(c) 2 (D) I
(oR)
l{gw manv storage locations are available when a memory device has
18.
12 address line? b. Explain the operation of CMOS
(A) 40e6 (B) 204S
NAND and NOR gates.
(c) st2 (f,D 144 30. a Explain carry look ahead adder.
19. How many address line are needed to select all memory locations in 16 k x I RAM?
(A)8 (B)4
(c) 16 (D) r+
b. Draw the logic diagram for an even
O*[,?"."ror and checken

31. a. Design MOD- I 0 synchronous counter.

PaEe Z of 4
(oR)
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