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RTL Sandesh P 1.3years

This document contains a resume for Sandesh P. It summarizes his education, technical skills, trainings, work experience and projects. For his education, it lists that he earned a B.E. in Electronics and Communication from Canara Engineering College in 2018. It also provides details on two technical projects he worked on, including developing an I2S Master Controller Core IP and designing an asynchronous FIFO. It concludes with his personal details and a declaration.

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chaitanyh
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193 views3 pages

RTL Sandesh P 1.3years

This document contains a resume for Sandesh P. It summarizes his education, technical skills, trainings, work experience and projects. For his education, it lists that he earned a B.E. in Electronics and Communication from Canara Engineering College in 2018. It also provides details on two technical projects he worked on, including developing an I2S Master Controller Core IP and designing an asynchronous FIFO. It concludes with his personal details and a declaration.

Uploaded by

chaitanyh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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SANDESH.

P
+91-8496055568

OBJECTIVE:

To utilize my knowledge and skills for achieving the target and for betterment of the
organization and myself.

EDUCATION:

Qualification Institution Board Percentage Year of


Passing
B.E. Canara Engineering VTU 64.3 2018
(Electronics and College
Communication)

12th Std. Kendriya Vidyalaya CBSE 87.8 2014


No.1
10th Std. Kendriya Vidyalaya CBSE CGPA 9.4 2012
No.1

TECHNICAL SKILLS:
 Good understanding and hands-on experience with RTL design methodology
 Well versed with Micro-architecture design, RTL coding with Verilog/System Verilog
 Have designed and implemented multiple IPs from architecture to implementation and
proven the designs on Xilinx FPGAs
 Expertise in Design tools like LINT, CDC
 Strong knowledge in ASIC and FPGA Logic Synthesis, Timing Analysis, Timing
closure and UPF (for ASIC)
 Familiarity with multiple simulators and debugging
 Strong knowledge in Bus architecture in AHB and APB
 Strong programming skill in Perl

TRAININGS ATTENTED :
 Scripting in Perl
 Overview of ASIC flow
 Overview of SDC
 Overview of CDC
 Session on Synthesis using DC
WORK EXPERIENCE :
1. Working in Cientra Tech solution since April 2019 till today.

Customer 1 - SOC (7nm, 100MG)


Duration: 7 months
 Generating and delivering RTL list and hiplist to backend.
 Elaborating the design, recognize and fix bugs if encountered.
 Synthesis using Synopsys DC for 3 blocks and delivering netlist to DFT and
timing team.
 Sim2syn LEC using Cadence Conformal for comparison between synthesis and
simulation RTL.
 FEV lite using Cadence Conformal with UPF for 3 blocks to elaborate the
design.
 Caliber using Synopsys Prime time for 2 blocks and generate reports for given
ruleset. Create waivers if any.

PROJECT 1:
Title I2S Master Controller Core for CPUSS
Programming SystemVerilog
language
Platform/EDA Vivado, Modelsim for RTL Simulation, Zboard-Sparten3AN FPGA kit.
Tool
Brief I2S-Master core is a half-duplex, three wire synchronous serial audio
description interface IP used to communicate PCM audio data between integrated
circuits with APB host Interface. In order to improve the throughput of the
overall system, core implements the configurable Rx and Tx FIFO depths.
Furthermore, the core supports multiple clock modes and word length on
which data is transmitted to slave.
Bus interface logic for native bus SoC integration is done with the APB
interface block.
Team size 3
Responsibility: Individual contributor in creating micro-architecture from Spec and
development of I2S Master Controller Core IP for CPU Subsystem.
Creation of Makefile.
The IP is simulated and synthesized using various industry standard tools.
The design has also been taken through various LINT and CDC checks for
conformance checks.
I2S Master Controller Core IP is integrated to CPU-Subsytem, along with
CPU(RISC-V Core) & 15+ other IPs including GPIO interface. I2S Master
+ I2S Slave were tested together as part of this platform.
Project Currently all the 15+ IPs are functional on FPGA platform and are now
Outcome getting tested with Cientra’ internally developed RISC-V processor IP
having AHB bus.
PROJECT 2:
Title Asynchronous FIFO Design
Language System Verilog
Tools ALDEC Riviera Pro
Duration 10 Days
Description:
This project involves the design and functional verification of asynchronous FIFO
using system Verilog. Constrained random test-bench is developed to generate
random stimulus to the DUT and to check its response. Different TB components like
generator, driver, monitor and scoreboard were developed. Different functionalities
like write, read, full generation, empty generation and reset scenarios were verified for
asynchronous FIFO.

PERSONAL DETAILS:
DOB: 21-10-1996

PRESENT ADDRESS:

#24, Lilac Residency, 10th cross, 2nd main, 1st cross Rd, Manjunatha Layout,
Munnekollal, Bengaluru,
560037
PERMANENT ADDRESS:

"Shree Ganesha", Sneha Nagara, 2nd cross, Fisheries Rd, Kulai- Hosabettu,

Mangalore,

575019

DECLARATION:
I hereby declare that all the statements made above are true, complete and correct to the best of
my knowledge and belief.

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