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Low Power Design Methodology

Low-power design methodology needs to be applied at all levels of design from system to physical to effectively reduce power in digital circuits. Reducing supply voltage is very effective for reducing dynamic power but hurts performance. A variety of techniques can compensate for this performance loss at different design levels, including device scaling, parallelism, voltage and frequency scaling. Switching activity can also be reduced through optimizations at the algorithmic, architectural, logic style, and encoding levels to minimize capacitance and reduce dynamic power. As technology scales, leakage power is becoming a dominant factor, necessitating techniques like input vector control, body bias control, and multi-threshold CMOS to reduce standby and runtime leakage.

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97 views3 pages

Low Power Design Methodology

Low-power design methodology needs to be applied at all levels of design from system to physical to effectively reduce power in digital circuits. Reducing supply voltage is very effective for reducing dynamic power but hurts performance. A variety of techniques can compensate for this performance loss at different design levels, including device scaling, parallelism, voltage and frequency scaling. Switching activity can also be reduced through optimizations at the algorithmic, architectural, logic style, and encoding levels to minimize capacitance and reduce dynamic power. As technology scales, leakage power is becoming a dominant factor, necessitating techniques like input vector control, body bias control, and multi-threshold CMOS to reduce standby and runtime leakage.

Uploaded by

chiranjeevi muppala
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Low Power Design Methodology

Low-power design methodology needs to be applied


throughout the design process starting from system level to
physical or device level to get effective reduction of power
dissipation in digital circuits based on MOS technology. Various
approaches can be used at different level of design hierarchy.
As the most dominant component has quadratic dependence
and other components have linear dependence on the supply
voltage, reducing the supply voltage is the most effective means
to reduce dynamic power consumption. Unfortunately, this
reduction in power dissipation comes at the expense of
performance. It is essential to devise suitable mechanism to
contain this loss in performance due to supply voltage scaling for
the realization of low- power high-performance circuits. The loss
in performance can be compensated by using suitable techniques
at the different levels of design hierarchy; that is physical level,
logic level, architectural level, and system level. Techniques like
device feature size scaling, parallelism and pipelining,
architectural-level transformations, dynamic voltage, and
frequency scaling.
Apart from scaling the supply voltage to reduce dynamic
power, another alternative approach is to minimize the switched
capacitance comprising the intrinsic capacitances and
switching activity. Choosing which functions to implement in
hardware and which in software is a major engineering challenge
that involves issues such as cost complexity, performance, and
power consumption. From the behavioral description, it is
necessary to perform hardware/software partitioning in a
judicious manner such that the area, cost, performance, and power
requirements are satisfied. Transmeta’s Crusoe processor is an
interesting example that demonstrated that processors of high
performance with remarkably low power consumption can be
implemented as hardware–software hybrids. The approach is
fundamentally software based, which replaces complex hardware
with software, thereby achieving large power savings.
In CMOS digital circuits, the switching activity can be
reduced by algorithmic optimization, by architectural
optimization, by use of suitable logic-style or by logic- level
optimization. The intrinsic capacitances of system-level busses
are usually several orders of magnitude larger than that for the
internal nodes of a circuit. As a consequence, a considerable
amount of power is dissipated for transmission of data over I/O
pins. It is possible to save a significant amount of power reducing
the number of transactions, i.e., the switching activity, at the
processors I/O interface. One possible approach for reducing the
switching activity is to use suitable encoding
of the data before sending over the I/O interface. The concept is
also applicable in the context of multi-core system-on-a-chip
(SOC) design. In many situations the switching activity can be
reduced by using the sign-magnitude representation in place of the
conventional two’s complement representation. Switching
activity can be reduced by judicious use of clock gating, leading
to considerable reduction in dynamic power dissipation. Instead
of using static CMOS logic style, one can use other logic styles
such as pass-transistor and dynamic CMOS logic styles or a
suitable combination of pass-transistor and static CMOS logic
styles to minimize energy drawn from the supply.

Although the reduction in supply voltage and gate


capacitances with device size scaling has led to the reduction in
dynamic power dissipation, the leakage power dissipation has
increased at an alarming rate because of the reduction of threshold
voltage to maintain performance. As the technology is scaling
down from submicron to nanometer, the leakage power is
becoming a dominant component of total power dissipation. This
has led to vigorous research for the reduction of leakage power
dissipation. Leakage reduction methodologies can be broadly
classified into two categories, depending on whether it reduces
standby leakage or runtime leakage. There are various standby
leakage reduction techniques such as input vector control (IVC),
body bias control (BBC), multi-threshold CMOS (MTCMOS),
etc. and runtime leakage reduction techniques such as static dual
threshold voltage CMOS (DTCMOS) technique, adaptive body
biasing, dynamic voltage scaling, etc.

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