The document contains questions about digital design for test (DFT) techniques including scan chain design and implementation, ATPG flows, fault models, and memory testing. Specific topics addressed include scan methodology, scan frequency, linear feedback shift registers, DFT friendly design practices, test pattern generation, fault simulation, boundary scan, and compression techniques.
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The document contains questions about digital design for test (DFT) techniques including scan chain design and implementation, ATPG flows, fault models, and memory testing. Specific topics addressed include scan methodology, scan frequency, linear feedback shift registers, DFT friendly design practices, test pattern generation, fault simulation, boundary scan, and compression techniques.
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1. Why do we need testing ?
2. Explain scan methodology?
3. What is scan frequency? 4. What is lfsr? 5. How many flops are used in your project? ( complete project analysis) 6. Why scan chain contain first negedge scan flop then posedge scan flop? 7. Is lockup latch DFT friendly? 8. what is difference between transparent and non-transparent latch ? 9. Why DFT is required? Can we achieve DFT goals by any other method? 10. Where DFT part fit in ASIC design flow? 11. What is compression ratio? where do compressed scan chains come from? 12. what are possible root causes for compression DRC's? 13. what is the tool used for compression in mentor , synopsis and cadence ? 14. what is the DRC number if you get a violation related to preexisting scan flops exists in netlist before performing scan insertion ? 15. What are the techniques used to reduce pattern count without losing coverage ? 16. What is ATPG Flow? 17. Imagine you have to perform Stuck at and Transition ATPG runs , which one will you trigger first and why ? 18. Are the faults on the resets of the flops are detected? if so how are they detected? 19. when both the Transition-delay and path_delay target for transition faults, why we should have two different methods to detect the same? 20. What is the difference between multi cycle path and false path? 21. Write 5 different commands of SDC? 22. Write the command to increase the abort limit 23. What is sequential depth ? 24. What are ATPG Untestable faults , its sub categories ? 25. Which one is better AATPG or LBIST for testing a core logic ? 26. What is RPG? 27. What is D Algorithm , explain different stages in D Algorithm ? 28. What is difference between fault , error and defect ? 29. What is fault grading ? 30. which scan style is preferred for scan insertion and why? 31. How to fix black box violation? 32. What are the reasons for scan chain broken? 33. How to debug faults in fault simulation? 34. Explain complete test procedure for fault simulation? 35. Explain sample and preload instruction? 36. Applications of boundary scan? 37. How to decide capture cycles and shift cycles? 38. What is terminal lockup latch? 39. What are redundant faults? 40. Is there any need of pll when functional frequency equals to scan frequency? 41. Why scan clock is slow frequency? What if we give high frequency for scan chains? 42. What is shadow logic? 43. Why multi clock domains is used? Does it have any problem in design? 44. What logic we see in test point insertion? 45. What is named capture procedures? 46. Explain the decompression logic? 47. why reset is optional in jtag? When reset state occurs? 48. Explain architecture for compression? 49. why we do scan chain balancing? 50. Explain tap controller working? On what edge tap works? 51. What is fault collapsing, equivalence and dominance? 52. what are different types of fault models? 53. How to detect stuck at faults? Explain with diagram? 54. How do you test at-speed faults for inter clock domains? 55. What is integrated clock gating? 56. What is meant by scan chain pattern? Why it require? 57. In your design you have dual port memories each working at a different frequency. What is the clock frequency you use for testing (MBIST)? 58. What are the differences between IJTAG and JTAG standard? 59. What are the differences between Boundary scan and IEEE1500 standards? 60. What is the effect of LOS method for testing delay faults on the tester? 61. What are the typical issues you face during timing simulation of scan? 62. How do you implement DFT for a design have lot of Analog blocks? How to improve coverage? 63. Are multi-cycle paths tested in the design? 64. What are the typical steps to improve coverage when our coverage target is not achieved? 65. Steps to fix broken scan chain issues during ATPG? Write Step by step procedure to find the issue? 66. In SDF we have 3 values best, typical and worst case? Best is for good processor, less temp , high vol and worst is reverse. What is typical? 67. What is split capture clock cycle in ATPG? 68. .what are the basic things that needs to take care for Scan Insertion? 69. why we don't go for higher compression ratio like 90-100%? 70. Suppose if you get hold violation in simulations , how you fix that? 71. why we do MBIST Insertion and verification? Which tool you are using 72. what are typical memory faults? 73. what is neighborhood and coupling faults how these faults are different from each other? 74. which tool did you use for MBIST insertion? 75. what are the mandatory instructions in JTAG? 76. Draw and explain the TAP state machine with tms values? 77. what all ctls you read while scan insertion? 78. Consider two flop of .2sec and 0.3 sec latency how do you connect the flops in scan chain? 79. What is the importance of shift registers residing inside OCC logic ? 80. Which is the better way of implementation of DFT , hierarchical or flat and why ?