Scribd
Upload
152 views1 page

PD Interview Questions - Set1

This document contains questions about various stages of the chip design process including: 1. Experience working on different design modules. 2. Differences between OCV, AOCV and POCV design approaches and experience with AOCV. 3. Checks needed before applying timing constraints like derate values. 4. Tools and inputs used for noise analysis including noise libraries. 5. Differences between check_timing and report_timing as well as reasons for higher than expected register-to-register timing in the design. 6. Checks and steps to move from the final design check to physical design implementation and signoff.

Uploaded by

sai jagadeesh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
152 views1 page

PD Interview Questions - Set1

This document contains questions about various stages of the chip design process including: 1. Experience working on different design modules. 2. Differences between OCV, AOCV and POCV design approaches and experience with AOCV. 3. Checks needed before applying timing constraints like derate values. 4. Tools and inputs used for noise analysis including noise libraries. 5. Differences between check_timing and report_timing as well as reasons for higher than expected register-to-register timing in the design. 6. Checks and steps to move from the final design check to physical design implementation and signoff.

Uploaded by

sai jagadeesh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 1

1.

Self-Introduction (5 min)
2. In what module you have worked in previous project?
3. Diff b/w OCV,AOCV and POCV and how you approached AOCV in your design?
4. Does anything need to be set before applying DERATE value like timing constraints?
5. Noise libraries, nldm lib, RC corners lib
6. Diff between COS and RCOS corners?
7. Diff between GLITCH and CROSSTALK?
8. Tools used to analyze CROSSTALK? And input needed for noise?
9. Scenerio: If I have Only one internal violation and tapeout in next two days, How will you know
this one violation is hazardous or non-mandate to fix??
10. If I give RTL to you, how will you start the work?
11. Diff between check_timing and Report_timing?
12. What is your reg2reg WNS/TNS in your DC final netlist? If it extremely higher than your clock
period what is the reason could be?
13. What is your ICG WNS in DC?
14. How will you decide your final DC netlist is good to go ahead with PNR?
15. Tell me the implementation of Final netlist to PNR?
16. How will you do power planning?
17. What is the highest metal layer used for power bumps and upto what layer you have dropped
Vias to macros and why?
18. I have one macro where I can put via till m1 and in another macro I can't put vias beyond m4--
why??
19. How will you place macros and IO ports?
20. How will you analyze congestion after placement? What are methods to prevent congestion?
21. What is your Utilization ratio in your design?
22. How decap cells placed in your design? (he meant distance bw two decap cells and it's pattern)
23. What checks to be done after placement? Hw will you fix setup violation?
24. How will you do CTS and by what way you synthesis your clocks?
25. How will you check routing congestion?
26. If I have CLOCK DRC's but my timing LEC and all met, Can I still go for tapeout? If no, why and
how will you identify CLOCK DRC's and its fix method?
27. Have you done all LVS fixes and how?
28. How about LEC verification you have handled?
29. What are the signoff checks you have done after Routing DB dumped?
30. How will you implement ECO's? what are the timing ECO's you have implemented?
31. Have you done CROSSTALK fixes and how?

You might also like

pFad - Phonifier reborn

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.

Note: This service is not intended for secure transactions such as banking, social media, email, or purchasing. Use at your own risk. We assume no liability whatsoever for broken pages.


Alternative Proxies:

Alternative Proxy

pFad Proxy

pFad v3 Proxy

pFad v4 Proxy