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Neotec Semiconductor Ltd.

新德科技股份有限公司

NT7086PQ
LCD Driver
Version 1.0

INTRODUCTION
The NT7086PQ is a LCD driver LSI that is fabricated by low power CMOS high voltage process
technology.
In segment drive mode, it can be interfaced in 1-bit serial or 4-bit parallel method by the controller.
In common drive mode, dual type mode is applicable. And in segment mode application, the power down
function reduces power consumption.

FEATURES
•Power supply voltage:+5 V±10%, + 3V±10%
•Supply voltage for display: 6 to 28 V (VDD-VEE)
•4-bit parallel/1-bit serial data processing (in segment mode)..
•Single mode operation / dual mode operation (in common mode).
•Power down function (in segment mode).
•Applicable LCD duty:1/64 ~ 1/256
•Interface

DRIVERS
COM(cascade) SEG(cascade)
NT7086PQ NT7086PQ

•High voltage CMOS process.

•Available PKG type : bare chip, 100-LQFP, 100-QFP

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Neotec Semiconductor Ltd.

新德科技股份有限公司

NT7086PQ
LCD Driver
Version 1.0

PKG TYPE = 100-LQFP

PKG THICKNESS = 1.40 (± 0.05) mm
PKG SIZE = 14.00 (± 0.10) X 14.00 (± 0.10) mm
PAD PITCH = 0.5 mm
PAD WIDTH = 0.20 ( +0.07,-0.03) mm
PAD LENGTH = 1.0 (±0.1) mm

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Neotec Semiconductor Ltd.

新德科技股份有限公司

NT7086PQ
LCD Driver
Version 1.0

PKG TYPE = 100-QFP

PKG THICKNESS = 3.00 (± 0.40) mm
PKG SIZE = 24.80(± 0.20) X 18.8 (± 0.20) mm
PAD PITCH = 0.65 mm
PAD WIDTH = 0.30 (± 0.10) mm
PAD LENGTH = 2.4 (± 0.20) mm

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Neotec Semiconductor Ltd.

新德科技股份有限公司

NT7086PQ
LCD Driver
Version 1.0

PAD DIAGRAM Note: Please connects the substrate to VDD or Floating

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Neotec Semiconductor Ltd.

新德科技股份有限公司

NT7086PQ
LCD Driver
Version 1.0

PAD LOCATION

Pad No. Pad name X Y Pad No. Pad name X Y

1 SC51 -1313.50 1746.00 51 SC1 1542.00 -1754.00
2 SC52 -1544.00 1746.00 52 SC2 -1629.00
3 SC53 1621.00 53 SC3 -1504.00
4 SC54 1496.00 54 SC4 -1379.00
5 SC55 1371.00 55 SC5 -1254.00
6 SC56 1246.00 56 SC6 -1129.00
7 SC57 1121.00 57 SC7 -1004.00
8 SC58 996.00 58 SC8 -879.00
9 SC59 871.00 59 SC9 -754.00
10 SC60 746.00 60 SC10 -629.00
11 SC61 621.00 61 SC11 -504.00
12 SC62 496.00 62 SC12 -379.00
13 SC63 371.00 63 SC13 -254.00
14 SC64 246.00 64 SC14 -129.00
15 SC65 121.00 65 SC15 -4.00
16 SC66 -4.00 66 SC16 121.00
17 SC67 -129.00 67 SC17 246.00
18 SC68 -254.00 68 SC18 371.00
19 SC69 -379.00 69 SC19 496.00
20 SC70 -504.00 70 SC20 621.00
21 SC71 -629.00 71 SC21 746.00
22 SC72 -754.00 72 SC22 871.00
23 SC73 -879.00 73 SC23 996.00
24 SC74 -1004.00 74 SC24 1121.00
25 SC75 -1129.00 75 SC25 1246.00
26 SC76 -1254.00 76 SC26 1371.00
27 SC77 -1379.00 77 SC27 1496.00
28 SC78 -1504.00 78 SC28 1621.00
29 SC79 -1629.00 79 SC29 1746.00
30 SC80 -1754.00 80 SC30 1311.50
31 ERB -1218.40 81 SC31 1186.50
32 VEE -1048.70 82 SC32 1061.50
33 V5 -923.70 83 SC33 936.50
34 V43 -798.70 84 SC34 811.50
35 V12 -673.70 85 SC35 686.50
36 V0 -548.70 86 SC36 561.50
37 CS -380.00 87 SC37 436.50
38 M -255.00 88 SC38 311.50
39 DISPOFFB -130.00 89 SC39 186.50
40 VDD -5.00 90 SC40 61.50
41 SHL 120.10 91 SC41 -63.50
42 VSS 245.10 92 SC42 -188.50
43 D4_DR 370.10 93 SC43 -313.50
44 D3_DM 495.10 94 SC44 -438.50
45 D2_DL 620.10 95 SC45 -563.50
46 D1_SID 745.10 96 SC46 -688.50
47 CL2 870.10 97 SC47 -813.50
48 AMS 995.10 98 SC48 -938.50
49 CL1 1120.10 99 SC49 -1063.50
50 ELB 1245.10 100 SC50 -1188.50

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Neotec Semiconductor Ltd.

新德科技股份有限公司

NT7086PQ
LCD Driver
Version 1.0

BLOCK DIAGRAM

SC1 SC2 SC3 SC78 SC79 SC80

......

V0
V12 80-bit 4-level driver
V43
V5
..............

VEE
80-bit level driver
M Output
DISPOFFB level
..............
selector
D1_SID
D2_DL
LCK 80 bit data latch /
D3_DM
common data bidirectional shift register
D4_DR
..............

SCK 20 X 4-bits segment data

bidirectional shift register

CL1 Data latch control

CL2
Clock
control

CS Power down ERB

AMS function

VDD
VSS

ELB

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Neotec Semiconductor Ltd.

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NT7086PQ
LCD Driver
Version 1.0

BLOCK DESCRIPTION

NAME FUNCTION COM / SEG

Generates latch clock (LCK), shift clock (SCK) and control clock
timing according to the input of CL1, CL2 and control inputs (CS,
Clock control AMS). In common driver application mode, this block generates COM / SEG
the shift clock (LCK) for the common data Bi-directional shift
register.
Determines the direction of segment data shift, and input data of
each Data latch Bi-directional shift register. In 4-bit segment data
Data latch
parallel transfer mode, data is shifted by a 4-bit unit. In common SEG
control
driver application mode, data is transferred to the common data
shift register directly, which disables this block.
Controls the clock enable state of the current driver according to
the input value of enable pin (ELB or ERB). If enable input value
Power down is “Low”, every clock of the current driver is enabled and the
SEG
function clock control block works. But if enable input is “High”, current
driver is disabled and the input data value has no effect on the
output level. So power consumption can be lowered.
Output level Controls the output voltage level according to the input control pin
COM / SEG
selector (M and DISPOFFB) (refer to PIN DESCRIPTION).
Stores output data value by shifting the input values. In 1-bit serial
20x4-bitsegm
interface mode application, all 80 shift clocks (SCK) are needed to
ent data
store all the display data. But in 4-bit parallel transfer mode SEG
bi-directional
application, only 20 clocks are needed. In common driver
shift register
application mode, this block does not work.
In segment driver application mode, the data from the 20x4-bit
80-bit data segment data shift register are latched for segment driver output.
latch / In single-type common driver application, 1-bit input data (from
common data DL or DR pin) is shifted and latched by the direction according to COM / SEG
bi-directional the SHL signal input. In dual-type common application mode,
shift register 80-bit registers are divided by two blocks and controlled
Independently (refer to NOTE 3).
Voltage level shifter block for high voltage part. The inputs of this
80-bit level
block are of logical voltage level and the outputs of this block are SEG
shifter
at high voltage level value. These values are input in to the driver.
Selects the output voltage level according to M and latched data
value. If the data value is "High" the driver output is at selected
80-bit 4-level voltage level (V0 or V5), and in the reverse case the driver output
SEG
driver value is at the non-selected level (V12 or V43). In segment driver
application mode, non-selected output value is V2 or V3 and
when in common driver application, this value becomes V1 or V4.

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Neotec Semiconductor Ltd.

新德科技股份有限公司

NT7086PQ
LCD Driver
Version 1.0

PIN DESCRIPTION

PIN I/O NAME FUNCTION INTERFACE

Logical "High" input port (+5V±10%, +3V±
VDD
Power 10%)
Power
VSS supply 0V (GND)
VEE Logical "Low" for high voltage part
LCD driver Bias supply voltage input to drive the LCD.
V0,V12, output Bias voltage divided by the resistance is
I Power
V43,V5 voltage usually used as a supply voltage source (refer
level to NOTE 2).
Display data output pin which corresponds to
the respective latch contents. One of V0, V12,
LCD driver V34 and V5 is selected as a display driving
SC1~SC80 O LCD
output voltage source according to the combination of
the latched data level and M signal (refer to
NOTE 1).
Clock pulse input for the bi-directional shift
register.
– In segment driver application mode, the data
is shifted to 20 x4-bit segment data shift. The
clock pulse, which was input when the enable
Data shift bit (ELB/ERB) is in not active condition, is
CL2 I Controller
clock invalid.
– In common driver application mode, the
data is shifted to 80-bit common data
bi-directional shift register by the CL1 clock.
Hence, this clock pin is not used (Open or
connect this pin to VDD).
AC signal
Alternate signal input pin for LCD driving.
for LCD
M I Normal frame inversion signal is input in to Controller
driver
this pin.
output
– In segment driver application mode, this
signal is used for latching the shift register
contents at the falling edge of this clock pulse.
Data latch
CL1 I CL1 pulse "High" level initializes power-down Controller
clock
function block.
– In common driver application mode, CL1 is
used as a shifting clock of common output data.

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Neotec Semiconductor Ltd.

新德科技股份有限公司

NT7086PQ
LCD Driver
Version 1.0

PIN DESCRIPTION (CONTINUED)

PIN I/O NAME FUNCTION INTERFACE
Control input pin to fix the driver output
(SC1~SC80) to V0 level, during "Low" value
Display
DISPOFFB I input. LCD becomes non-selected by V0 level Controller
OFF control
output from every output of segment drivers
and every output of common drivers.
When CS = "Low", NT7086PQ is used as an
COM / SEG
80-bit segment driver.
CS I mode VDD/VSS
When CS = "High", NT7086PQ is set to an
control
80-bit common driver
According to the input value of the AMS and the
CS pin, application mode of NT7086PQ is
differs as shown below.

CS AMS Application mode COM/SEG

4-bit parallel
0 0
Application interface mode
AMS I SEG VDD/VSS
mode select 1-bit serial interface
0 1
mode
Single type
1 0
application Mode
COM
Dual type application
1 1
mode

-In segment driver mode, these pins are used as

4-bit data input pin (when 4-bit parallel
interface mode AMS= ”low”), or D1_SID is
used as serial data input pin and other pins are
not used (connect these to VDD) (when 1-bit
Display data
serial interface mode AMS= ”high”).
D1_SID, input/ serial
-In common driver mode, the data is shifted
D2_DL, input data/
I/O from D2_DL (D4_DR) to D4_DR (D2_DL), Controller
D3_DM, left , right
when in single interface mode (AMS= ”Low”).
D4_DR data input
In dual-type application case, the data are
output
shifted from D2_DL and D3_DM (D4_DR and
D3_DM) to D4_DR(D2_DL). In each case the
direction of the data shift and the connection of
data pins are determined by SHL input (refer to
NOTE 3, NOT 4).

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Neotec Semiconductor Ltd.

新德科技股份有限公司

NT7086PQ
LCD Driver
Version 1.0

PIN DESCRIPTION (CONTINUED)

PIN I/O NAME FUNCTION INTERFACE
When SHL = "Low", data is shifted from left to
Shift
right.
SHL I direction
When SHL = "High", the direction is reversed.
control
(refer to NOTE3)
-In segment driver mode, the internal operation
is enabled only when enable input (ELB or
ERB) is "Low" (power down function). When
several drivers a serially connected, the enable
state of each driver is shifted according to the
VDD/VSS
SHL input. Connect these pins as below.
Enable data
ELB, ERB I/O input/
Segment driver
output SHL
ELB ERB
L Output (open) Input (VSS)
H Input (VSS) Output(open)

-In common driver mode, the power down

function is not used. Open these pins.

NOTE 1. Output level control "X": don't care

Output level (CS1~CS80)
M Latched data DISPOFFB
SEG Mode COM Mode
L L H V12(V2) V12(V1)
L H H V0 V5
H L H V43(V3) V43(V4)
H H H V5 V0
X X L V0 V0

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Neotec Semiconductor Ltd.

新德科技股份有限公司

NT7086PQ
LCD Driver
Version 1.0

NOTE 2. LCD Driving Voltage Application Circuit

(1) Segment driver application (CS = “Low”)

(2) Common driver application (CS = “High”)

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Neotec Semiconductor Ltd.

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NT7086PQ
LCD Driver
Version 1.0

NOTE 3. Data Shift Direction according to Control Signals

(1) When CS = “Low” (segment driver application)
Application
AMS SHL Data Direction Input pin
mode
S S S S S S S S
S S S S C C C C C C C C
C C C C 7 7 7 7 7 7 7 8
........ 3 4 5 6 7 8 9 0
1 2 3 4

D D D D ........ D D D D D D D D
L 1 2 3 4 1 2 3 4 1 2 3 4

D1 Shift direction
4-bit D2
D3 Last data Frist data
parallel D4 D1_SID,
data D2_DL,
L
transfer S S S S S S S S D3_DM,
mode S S S S C C C C C C C C D4_DR
C C C C 7 7 7 7 7 7 7 8
(SEG) 1 2 3 4
........ 3 4 5 6 7 8 9 0

D D D D ........ D D D D D D D D
H 4 3 2 1 4 3 2 1 4 3 2 1

Shift direction D1
D2
Frist data D3 Last data
D4

S S S S S S S S
S S S S
C C C C ........ C C C C C C C C
7 7 7 7 7 7 7 8
1 2 3 4
L 3 4 5 6 7 8 9 0

1-bit serial Shift direction

data Last data (D1_SID) Frist data
H transfer D1_SID
mode S S S S S S S S
S S S S
(SEG) C C C C . . . . . . . . C C C C C C C C
7 7 7 7 7 7 7 8
1 2 3 4
H 3 4 5 6 7 8 9 0

Shift direction
Frist data Last data

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Neotec Semiconductor Ltd.

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NT7086PQ
LCD Driver
Version 1.0

(2) When CS = “High” (common driver application)

Application
AMS SHL Data Direction Input pin
mode
..... .....
S S S S S S S S S
S S S
C C C C C C C C C
C C C
3 3 4 4 4 4 7 7 8
1 2 3
..... 8 9 0 1 2 3 ..... 8 9 0
L D2_DL
Shift direction

Input data Output data

Single-type (D2_DL) (D4_DR)
Application
L
mode ..... .....
S S S S S S S S S
(COM) S S S
C C C C C C C C C
C C C
3 3 4 4 4 4 7 7 8
1 2 3
..... 8 9 0 1 2 3 ..... 8 9 0
H D4_DR
Shift direction

Output data Input data

(D2_DL) (D4_DR)

Shift direction
..... .....
S S S S S S S S S
S S S
C C C C C C C C C
C C C
3 3 4 4 4 4 7 7 8
1 2 3 D2_DL,
L ..... 8 9 0 1 2 3 ..... 8 9 0
D3_DM

Input data 1 Input data 2 Output data

Dual-type (D2_DL) (D3_DM) (D4_DR)
Application
H
mode
Shift direction
(COM)
..... .....
S S S S S S S S S
S S S
C C C C C C C C C
C C C
3 3 4 4 4 4 7 7 8
1 2 3 D4_DR,
H ..... 8 9 0 1 2 3 ..... 8 9 0
D3_DM

Output data Input data 2 Input data 1

(D2_DL) (D3_DM) (D4_DR)

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Neotec Semiconductor Ltd.

新德科技股份有限公司

NT7086PQ
LCD Driver
Version 1.0

NOTE 4. Usage of Data Pins

COM / Data interface pin

Application mode
SEG SHL
(AMS pin) D1_SID D2_DL D3_DM D4_DR
(CS pin)
4-bit parallel interface
SEG X D1 (input) D2 (input) D3 (input) D4(input)
mode (AMS = “Low”)
(CS
1-bit serial interface mode
=”Low”) X SID (input) Connect to VDD
(AMS = “High”)
single-type application L DL (input) Open DR (output)
open
COM mode (AMS = “Low”) H DL (output) DR (input)
(CS DM
L DL (input1) DR (output2)
=”High” dual-type application mode (input2)
open
) (AMS = “High”) DL (output2) DM
H DR (input1)
(input2)

MAXIMUM ABSOLUTE LIMIT

Characteristic Symbol Value Unit

Power supply voltage VDD -0.3~+7.0
Driver supply voltage VLCD 0~+30 V
Input voltage VIN -0.3~VDD+0.3
Operating temperature Topr -30~+85
℃
Storage temperature Tstg -55~+150
NOTE: Voltage greater than above may do damage to the circuit.

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Neotec Semiconductor Ltd.

新德科技股份有限公司

NT7086PQ
LCD Driver
Version 1.0

ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS
(1) Segment Driver Application
(VSS = 0V, Ta = - 30 ~ +85°C)
Characteristic Symbol Test Condition Min. Typ. Max. Unit
Operating VDD - 2.7 - 5.5
Voltage 1 VLCD VIN=VDD-VEE 6 - 28
V
VIH - 0.8VDD - VDD
Input voltage (1)
VIL - 0 - 0.2VDD
VOH ICH=-0.4mA VDD-0.4 - -
Input voltage (2) V
VOL IOH=-0.4mA - - 0.4
Input leakage
IIL1 VIN=VDD to VSS -10 - 10
current 1 (1)
μA
Input leakage
IIL2 VIN=VDD to VEE -25 - 25
current 2 (3)
On resistance(4) RON ION=100μA - 2 4 kΩ
ISTBY fCL1=32kHZ, M=VSS VSS PIN - - 100 μA
Supply VDD=5V - - 5
IDD mA
current(5) fCL1=32kHZ FM=80HZ VDD=3V - - 2
IEE VDD=5V - - 500 μA
NOTES:
1. Applied to CL1, CL2, ELB, ERB, D1_SID - D4_DR, SHL, DISPOFFB, M, CS, AMS pin
2. ELB, ERB pin
3. V0, V12, V43, V5 pin
4. VLCD = VDD - VEE, V0 = VDD = 5V, V5= VEE = -23 V
V12 = VDD-2/n(VLCD), V43 = VEE+2/n(VLCD), n = 17 (1/256 duty, 1/17 bias)
5. V0 = VDD, V12 = 1.71V(VDD = 5V) or -0.06V (VDD = 3V),
V43 = -19.71 V(VDD = 5V) or -19.94V (VDD = 3V), V5 = VEE = -23V, no-load condition (1/256 duty, 1/17 bias)
4-bit parallel interface mode
ISTBY : VDD = 5V, fCL2 = 5.12MHz, SHL = VSS, DISPOFFB = VDD, M = VSS, display data pattern = 0000
IDD : VDD = 3V, fCL2 = 4MHz, display data pattern = 0101
VDD = 5 V, fCL2 = 5.12MHz, display data pattern = 0101
IEE : VDD = 5V, fCL2 = 5.12MHz, display data pattern = 0101, VEE pin

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Neotec Semiconductor Ltd.

新德科技股份有限公司

NT7086PQ
LCD Driver
Version 1.0

DC CHARACTERISTICS (CONTINUED)
(2) Common Driver Application
(VSS = 0V, Ta = - 30 ~ +85°C)
Characteristic Symbol Test Condition Min. Typ. Max. Unit
Operating VDD - 2.7 - 5.5
Voltage 1 VLCD VIN=VDD-VEE 6 - 28
V
VIH - 0.8VDD - VDD
Input voltage (1)
VIL - 0 - 0.2VDD
VOH ICH=-0.4mA VDD-0.4 - -
Input voltage (3) V
VOL IOH=-0.4mA - - 0.4
Input leakage
IIL1 VIN=VDD to VSS -10 - 10
current 1 (1)
μA
Input leakage
IIL2 VIN=0V, VDD=5V(Pull up) -50 -125 -250
current 2 (2)
Input leakage
IIL3 VIN=VDD to VEE -25 - 25
current 3 (4)
On resistance(5) RON ION=100μA - 2 4 kΩ
ISTBY fCL1=32kHZ, M=VSS VSS PIN - - 100
Supply VDD=5V - - 200
IDD μA
current(6) fCL1=32kHZ FM=80HZ VDD=3V - - 120
IEE VDD=5V - - 150
NOTES:
1. Applied to CL1, D2_DL (SHL = LOW), D4_DR (SHL = HIGH), SHL, DISPOFFB, M, CS, AMS pin
2. Pull-up input pins : CL2, D1_SID, D3_DM (AMS = HIGH), ELB (SHL = LOW), ERB (SHL = HIGH)
3. D2_DL (SHL = HIGH) , D4_DR (SHL = LOW) pin
4. V0, V12, V43, V5 pin
5. VLCD = VDD-VEE, V0 = VDD = 5V, V5 = VEE = -23V
V12 = VDD-1/n(VLCD), V43 = VEE+1/n(VLCD), n = 17(1/256 duty, 1/17 bias)
6. V0 = VDD, V12 = 3.35V (VDD = 5V) or 1.47V (VDD = 3V),
V43 = -21.35V (VDD = 5 V) or -21.47V (VDD = 3 V), V5 = VEE = -23 V, no-load condition (1/256 duty, 1/17 bias)
single-type mode operation : AMS = VSS, SHL = VSS, DISPOFFB = VDD
D1_SID = D3_DM = VDD, D4_DR = OPEN, ELB = ERB = OPEN,
ISTBY : VDD = 5V, M = VSS, D2_DL = VSS
IDD : fM = 80Hz, D2_DL = VDD
VDD = 3 V, display data pattern = 10000000..., 01000000..., 00100000..., 00010000..., ..
VDD = 5 V, display data pattern = 10000000..., 01000000..., 00100000..., 00010000..., ..
IEE : fM = 80Hz, D2_DL = VDD
VDD = 5V, current through VEE Pin, display data pattern = 10000000..., 01000000...,
00100000..., 00010000...

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Neotec Semiconductor Ltd.

新德科技股份有限公司

NT7086PQ
LCD Driver
Version 1.0

AC CHARACTERISTICS
(1) Segment Driver Application
(VSS = 0V, Ta = - 30 ~ +85°C)
(1) VDD=5V±10% (2) VDD=3V±10%
Characteristic Symbol Test condition Unit
Min. Typ. Max. Min. Typ. Max.
Clock cycle time tCY Duty=50% 125 - - 250 - -
Clock pulse width tWCK - 45 - - 95 - -
Clock rise/ fall time tR / tF - - - - - - 30
Data set-up time tDS - 30 - 65 - -
Data hold time tDH - 30 - 65 - -
Clock set-up time tCS - 80 - 120 - - ns
Clock hold time tCH - 80 - 120 - -
ELB output 60 125
Propagation delay time tPHL - - - -
ERB output 60 125
ELB input 30 65
ELB,ERB set-up time tPSU - - - -
ERB input 30 65
DISPOFFB low pulse
tWDL - 1.2 - - 1.2 - - μs
width
DISPOFFB clear time tCD - 100 - - 100 - - ns
M – OUT
tPD1 - - 1.0 - - 1.2
propagation delay time
CL1 – OUT
tPD2 CL=15pF - - 1.0 - - 1.2 μs
propagation delay time
DISPOFFB – OUT
tPD3 - - 1.0 - - -
propagation delay time

(2) Common Driver Application

(VSS = 0V, Ta = - 30 ~ +85°C)
(1) VDD=5V±10% (2) VDD=3V±10%
Characteristic Symbol Test condition Unit
Min. Typ. Max. Min. Typ. Max.
Clock cycle time tCY Duty=50% 250 - - 500 - -
Clock pulse width tWCK - 45 - - 95 - -
Clock rise/ fall time tR / tF - - - 50 - - 50 ns
Data set-up time tDS - 30 - 65 - -
Data hold time TDH - 30 - 65 - -
DISPOFFB low pulse
tWDL - 1.2 - - 1.2 - - μs
width
DISPOFFB clear time tCD - 100 - - 100 - -
ns
Output delay time tDL - - 200 - - 250
M – OUT
tPD1 - - 1.0 - - 1.2
propagation delay time
CL1 – OUT CL=15pF
tPD2 - - 1.0 - - 1.2 μs
propagation delay time
DISPOFFB – OUT
tPD3 - - 1.0 - - 1.2
propagation delay time

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Neotec Semiconductor Ltd.

新德科技股份有限公司

NT7086PQ
LCD Driver
Version 1.0

(3) Segment Driver Application Timing

0.8VDD tWCK 0.8VDD

CL1 0.2VDD 0.2VDD
tCS
tCH
tWCK
0.8VDD 0.8VDD 0.8VDD
CL2 0.2VDD tWCK 0.2VDD 0.2VDD
tR tF
tCY tDS tDH
0.8VDD
D1_SID - D4_DR 0.2VDD
tCD
tWDL
DISPOFFB

CL1
1 2 3 19 20
0.8VDD
CL2
0.2VDD
tPHL
ELB, ERB
(Output 1) 0.2VDD
ELB, ERB tPSU
(Input 2) 0.2VDD

0.8VDD
M
0.2VDD
tPD1
CL1 tPD2
0.2VDD

0.8VDD
DISPOFFB
0.2VDD
tPD3

SC1 - SC80
(Latched data)

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Neotec Semiconductor Ltd.

新德科技股份有限公司

NT7086PQ
LCD Driver
Version 1.0

(4) Common Driver Application Timing

tCY
0.8VDD 0.8VDD
CL1 tDWCKH
0.2VDD 0.2VDD
tR tF tF
tDS tDH

0.8VDD 0.8VDD
(*1) DI 0.2VDD 0.2VDD
tDL

0.8VDD
(*1) DO 0.2VDD
tCD
tWDL

DISPOFFB

(*1) When in single-type interface mode

DI=>DDL(SHL=L), D4_DR(SHL=H)
DO=>D4_DR(SHL=L), D2_DL(SHL=H)
When in dual-type interface mode
DI=>D2_DL and D3_DM(SHL=L),D4_DR and D3_DM(SHL=H)
DO=>D4_DR(SHL=L), D2_DL(SHL=H)

0.8VDD
M 0.2VDD
tPD1
tPD2
CL1
0.2VDD
0.8VDD
DISPOFFB 0.2VDD
tPD3
SC1 - SC80
(Latched data)

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Neotec Semiconductor Ltd.

新德科技股份有限公司

NT7086PQ
LCD Driver
Version 1.0

POWER DOWN FUNCTION

In the case of cascade connection of segment mode drivers, NT7086PQ has a "power down function" In
order to reduce the power consumption.

SHL Enable input Enable output Current driver status The other drivers status
While ERB ="Low",
L ERB ELB Disabled
current driver is enabled.
While ELB ="Low",
H ELB ERB Disabled
current driver is enabled.

* In the case of common driver application, power down function does not work.

CL1
1 2 n-1 n 1 2 n-1 n 1 2 n-1 n 1 2 n-1 n 1 2 n-1
CL2
ELB1(input1)

ERB1/ELB2
(Output1/Input2)
ERB2/ELB3
(Output2/Input3)
ERB3/ELB4
(Output3/Input4)
ELB4(Output)

NOTES:
1. SHL = High (ELB = Input, ERB = Output)
2. When in 4-bit parallel interface mode: n = 20
When in 1-bit serial interface mode: n = 80

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Neotec Semiconductor Ltd.

新德科技股份有限公司

NT7086PQ
LCD Driver
Version 1.0

OPERATION TIMING DIAGRAM

(1) 4-bit parallel mode interface segment driver

When SHL= ”Low”

19 20 1 2 3 19 20 1 2
CL2

D1_SID SC5 SC1 SC77 SC73 SC69 SC5 SC1 SC77 SC73
D2_DL SC6 SC2 SC78 SC74 SC70 SC6 SC2 SC78 SC74
D3_DM SC7 SC3 SC79 SC75 SC71 SC7 SC3 SC79 SC75
D4_DR SC8 SC4 SC80 SC76 SC72 SC8 SC4 SC80 SC76
ERB(Input)
ELB(Onput)
CL1

SC1 - SC80

When SHL= ”High”

19 20 1 2 3 19 20 1 2
CL2

D1_SID SC76 SC80 SC4 SC8 SC12 SC76 SC80 SC4 SC8
D2_DL SC75 SC79 SC3 SC7 SC11 SC75 SC79 SC3 SC7
D3_DM SC74 SC78 SC2 SC6 SC10 SC74 SC78 SC2 SC6
D4_DR SC73 SC77 SC1 SC5 SC9 SC73 SC77 SC1 SC5
ELB(Input)
ERB(Onput)
CL1

SC1 - SC80

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Neotec Semiconductor Ltd.

新德科技股份有限公司

NT7086PQ
LCD Driver
Version 1.0

(2) 1-bit serial mode interface segment driver

When SHL= ”Low”

79 80 1 2 3 79 80 1 2
CL2

D1_SID SC2 SC1 SC80 SC79 SC78 SC2 SC1 SC80 SC79
ERB(Input)
ELB(Onput)
CL1

SC1 - SC80

When SHL= “High”

79 80 1 2 3 79 80 1 2
CL2

D1_SID SC79 SC80 SC1 SC2 SC3 SC79 SC80 SC1 SC2
ELB(Input)
ERB(Onput)
CL1

SC1 - SC80

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Neotec Semiconductor Ltd.

新德科技股份有限公司

NT7086PQ
LCD Driver
Version 1.0

(3) Single type interface mode common driver

When SHL= “Low”

79 80 1 2 79 80 1 2
CL1
D2_DL
D4_DR
COM_DATA1
COM_DATA2
COM_DATA3
COM_DATA79
COM_DATA80
Current Driver's COMMON area
When SHL= ”High”

79 80 1 2 79 80 1 2
CL1
D4_DR
D2_DL
COM_DATA1
COM_DATA2
COM_DATA3
COM_DATA79
COM_DATA80
Current Driver's COMMON area

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Neotec Semiconductor Ltd.

新德科技股份有限公司

NT7086PQ
LCD Driver
Version 1.0

(4) Dual-type interface mode common driver

When SHL= “Low”

1 2 3 39 40 1 2 3 39 40
CL1

D2_DL

D3_DM

D4_DR

COM_DATA1

COM_DATA2

COM_DATA3

COM_DATA39

COM_DATA40

COM_DATA41

COM_DATA42

COM_DATA43

COM_DATA79

COM_DATA80

When SHL= “High”

1 2 3 39 40 1 2 3 39 40
CL1

D2_DL

D3_DM

D4_DR

COM_DATA1

COM_DATA2

COM_DATA3

COM_DATA39

COM_DATA40

COM_DATA41

COM_DATA42

COM_DATA43

COM_DATA79

COM_DATA80

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2005/11/28
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Neotec Semiconductor Ltd.

新德科技股份有限公司

NT7086PQ
LCD Driver
Version 1.0

(5) Common / Segment driver timing (1/200 duty)

199 200 1 200 1 199 200 1 199 200

CL1
Latched data (SEG)
M
COM_DATA1
COM_DATA199
COM_DATA200
V0
V1
COM1
V4
V5

V0
V1
COM199
V4
V5
V0
V1
COM200
V4
V5

SEG_DATA1

V0
V1
SEG1 V2
V3
V4
V5

1 2 18 19 20 1
CL2
CL1
D1 - D4
Latched data
M
Enable Out

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2005/11/28
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Neotec Semiconductor Ltd.

新德科技股份有限公司

NT7086PQ
LCD Driver
Version 1.0

APPLICATION INFORMATION

1-bit serial interface mode (80 Ch. Segment mode)

a) Lower view (SHL= L, AMS= H)

b) Upper view (SHL= H, AMS= H)

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Neotec Semiconductor Ltd.

新德科技股份有限公司

NT7086PQ
LCD Driver
Version 1.0

4-bit parallel interface mode (80 Ch. Segment driver)

a) Lower view (SHL= L, AMS = L)

b) Upper view (SHL= H, AMS = L)

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Neotec Semiconductor Ltd.

新德科技股份有限公司

NT7086PQ
LCD Driver
Version 1.0

Single type interface mode (80 Ch. Common driver)

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Neotec Semiconductor Ltd.

新德科技股份有限公司

NT7086PQ
LCD Driver
Version 1.0

Dual-type interface mode (40 Ch. + 40Ch. Common driver)

NOTE: Using this application mode (dual-type common mode), the duty ratio can be reduced to half. In case,
1/200 duty can be used to driver the 400 common LCD panel.

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Neotec Semiconductor Ltd.

新德科技股份有限公司

NT7086PQ
LCD Driver
Version 1.0

APPLICATION CIRCUIT EXAMPLE

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2005/11/28
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Neotec Semiconductor Ltd.

新德科技股份有限公司

NT7086PQ
LCD Driver
Version 1.0

PRECAUTIONS
Precautions when connecting or disconnecting the power supply
This IC has a high-voltage LCD driver, so it may be permanently damaged by a high current which may
flow if voltage is supplied to the LCD drive power supply while the logic system power supply is floating. The
details are as follows.

When connecting the power supply, connect the LCD drive power after connecting the
logic system power. Furthermore, when disconnecting the power, disconnect the logic
system power after disconnecting the LCD drive power.

And when connecting the logic power supply, the logic condition of this IC inside is insecure. Therefore
connect the LCD drive power supply after resetting logic condition of this IC inside on /DISPOFF function.
After that, cancel the /DISPOFF function after the LCD drive power supply has become stable. Furthermore,
when disconnecting the power, set the LCD drive output pins to level V5 on /DISPOFF function. Then,
disconnect the logic system power after disconnecting the LCD drive power.
When connecting the power supply, follow the recommended sequence shown here.

VDD
VDD
VSS

VDD
/DISPOFF
VSS

VSS
VEE
VEE

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