TOP LEVEL CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity TopLevel is
port (
kelvin: in std_logic;
HexDec: in std_logic;
SystemClock: in std_logic;
ClockOut: out std_logic;
Power: out std_logic;
CS: out std_logic;
MISO: in std_logic;
An: out std_logic_vector (5 downto 0);
Ca, Cb, Cc, Cd, Ce, Cf, Cg: out std_logic;
SFD: out std_logic_vector (3 downto 0);
LCDE, LCDRS, LCDRW: out std_logic);
end TopLevel;

architecture Behavioral of TopLevel is

component PULLDOWN
port ( O : out std_ulogic);
end component;

component Max6675
port ( SystemClock: in std_logic;
ClockOut: out std_logic;
Power: out std_logic;
MISO: in std_logic;
DataOut: out std_logic_vector (15 downto 0);
CS: out std_logic);
end component;

--component D4to7
-- port ( Q: in std_logic_vector (3 downto 0);
-- Seg: out std_logic_vector (6 downto 0));
--end component;

component Converter
port ( kelvin: in std_logic;
Hexdec : in std_logic;
q : in STD_LOGIC_VECTOR (15 downto 0);
seg1 : out STD_LOGIC_VECTOR (6 downto 0);
seg2 : out STD_LOGIC_VECTOR (6 downto 0);

1
 seg3 : out STD_LOGIC_VECTOR (6 downto 0);
seg4 : out STD_LOGIC_VECTOR (6 downto 0);
seg5 : out STD_LOGIC_VECTOR (6 downto 0);
seg6 : out STD_LOGIC_VECTOR (6 downto 0);
lcd1 : out STD_LOGIC_VECTOR (3 downto 0);
lcd2 : out STD_LOGIC_VECTOR (3 downto 0);
lcd3 : out STD_LOGIC_VECTOR (3 downto 0);
lcd4 : out STD_LOGIC_VECTOR (3 downto 0));
end component;

component Scan4Digit
port ( Digit5, Digit4, Digit3, Digit2, Digit1, Digit0: in std_logic_vector(6 downto 0);
Clock: in std_logic; An : out std_logic_vector(5 downto 0);
Ca, Cb, Cc, Cd, Ce, Cf, Cg: out std_logic);
end component;

component LCD
port ( SystemClock: in std_logic;
lcd1: in STD_LOGIC_VECTOR (3 downto 0);
lcd2: in STD_LOGIC_VECTOR (3 downto 0);
lcd3: in STD_LOGIC_VECTOR (3 downto 0);
lcd4: in STD_LOGIC_VECTOR (3 downto 0);
LCDE : out std_logic;
LCDRS : out std_logic;
LCDRW : out std_logic;
SFD : out std_logic_vector (3 downto 0));
end component;

signal iClock1m: std_logic;

signal iClock16x: std_logic;
--signal iClockOut : std_logic;
signal iDigitOut5, iDigitOut4, iDigitOut3, iDigitOut2, iDigitOut1, iDigitOut0: std_logic_vector (6 downto 0);
signal iDataOut: std_logic_vector (15 downto 0);
--signal iMISO: std_logic_vector (15 downto 0);
signal iCount9: std_logic_vector (23 downto 0);
signal iCount: std_logic_vector (8 downto 0);
signal Clock123: std_logic;
signal itlcd1, itlcd2, itlcd3, itlcd4: std_logic_vector (3 downto 0);

begin

--process (SystemClock)
-- begin
-- if rising_edge(SystemClock) then
-- if
-- iCount9 = "101001111101100011000000" then -- the divider is 11000000
-- iCount9 <= (others=>'0');
-- Clock123 <=
-- else iCount9 <= iCount9 + '1';
-- end if;
-- end if;
--

2
-- if rising_edge(SystemClock) then
-- if
-- iCount = "101000101" then -- the divider is 325, or "101000101"
-- iCount <= (others=>'0');
-- else iCount <= iCount + '1';
-- end if;
-- end if;
--end process;

--iClock1m <= iCount9(23);

--iClock16x <= iCount(8);
--iClock1m <= SystemClock;

U1: Max6675 port map ( --Clock1m => iClock1m,

--Clock16x => iClock16x,
SystemClock => SystemClock,
ClockOut => ClockOut,
Power => Power,
MISO => MISO,
DataOut => iDataOut,
CS => CS);

--U2: D4to7 port map (

-- Q => iDataOut(3 downto 0),
-- Seg => iDigitOut0);
--
--U3: D4to7 port map (
-- Q => iDataOut(7 downto 4),
-- Seg => iDigitOut1);
--
--U4: D4to7 port map (
-- Q => iDataOut(11 downto 8),
-- Seg => iDigitOut2);
--
--U5: D4to7 port map (
-- Q => iDataOut(15 downto 12),
-- Seg => iDigitOut3);

U2: Converter port map (

kelvin => kelvin,
Hexdec => Hexdec,
q => iDataOut,
seg1 => iDigitOut0,
seg2 => iDigitOut1,
seg3 => iDigitOut2,
seg4 => iDigitOut3,
seg5 => iDigitOut4,
seg6 => iDigitOut5,
lcd1 => itlcd1,
lcd2 => itlcd2,
lcd3 => itlcd3,
lcd4 => itlcd4);

3
U3: scan4digit port map (
Digit5 => iDigitOut5,
Digit4 => iDigitOut4,
Digit3 => iDigitOut3,
Digit2 => iDigitOut2,
Digit1 => iDigitOut1,
Digit0 => iDigitOut0,
Clock => SystemClock,
An => An,
Ca => Ca,
Cb => Cb,
Cc => Cc,
Cd => Cd,
Ce => Ce,
Cf => Cf,
Cg => Cg);

U4: LCD port map (

SystemClock => SystemClock,
lcd1 => itlcd1,
lcd2 => itlcd2,
lcd3 => itlcd3,
lcd4 => itlcd4,
LCDE => LCDE,
LCDRS => LCDRS,
LCDRW => LCDRW,
SFD => SFD);

end Behavioral;

MAX 6675

entity Max6675 is
port ( SystemClock, MISO: in std_logic;
ClockOut: out std_logic;
Power: out std_logic;
DataOut: out std_logic_vector (15 downto 0);
CS: out std_logic);
end Max6675;

architecture Behavioral of Max6675 is

attribute enum_encoding: string;
-- state definitions
type stateType is (stIdle, stData, stStop, stRxdCompleted);
attribute enum_encoding of statetype: type is "00 01 11 10";

signal presState: stateType;

signal nextState: stateType;
signal iReset: std_logic;
signal iCS: std_logic;
signal iCSEnable: std_logic;
signal iSClkEnable: std_logic;

4
 signal iClkDiv: std_logic_vector (3 downto 0);
signal iSClk: std_logic;
signal NoBits: std_logic_vector (3 downto 0);
signal iEnableDataOut: std_logic;
signal iDataOut: std_logic_vector (15 downto 0);
signal iShiftRegister: std_logic_vector (15 downto 0);
signal iCount9: std_logic_vector (23 downto 0);

begin

Power <= '1';

--CS Clock
--process (Clock1m, iReset)
--begin
-- if Clock1m'event and Clock1m = '0' then
-- iCS <= '0';
-- elsif Clock1m'event and Clock1m = '0' then
-- iCS<= '1';
-- end if;
-- end if;
--end process;

--CS <= Clock1m;

--process (Clock16x, Clock1m)

--begin
-- if Clock16x'event and Clock16x = '0' then
-- if Clock1m = '0' then
-- iClkDiv <= iClkDiv +'1';
-- else
-- iClkDiv <= (others=>'0');
-- end if;
-- end if;
--end process;
--
--
--iSClk <= iClkDiv(3);
--ClockOut <= iSClk;

process (SystemClock, iReset)

begin
if SystemClock'event and SystemClock = '1' then

iCount9 <= iCount9 + '1';

if iCS = '1' then
iCS <= '1';
iCSEnable <= '0';
else
iCS <= '0';

5
 iCSEnable <= '1';
end if;

if iCount9 = "101001111101100011000000" then -- the divider is 11000000

--iCount9 <= (others=>'0');
iCS <= '0';
iCSEnable <= '1';
end if;

if iReset = '1' and iCS = '0' then

iCount9 <= (others=>'0');
iCS <= '1';
iCSEnable <= '0';
end if;

if iCSEnable = '1' then

iClkDiv <= iClkDiv +'1';
else
iClkDiv <= (others=>'0');
end if;
end if;
end process;

CS <= iCS;

--process (Clock1m)
--begin
-- if rising_edge(Clock1m) then
--
-- end if;
--end process;

iSClk <= iClkDiv(3);

ClockOut <= iSClk;
--SClk Clock
process (iCS, iSClk)
begin
if iCSEnable = '0' then
NoBits <= (others=>'0');
presState <= stIdle;
elsif iSClk'event and iSClk = '0' then
NoBits <= NoBits + '1';
presState <= nextState;
end if;

if iSClk'event and iSClk = '0' then

if iEnableDataOut = '1' then
iDataOut <= '0' & '0' & '0' & '0' & iShiftRegister(14 downto 3);
else
iShiftRegister <= iShiftRegister(14 downto 0) & MISO;
end if;
end if;

6
end process;

DataOut <= iDataOut;

process (presState, iCSEnable, NoBits)

begin
-- signal defaults
iReset <= '0';
iEnableDataOut <= '0';

case presState is
when stIdle =>
if iCSEnable = '1' then
nextState <= stData;
else
nextState <= stIdle;
end if;
when stData =>
if NoBits = "1110" then
iEnableDataOut <= '1';
nextState <= stStop;
else
iEnableDataOut <= '0';
nextState <= stData;
end if;
when stStop =>
nextState <= stRxdCompleted;
when stRxdCompleted =>
iReset <= '1';
nextState <= stIdle;
end case;
end process;

end Behavioral;

CONVERTER

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Converter is
Port ( --hexdec : in std_logic;
kelvin: in std_logic;
Hexdec: in std_logic;
q : in STD_LOGIC_VECTOR (15 downto 0);

7
seg1 : out STD_LOGIC_VECTOR (6 downto 0);
seg2 : out STD_LOGIC_VECTOR (6 downto 0);
seg3 : out STD_LOGIC_VECTOR (6 downto 0);
seg4 : out STD_LOGIC_VECTOR (6 downto 0);
seg5 : out STD_LOGIC_VECTOR (6 downto 0);
seg6 : out STD_LOGIC_VECTOR (6 downto 0);
lcd1: out STD_LOGIC_VECTOR (3 downto 0);
lcd2: out STD_LOGIC_VECTOR (3 downto 0);
lcd3: out STD_LOGIC_VECTOR (3 downto 0);
lcd4: out STD_LOGIC_VECTOR (3 downto 0));
end Converter;

architecture Behavioral of Converter is

signal d1: std_logic_vector (3 downto 0);

signal d2: std_logic_vector (3 downto 0);
signal d3: std_logic_vector (3 downto 0);
signal d4: std_logic_vector (3 downto 0);
--signal d5: std_logic_vector (4 downto 0);
--signal d6: std_logic_vector (4 downto 0);
signal biseg3, biseg4, biseg5, biseg6 : STD_LOGIC_VECTOR (6 downto 0);
signal iseg1, iseg2, iseg3, iseg4, iseg5, iseg6 : STD_LOGIC_VECTOR (6 downto 0);
signal decseg3, decseg4, decseg5, decseg6 : STD_LOGIC_VECTOR (6 downto 0);
signal kelseg3, kelseg4, kelseg5, kelseg6 : STD_LOGIC_VECTOR (6 downto 0);
signal deci, deci1, deci2, kelvin0, kelvin1, kelvin2, kelvinh2, kelvin3: Integer;
signal c1, c2, c3, c4 : STD_LOGIC_VECTOR (3 downto 0);
signal k1, k2, k3, k4 : STD_LOGIC_VECTOR (3 downto 0);
signal ilcd1, ilcd2, ilcd3, ilcd4 : STD_LOGIC_VECTOR (3 downto 0);

begin

deci <= conv_integer(q);

d1 <= q(3 downto 0);
d2 <= q(7 downto 4);
d3 <= q(11 downto 8);
d4 <= q(15 downto 12);
kelvin0 <= deci + 273;

biSeg3 <= "1111110" when d1 = "00000" else

"0110000" when d1 = "000001" else
"1101101" when d1 = "000010" else
"1111001" when d1 = "00011" else
"0110011" when d1 = "00100" else
"1011011" when d1 = "00101" else
"1011111" when d1 = "00110" else
"1110000" when d1 = "00111" else
"1111111" when d1 = "01000" else
"1111011" when d1 = "01001" else
"1110111" when d1 = "01010" else
"0011111" when d1 = "01011" else
"1001110" when d1 = "01100" else
"0111101" when d1 = "01101" else
"1001111" when d1 = "01110" else

8
 "1000111" when d1 = "01111" else
"0000000";

biSeg4 <= "1111110" when d2 = "00000" else

"0110000" when d2 = "000001" else
"1101101" when d2 = "000010" else
"1111001" when d2 = "00011" else
"0110011" when d2 = "00100" else
"1011011" when d2 = "00101" else
"1011111" when d2 = "00110" else
"1110000" when d2 = "00111" else
"1111111" when d2 = "01000" else
"1111011" when d2 = "01001" else
"1110111" when d2 = "01010" else
"0011111" when d2 = "01011" else
"1001110" when d2 = "01100" else
"0111101" when d2 = "01101" else
"1001111" when d2 = "01110" else
"1000111" when d2 = "01111" else
"0000000";

biSeg5 <= "1111110" when d3 = "00000" else

"0110000" when d3 = "000001" else
"1101101" when d3 = "000010" else
"1111001" when d3 = "00011" else
"0110011" when d3 = "00100" else
"1011011" when d3 = "00101" else
"1011111" when d3 = "00110" else
"1110000" when d3 = "00111" else
"1111111" when d3 = "01000" else
"1111011" when d3 = "01001" else
"1110111" when d3 = "01010" else
"0011111" when d3 = "01011" else
"1001110" when d3 = "01100" else
"0111101" when d3 = "01101" else
"1001111" when d3 = "01110" else
"1000111" when d3 = "01111" else
"0000000";

biSeg6 <= "1111110" when d4 = "00000" else

"0110000" when d4 = "000001" else
"1101101" when d4 = "000010" else
"1111001" when d4 = "00011" else
"0110011" when d4 = "00100" else
"1011011" when d4 = "00101" else
"1011111" when d4 = "00110" else
"1110000" when d4 = "00111" else
"1111111" when d4 = "01000" else
"1111011" when d4 = "01001" else
"1110111" when d4 = "01010" else
"0011111" when d4 = "01011" else
"1001110" when d4 = "01100" else

9
 "0111101" when d4 = "01101" else
"1001111" when d4 = "01110" else
"1000111" when d4 = "01111" else
"0000000";

--deci2 <= deci / 10;

--deci1 <= deci mod 10;

-- DEGREE CELCIUS --
deci2 <= 1 when deci>9 and deci<20 else
2 when deci>19 and deci<30 else
3 when deci>29 and deci<40 else
4 when deci>39 and deci<50 else
0;

deci1 <= deci - (deci2*10);

decSeg3 <= "1111110" when deci1 = 0 else

"0110000" when deci1 = 1 else
"1101101" when deci1 = 2 else
"1111001" when deci1 = 3 else
"0110011" when deci1 = 4 else
"1011011" when deci1 = 5 else
"1011111" when deci1 = 6 else
"1110000" when deci1 = 7 else
"1111111" when deci1 = 8 else
"1111011" when deci1 = 9 else
"0000000";

decSeg4 <= "1111110" when deci2 = 0 else

"0110000" when deci2 = 1 else
"1101101" when deci2 = 2 else
"1111001" when deci2 = 3 else
"0110011" when deci2 = 4 else
"1011011" when deci2 = 5 else
"1011111" when deci2 = 6 else
"1110000" when deci2 = 7 else
"1111111" when deci2 = 8 else
"1111011" when deci2 = 9 else
"0000000";

decSeg5 <= "1111110";

decSeg6 <= "1111110";

c1 <= "0000" when deci1 = 0 else

"0001" when deci1 = 1 else
"0010" when deci1 = 2 else
"0011" when deci1 = 3 else
"0100" when deci1 = 4 else
"0101" when deci1 = 5 else
"0110" when deci1 = 6 else

10
 "0111" when deci1 = 7 else
"1000" when deci1 = 8 else
"1001" when deci1 = 9 else
"0000";

c2 <= "0000" when deci2 = 0 else

"0001" when deci2 = 1 else
"0010" when deci2 = 2 else
"0011" when deci2 = 3 else
"0100" when deci2 = 4 else
"0101" when deci2 = 5 else
"0110" when deci2 = 6 else
"0111" when deci2 = 7 else
"1000" when deci2 = 8 else
"1001" when deci2 = 9 else
"0000";

c3 <= "0000";
c4 <= "0000";

-- KELVIN --
kelvin3 <= 1 when kelvin0>99 and kelvin0<200 else
2 when kelvin0>199 and kelvin0<300 else
3 when kelvin0>299 and kelvin0<400 else
4 when kelvin0>399 and kelvin0<500 else
5 when kelvin0>499 and kelvin0<600 else
6 when kelvin0>599 and kelvin0<700 else
7 when kelvin0>699 and kelvin0<800 else
8 when kelvin0>799 and kelvin0<900 else
9 when kelvin0>899 and kelvin0<1000 else
0;

kelvinh2 <= kelvin0 - (kelvin3*100);

kelvin2 <= 1 when kelvinh2>9 and kelvinh2<20 else

2 when kelvinh2>19 and kelvinh2<30 else
3 when kelvinh2>29 and kelvinh2<40 else
4 when kelvinh2>39 and kelvinh2<50 else
5 when kelvinh2>49 and kelvinh2<60 else
6 when kelvinh2>59 and kelvinh2<70 else
7 when kelvinh2>69 and kelvinh2<80 else
8 when kelvinh2>79 and kelvinh2<90 else
9 when kelvinh2>89 and kelvinh2<100 else
0;

kelvin1 <= kelvinh2 - (kelvin2*10);

kelSeg3 <= "1111110" when kelvin1 = 0 else

"0110000" when kelvin1 = 1 else
"1101101" when kelvin1 = 2 else
"1111001" when kelvin1 = 3 else
"0110011" when kelvin1 = 4 else

11
 "1011011" when kelvin1 = 5 else
"1011111" when kelvin1 = 6 else
"1110000" when kelvin1 = 7 else
"1111111" when kelvin1 = 8 else
"1111011" when kelvin1 = 9 else
"0000000";

kelSeg4 <= "1111110" when kelvin2 = 0 else

"0110000" when kelvin2 = 1 else
"1101101" when kelvin2 = 2 else
"1111001" when kelvin2 = 3 else
"0110011" when kelvin2 = 4 else
"1011011" when kelvin2 = 5 else
"1011111" when kelvin2 = 6 else
"1110000" when kelvin2 = 7 else
"1111111" when kelvin2 = 8 else
"1111011" when kelvin2 = 9 else
"0000000";

kelSeg5 <= "1111110" when kelvin3 = 0 else

"0110000" when kelvin3 = 1 else
"1101101" when kelvin3 = 2 else
"1111001" when kelvin3 = 3 else
"0110011" when kelvin3 = 4 else
"1011011" when kelvin3 = 5 else
"1011111" when kelvin3 = 6 else
"1110000" when kelvin3 = 7 else
"1111111" when kelvin3 = 8 else
"1111011" when kelvin3 = 9 else
"0000000";

kelSeg6 <= "1111110";

k1 <= "0000" when kelvin1 = 0 else

"0001" when kelvin1 = 1 else
"0010" when kelvin1 = 2 else
"0011" when kelvin1 = 3 else
"0100" when kelvin1 = 4 else
"0101" when kelvin1 = 5 else
"0110" when kelvin1 = 6 else
"0111" when kelvin1 = 7 else
"1000" when kelvin1 = 8 else
"1001" when kelvin1 = 9 else
"0000";

k2 <= "0000" when kelvin2 = 0 else

"0001" when kelvin2 = 1 else
"0010" when kelvin2 = 2 else
"0011" when kelvin2 = 3 else
"0100" when kelvin2 = 4 else
"0101" when kelvin2 = 5 else
"0110" when kelvin2 = 6 else

12
 "0111" when kelvin2 = 7 else
"1000" when kelvin2 = 8 else
"1001" when kelvin2 = 9 else
"0000";

k3 <= "0000" when kelvin3 = 0 else

"0001" when kelvin3 = 1 else
"0010" when kelvin3 = 2 else
"0011" when kelvin3 = 3 else
"0100" when kelvin3 = 4 else
"0101" when kelvin3 = 5 else
"0110" when kelvin3 = 6 else
"0111" when kelvin3 = 7 else
"1000" when kelvin3 = 8 else
"1001" when kelvin3 = 9 else
"0000";

k4 <= "0000";

process (hexdec)

begin
if kelvin = '0' then
if hexdec = '0' then

iSeg1 <= "0111101";

iSeg2 <= "0110111";

iSeg3 <= biseg3;

iSeg4 <= biseg4;

iSeg5 <= biseg5;

iSeg6 <= biseg6;

ilcd1 <= d1;

ilcd2 <= d2;
ilcd3 <= d3;
ilcd4 <= d4;

else

iSeg1 <= "1001110";

iSeg2 <= "1100011";

iSeg3 <= decseg3;

iSeg4 <= decseg4;

13
 iSeg5 <= decseg5;

iSeg6 <= decseg6;

ilcd1 <= c1;

ilcd2 <= c2;
ilcd3 <= c3;
ilcd4 <= c4;

end if;

else

iSeg1 <= "0000100";

iSeg2 <= "0100111";

iSeg3 <= kelseg3;

iSeg4 <= kelseg4;

iSeg5 <= kelseg5;

iSeg6 <= kelseg6;

ilcd1 <= k1;

ilcd2 <= k2;
ilcd3 <= k3;
ilcd4 <= k4;
-- if d1 = "00000" then
-- iSeg3 <= "1111110";
-- iSeg3 <= "1111110" when d1 = "00000" else
-- "0110000" when d1 = "000001" else
-- "1101101" when d1 = "000010" else
-- "1111001" when d1 = "00011" else
-- "0110011" when d1 = "00100" else
-- "1011011" when d1 = "00101" else
-- "1011111" when d1 = "00110" else
-- "1110000" when d1 = "00111" else
-- "1111111" when d1 = "01000" else
-- "1111011" when d1 = "01001" else
-- "1110111" when d1 = "01010" else
-- "0011111" when d1 = "01011" else
-- "1001110" when d1 = "01100" else
-- "0111101" when d1 = "01101" else
-- "1001111" when d1 = "01110" else
-- "1000111" when d1 = "01111" else
-- "0000000";
--
-- iSeg4 <= "1111110" when d2 = "00000" else

14
-- "0110000" when d2 = "000001" else
-- "1101101" when d2 = "000010" else
-- "1111001" when d2 = "00011" else
-- "0110011" when d2 = "00100" else
-- "1011011" when d2 = "00101" else
-- "1011111" when d2 = "00110" else
-- "1110000" when d2 = "00111" else
-- "1111111" when d2 = "01000" else
-- "1111011" when d2 = "01001" else
-- "1110111" when d2 = "01010" else
-- "0011111" when d2 = "01011" else
-- "1001110" when d2 = "01100" else
-- "0111101" when d2 = "01101" else
-- "1001111" when d2 = "01110" else
-- "1000111" when d2 = "01111" else
-- "0000000";
--
-- iSeg5 <= "1111110" when d3 = "00000" else
-- "0110000" when d3 = "000001" else
-- "1101101" when d3 = "000010" else
-- "1111001" when d3 = "00011" else
-- "0110011" when d3 = "00100" else
-- "1011011" when d3 = "00101" else
-- "1011111" when d3 = "00110" else
-- "1110000" when d3 = "00111" else
-- "1111111" when d3 = "01000" else
-- "1111011" when d3 = "01001" else
-- "1110111" when d3 = "01010" else
-- "0011111" when d3 = "01011" else
-- "1001110" when d3 = "01100" else
-- "0111101" when d3 = "01101" else
-- "1001111" when d3 = "01110" else
-- "1000111" when d3 = "01111" else
-- "0000000";
--
-- iSeg6 <= "1111110" when d4 = "00000" else
-- "0110000" when d4 = "000001" else
-- "1101101" when d4 = "000010" else
-- "1111001" when d4 = "00011" else
-- "0110011" when d4 = "00100" else
-- "1011011" when d4 = "00101" else
-- "1011111" when d4 = "00110" else
-- "1110000" when d4 = "00111" else
-- "1111111" when d4 = "01000" else
-- "1111011" when d4 = "01001" else
-- "1110111" when d4 = "01010" else
-- "0011111" when d4 = "01011" else
-- "1001110" when d4 = "01100" else
-- "0111101" when d4 = "01101" else
-- "1001111" when d4 = "01110" else
-- "1000111" when d4 = "01111" else
-- "0000000";

15
-- else
--
-- deci2 <= deci / 10;
-- deci1 <= deci mod 10;
--
-- Seg1 <= "1001110";
--
-- Seg2 <= "1100011";
--
-- Seg3 <= "1111110" when deci1 = 0 else
-- "0110000" when deci1 = 1 else
-- "1101101" when deci1 = 2 else
-- "1111001" when deci1 = 3 else
-- "0110011" when deci1 = 4 else
-- "1011011" when deci1 = 5 else
-- "1011111" when deci1 = 6 else
-- "1110000" when deci1 = 7 else
-- "1111111" when deci1 = 8 else
-- "1111011" when deci1 = 9 else
-- "0000000";
--
-- Seg4 <= "1111110" when deci2 = 0 else
-- "0110000" when deci2 = 1 else
-- "1101101" when deci2 = 2 else
-- "1111001" when deci2 = 3 else
-- "0110011" when deci2 = 4 else
-- "1011011" when deci2 = 5 else
-- "1011111" when deci2 = 6 else
-- "1110000" when deci2 = 7 else
-- "1111111" when deci2 = 8 else
-- "1111011" when deci2 = 9 else
-- "0000000";
--
-- Seg5 <= "0000000";
--
-- Seg6 <= "0000000";
end if;

end process;

Seg1 <= iSeg1;

Seg2 <= iSeg2;
Seg3 <= iSeg3;
Seg4 <= iSeg4;
Seg5 <= iSeg5;
Seg6 <= iSeg6;

lcd1 <= ilcd1;

lcd2 <= ilcd2;
lcd3 <= ilcd3;
lcd4 <= ilcd4;

16
end Behavioral;

SCAN4DIGIT

entity Scan4Digit is
Port ( digit0 : in STD_LOGIC_VECTOR (6 downto 0);
digit1 : in STD_LOGIC_VECTOR (6 downto 0);
digit2 : in STD_LOGIC_VECTOR (6 downto 0);
digit3 : in STD_LOGIC_VECTOR (6 downto 0);
digit4 : in STD_LOGIC_VECTOR (6 downto 0);
digit5 : in STD_LOGIC_VECTOR (6 downto 0);
clock : in STD_LOGIC;
an : out STD_LOGIC_VECTOR (5 downto 0);
ca : out STD_LOGIC;
cb : out STD_LOGIC;
cc : out STD_LOGIC;
cd : out STD_LOGIC;
ce : out STD_LOGIC;
cf : out STD_LOGIC;
cg : out STD_LOGIC);
end scan4Digit;

architecture Behavioral of scan4Digit is

signal iCount16: std_logic_vector (15 downto 0) := (others=>'0');
signal iDigitOut: std_logic_vector (6 downto 0);
begin
-- Generate the scan clock 50MHz/2**16 (763Hz)
process(Clock)
begin
if Clock'event and Clock='1' then
iCount16 <= iCount16 + '1';
end if;
end process;

--Send four digits to four 7-segment display using scan mode

with iCount16 (15 downto 13) select
iDigitOut <= Digit0 when "000", -- Connect Digit0 to the 7-segment display
Digit1 when "001", -- Connect Digit1 to the 7-segment display
Digit2 when "010", -- Connect Digit2 to the 7-segment display
Digit3 when "011", -- Connect Digit3 to the 7-segment display
Digit4 when "100", -- Connect Digit4 to the 7-segment display
Digit5 when "101", -- Connect Digit5 to the 7-segment display
Digit0 when others;
with iCount16 (15 downto 13) select
An <= "111110" when "000", -- with AN0 low only
"111101" when "001", -- with AN1 low only
"111011" when "010", -- with AN2 low only
"110111" when "011", -- with AN3 low only
"101111" when "100", -- with AN3 low only
"011111" when "101", -- with AN3 low only
"111110" when others;
Ca <= iDigitOut(6);
Cb <= iDigitOut(5);

17
Cc <= iDigitOut(4);
Cd <= iDigitOut(3);
Ce <= iDigitOut(2);
Cf <= iDigitOut(1);
Cg <= iDigitOut(0);
end Behavioral;

LCD

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity LCD is
port ( SystemClock: in std_logic;
lcd1: in STD_LOGIC_VECTOR (3 downto 0);
lcd2: in STD_LOGIC_VECTOR (3 downto 0);
lcd3: in STD_LOGIC_VECTOR (3 downto 0);
lcd4: in STD_LOGIC_VECTOR (3 downto 0);
LCDE : out std_logic;
LCDRS : out std_logic;
LCDRW : out std_logic;
SFD : out std_logic_vector (3 downto 0));
end LCD;

architecture Behavioral of LCD is

signal iData1, iData2, iData3, iData4 : STD_LOGIC_VECTOR (7 downto 0):= (others=>'0'); -- Data to be
displayed
signal Startup : std_logic := '0'; -- Power-On Initialization ready
signal displayconfig : std_logic := '0'; -- Display configuration ready
signal startcount : std_logic_vector (20 downto 0):= (others=>'0');
signal colours : std_logic_vector (5 downto 0):= (others=>'0');
signal iLCDE, iLCDRS : std_logic := '0';
signal iSFD : std_logic_vector (3 downto 0):= (others=>'0');
signal changers1, changers2: std_logic := '0';
signal systemstart: std_logic:= '0';
signal systemstartup : std_logic_vector (25 downto 0):= (others=>'0');
signal iLCDEfake : std_logic := '0';
signal iSFDfake : std_logic_vector (3 downto 0);

-- Procedure sendbit ( signal click : in std_logic;

-- signal dataout: in std_logic_vertor (7
downto 0);
-- signal iLCDE:out std_logic;
-- signal iSFD: out std_logic_vector (3 downto
0)) is

18
-- variable timing : integer;
-- begin
-- timing <= 0;
-- if click'event and click = '1' then
-- timing <= timing + 1;
-- end if;
-- if timing>0 and timing<45 then
-- iSFD <= dataout(7 downto 4);
-- elsif timing>46 and timing<90 then
-- iSFD <= dataout (3 downto 0);
-- else
-- iSFD <= "0000";
-- end if;
-- if timing>3 and timing<18 then
-- iLCDE <= '1';
-- elsif timing>70 and timing<85 then
-- iLCDE <= '1';
-- else
-- iLCDE <= '0';
-- end if;

begin

LCDRW <= '0'; -- LCD-RW signal is tied low permanently

iData1 <= "00110000" when lcd1 = "0000" else

"00110001" when lcd1 = "0001" else
"00110010" when lcd1 = "0010" else
"00110011" when lcd1 = "0011" else
"00110100" when lcd1 = "0100" else
"00110101" when lcd1 = "0101" else
"00110110" when lcd1 = "0110" else
"00110111" when lcd1 = "0111" else
"00111000" when lcd1 = "1000" else
"00111001" when lcd1 = "1001" else
"01000001" when lcd1 = "1010" else
"01000010" when lcd1 = "1011" else
"01000011" when lcd1 = "1100" else
"01000100" when lcd1 = "1101" else
"01000101" when lcd1 = "1110" else
"01000110" when lcd1 = "1111" else
"00110000";

iData2 <= "00110000" when lcd2 = "0000" else

"00110001" when lcd2 = "0001" else
"00110010" when lcd2 = "0010" else
"00110011" when lcd2 = "0011" else
"00110100" when lcd2 = "0100" else
"00110101" when lcd2 = "0101" else
"00110110" when lcd2 = "0110" else
"00110111" when lcd2 = "0111" else
"00111000" when lcd2 = "1000" else

19
 "00111001" when lcd2 = "1001" else
"01000001" when lcd2 = "1010" else
"01000010" when lcd2 = "1011" else
"01000011" when lcd2 = "1100" else
"01000100" when lcd2 = "1101" else
"01000101" when lcd2 = "1110" else
"01000110" when lcd2 = "1111" else
"00110000";

iData3 <= "00110000" when lcd3 = "0000" else

"00110001" when lcd3 = "0001" else
"00110010" when lcd3 = "0010" else
"00110011" when lcd3 = "0011" else
"00110100" when lcd3 = "0100" else
"00110101" when lcd3 = "0101" else
"00110110" when lcd3 = "0110" else
"00110111" when lcd3 = "0111" else
"00111000" when lcd3 = "1000" else
"00111001" when lcd3 = "1001" else
"01000001" when lcd3 = "1010" else
"01000010" when lcd3 = "1011" else
"01000011" when lcd3 = "1100" else
"01000100" when lcd3 = "1101" else
"01000101" when lcd3 = "1110" else
"01000110" when lcd3 = "1111" else
"00110000";

iData4 <= "00110000" when lcd4 = "0000" else

"00110001" when lcd4 = "0001" else
"00110010" when lcd4 = "0010" else
"00110011" when lcd4 = "0011" else
"00110100" when lcd4 = "0100" else
"00110101" when lcd4 = "0101" else
"00110110" when lcd4 = "0110" else
"00110111" when lcd4 = "0111" else
"00111000" when lcd4 = "1000" else
"00111001" when lcd4 = "1001" else
"01000001" when lcd4 = "1010" else
"01000010" when lcd4 = "1011" else
"01000011" when lcd4 = "1100" else
"01000100" when lcd4 = "1101" else
"01000101" when lcd4 = "1110" else
"01000110" when lcd4 = "1111" else
"00110000";

-- START SYSTEM --
process (SystemClock)
begin
if Systemstart = '1' then
Systemstart <= '1';
systemstartup <= (others=>'0');

20
 iSFDfake <= "0000";
iLCDEfake <= '0';
else
if SystemClock'event and SystemClock = '1' then
systemstartup <= systemstartup + '1';
end if;
if systemstartup = "10110111000110110000" then
iLCDEfake <= '1';
iSFDfake <= "0011";
elsif systemstartup = "10110111000110111100" then
iLCDEfake <= '0';
iSFDfake <= "0000";
elsif systemstartup = "11101001001010000100" then
iLCDEfake <= '1';
iSFDfake <= "0011";
elsif systemstartup = "11101001001010010000" then
iLCDEfake <= '0';
iSFDfake <= "0000";
elsif systemstartup = "11101010011000011000" then
iLCDEfake <= '1';
iSFDfake <= "0011";
elsif systemstartup = "11101010011000100100" then
iLCDEfake <= '0';
iSFDfake <= "0000";
elsif systemstartup = "11101010110111110100" then
iLCDEfake <= '1';
iSFDfake <= "0011";
elsif systemstartup = "11101010111000000000" then
iLCDEfake <= '0';
iSFDfake <= "0000";

-- power-on initialization finished, move to display configuration

-- function set
elsif systemstartup = "11101011010111010000" then
iSFDfake <= "0010";
elsif systemstartup = "111010110101110100101" then
iLCDEfake <= '1';
elsif systemstartup = "11101011010111011111" then
iLCDEfake <= '0';
elsif systemstartup = "11101011010111100000" then
iSFDfake <= "1000";
elsif systemstartup = "11101011011000010110" then
iLCDEfake <= '1';
elsif systemstartup = "11101011011000100010" then
iLCDEfake <= '0';

-- entry mode set

elsif systemstartup = "11101011011000100011" then
iSFDfake <= "0000";
elsif systemstartup = "11101011110111110011" then
iLCDEfake <= '1';

21
 elsif systemstartup = "11101011110111111111" then
iLCDEfake <= '0';
elsif systemstartup = "11101011111000000000" then
iSFDfake <= "0110";
elsif systemstartup = "11101011111000110010" then
iLCDEfake <= '1';
elsif systemstartup = "11101011111000111110" then
iLCDEfake <= '0';
elsif systemstartup = "11101011111000111111" then
iSFDfake <= "0000";

-- display on/off
elsif systemstartup = "11101100011000001111" then
iLCDEfake <= '1';
elsif systemstartup = "11101100011000011011" then
iLCDEfake <= '0';
elsif systemstartup = "11101100011000011100" then
iSFDfake <= "1100";
elsif systemstartup = "11101100100000010000" then
iLCDEfake <= '1';
elsif systemstartup = "11101100100000011100" then
iLCDEfake <= '0';
elsif systemstartup = "11101100100000011101" then
iSFDfake <= "0000";

-- Clear display
elsif systemstartup = "11101100111111101101" then
iLCDEfake <= '1';
elsif systemstartup = "11101100111111111001" then
iLCDEfake <= '0';
elsif systemstartup = "11101100111111111001" then
iSFDfake <= "0001";
elsif systemstartup = "11101101000000101100" then
iLCDEfake <= '1';
elsif systemstartup = "11101101000000111000" then
iLCDEfake <= '0';
elsif systemstartup = "100000001000010001000" then
Systemstart <= '1';
-- else
-- iLCDEfake <= iLCDEfake;
-- iSFDfake <= iSFDfake;
-- Systemstart <= Systemstart;
end if;
end if;
end process;

-- SET COLOURS --
process (SystemClock)
begin
if Systemstart = '1' then
if SystemClock'event and SystemClock = '1' then

22
 if colours="0" or colours ="10" or colours ="100" or colours ="110" or colours ="1000"
or colours ="1010" or colours ="1100" or colours ="1110" or colours ="10000" or colours ="10010" then
startcount <= startcount + '1';
iLCDRS <= '1';
if startcount = "10110" then -- 22 cycles / 440
ns
colours <= colours + '1';
startcount <= (others=>'0');
end if;
--end if;

elsif colours="1" or colours ="101" or colours ="1001" or colours ="1101" or colours

="10001" then
startcount <= startcount + '1';
iLCDRS <= '1';
if startcount = "110110" then -- 54 cycles /
1080 ns
colours <= colours + '1';
startcount <= (others=>'0');
end if;
--end if;

elsif colours="11" or colours ="111" or colours ="1011" or colours ="1111" then

startcount <= startcount + '1';
iLCDRS <= '1';
if startcount = "11111010100" then -- 2004 cycles / 40080 ns
colours <= colours + '1';
startcount <= (others=>'0');
end if;
--end if;

elsif colours="10011" then

startcount <= startcount + '1';
iLCDRS <= '0';
if startcount = "10100000001011010" then -- 82010 cycles / 1.6402
ms
colours <= (others=>'0');
startcount <= (others=>'0');
end if;
--end if;
-- else
-- colours <= (others=>'0');
-- iLCDRS <= '0';
end if;
end if;
else
iLCDRS <= '0';
end if;
end process;

LCDRS <= iLCDRS;

23
 -- SEND LCD_E --
process (Colours, startcount, iLCDEfake)
begin
if SystemStart = '1' then
if colours="0" or colours ="10" or colours ="100" or colours ="110" or colours ="1000" or colours
="1010" or colours ="1100" or colours ="1110" or colours ="10000" or colours ="10010" then
if startcount = "100" then
iLCDE <= '1';
end if;
if startcount = "10100" then
iLCDE <= '0';
end if;
end if;
else
iLCDE <= iLCDEfake;
end if;
end process;

LCDE <= iLCDE;

-- SEND DATAS --
process (Colours, iSFDfake)
begin
if Systemstart = '1' then
if colours="0" then
iSFD <= iData1(7 downto 4);
changers1 <= '1';
end if;
if colours ="10" then
iSFD <= iData1(3 downto 0);
changers1 <= '1';
end if;
if colours ="100" then
iSFD <= iData2(7 downto 4);
changers1 <= '1';
end if;
if colours ="110" then
iSFD <= iData2(3 downto 0);
changers1 <= '1';
end if;
if colours ="1000" then
iSFD <= iData3(7 downto 4);
changers1 <= '1';
end if;
if colours ="1010" then
iSFD <= iData3(3 downto 0);
changers1 <= '1';
end if;
if colours ="1100" then
iSFD <= iData4(7 downto 4);
changers1 <= '1';

24
 end if;
if colours ="1110" then
iSFD <= iData4(3 downto 0);
changers1 <= '1';
end if;
if colours ="10000" then
iSFD <= "0000";
changers1 <= '0';
end if;
if colours ="10010" then
iSFD <= "0001";
changers1 <= '0';
end if;
else
iSFD <= iSFDfake;
end if;
end process;

SFD <= iSFD;

-- process (SystemClock)
-- begin
--
-- if SystemClock'event and SystemClock = '1' then
-- startcount <= startcount + 1;
-- end if;
-- if startcount = then
-- iSFD <= dataout(7 downto 4);
-- elsif startcount>46 and startcount<90 then
-- iSFD <= dataout (3 downto 0);
-- else
-- iSFD <= "0000";
-- end if;
-- if startcount>3 and startcount<18 then
-- iLCDE <= '1';
-- elsif startcount>70 and startcount<85 then
-- iLCDE <= '1';
-- else
-- iLCDE <= '0';
-- end if;
-- end process;

end Behavioral;

D4TO7

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;

25
--use UNISIM.VComponents.all;

entity D4to7 is
Port ( q : in STD_LOGIC_VECTOR (3 downto 0);
seg : out STD_LOGIC_VECTOR (6 downto 0));
end D4to7;

architecture Behavioral of D4to7 is

begin
Seg<= "1111110" when q = "00000" else
"0110000" when q = "000001" else
"1101101" when q = "000010" else
"1111001" when q = "00011" else
"0110011" when q = "00100" else
"1011011" when q = "00101" else
"1011111" when q = "00110" else
"1110000" when q = "00111" else
"1111111" when q = "01000" else
"1111011" when q = "01001" else
"1110111" when q = "01010" else
"0011111" when q = "01011" else
"1001110" when q = "01100" else
"0111101" when q = "01101" else
"1001111" when q = "01110" else
"1000111" when q = "01111" else
"0000000";
end Behavioral;

26