International Journal of Innovative Technology and Exploring Engineering (IJITEE)

ISSN: 2278-3075, Volume-8, Issue-7S, May 2019

Static Timing Analysis and Timing Violations

of Sequential Circuits
G.Siva Priya, K.Hari Kishore, Fazal Noorbasha

Abstract: Designing of sequential circuits needs timing analysis

at each and every stage of design process (synthesis, floor planning,
placement, routing, layout design...) and comprises of three main
parts-Timing checks, Constraints and Libraries. Timing checks
such as setup (Ts) and hold time (Th) violation check in sequential
circuits plays an important role during timing verification. This
paper describes about static timing analysis mainly about reg2reg
setup and holds analysis and analyses a kind of detection and
correction circuits for Ts and Th violations [1] by associating a
digital circuit to them. Fig . 2.1 STA parts
Constraints are design specifications like operating
Index Terms: Timing parameters, static timing analysis,
additional pessimism, on-chip variations
frequency whereas libraries are cells with delay models and
are used to calculate delays of the cells.
I. INTRODUCTION Timing Checks
Sequential circuits are the major ones playing role in digital For any chip before moving to fabrication stage static timing
world. Without sequential circuits, no automation comes into analysis is the mandatory one so that we can reduce. Timing
practice. For such circuits, flip flops are the major blocks in violations. Initial level of checking/diagnosis for the chip is
which clock plays a key role. The relation between clock and timing check and timing checks we do are setup time, hold
data can modify the whole circuit as reliable or unreliable. So time, recovery, removal, etc. Timing checks requires
the timing of data with respect to time should be precise and following terms:
compatible or else the circuit enters into metastable state or i. Timing path- valid critical path identification is
gives corrupted results. While designing sequential circuits, important.
we come across different stages like logic synthesis, floor ii. Arrival time
planning, placement, clock tree synthesis, routing, and layout. iii. Required time
At every stage, timing analysis is important. Synchronous iv. Slack-min,max
sequential circuits need precise timing parameters and
violations in these specifications causes the Chip to operate Timing path: Path that reaches endpoint from start point
with reduced frequency or totally failure of chip. Timing where start point is of flip-flop clock pin/input port and end
parameters or Specifications are setup time, hold time, clock point is of flip-flop d pin/output ports as shown in Fig. 2.2.
frequency (f), skew and some other parameters Many factors
effects these parameters [2] such asprocess dependent factors-
etching, oxidation power supply voltage fluctuations Aging
Jitter.

II. STATIC TIMING ANALYSIS Fig . 2.2 Timing path definition

Static Timing Analysis (STA) mainly divided into three Arrival time (AT): Time required reaching end point from
kinds like timing checks, constraints, libraries as shown in Fig. start point and it is always calculated at end points.
2.1. Required Time (RT): Expected time for signal to arrive end
point from start point. It defines the design needs like
operating frequency.
Slack: Difference between arrival and required time.
Min slack/hold slack/min difference=AT-RT
Revised Manuscript Received on May 05, 2019. Max Slack or Setup slack or max difference=RT-AT
G.Siva Priya, Department of ECE, Koneru Lakshmaiah Education
Foundation, Vaddeswaram, Guntur, Andhra Pradesh, India
K.Hari Kishore, Department of ECE, Koneru Lakshmaiah Education
Foundation, Vaddeswaram, Guntur, Andhra Pradesh, India
Fazal Noorbasha, Department of ECE, Koneru Lakshmaiah Education
Foundation, Vaddeswaram, Guntur, Andhra Pradesh, India

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Retrieval Number: G10240587S19/19©BEIESP 115 & Sciences Publication
 Static Timing Analysis and Timing Violations of Sequential Circuits

Types of slack is shown in Fig. 2.3 Data to data analysis: paths from clock to a pin and another
clock to control signal.
Latch (time borrowing/time given) analysis: In some of the
sequential circuits, latches are available. If the time between
clock and latch does not meet, then level of latch can be
borrowed to clock period known as ‘time borrowing’. If the
time between latch and top flip-flop in the circuit doesn’t
meet, then time can be given to flip-flop from latch known as
‘time given’.
Slew/Transition analysis: Data and clock slews are
Fig. 2.3 Types of slack
calculated as they have different signal transition timings(rise
From these two we have setup timing and hold timing and fall times) because clock changes rapidly while data
analysis. We concern mainly about setup and hold static changes not often.
timing analysis. There are different types of setup and hold Load analysis: At each and every node ofcircuits, load
timing analysis. Based on the timing paths available, number values can be calculated. At loads, fan-out and capacitance
of analysis varies. As shown in Fig. 2.4, we have maximum values are calculated.
types of timing analysis. Clock timing analysis: A critical analysis of STA where
skew and clock pulse width values are majorly important.

III. DEMONSTRATION OF REG2REG SETUP/HOLD

ANALYSIS WITH AN EXAMPLE
Out of all kinds of analysis, understanding of reg2reg
analysis makes remaining analysis easy to understand. Now a
circuit is considered and doing reg2reg setup/hold analysis
[8].For this analysis, step by step process is followed.
Step-1: Consider a circuit as in Fig. 3.1 with known
specifications like gate delays, wire delays, clock period,
combinational path delay, clock-to-q delay, setup time, hold
time, jitter uncertainty, required arrival time at final output
Fig. 2.4 Sequential circuit to consider timing paths port, initial signal arrival times of combinational circuit.

Types of setup/hold analysis:

1. reg2reg
2. in2reg
3. reg2out
4. in2out
5. clock gating
6. recovery/removal
7. data-to-data
8. latch(time borrowing/time given)
9. slew/transition-(data, clock)
Fig . 3.1 Sequential circuit
10. load-(fan out, capacitance)
11. Clock timing-(skew, pulse width)
Reg2reg analysis: Timing path from launch flip-flop clock
port to capture flip-flop d pin which includes two registers
(flip-flops), so reg2reg.
In2reg analysis: path from input port to launch flip-flop d
pin.
Reg2out analysis: path from capture flip-flop clock port to
output port.
In2out analysis: path from input port to output port.
Clock gating analysis: path from another clock pin to AND
gate output i.e., making the capture flip-flop as gated one by Fig. 3.2 Combinational circuit in the above sequential
applying clock signal whenever the flip-flop is needed which circuit
reduces power consumption.
Recovery/removal analysis: path from another clock port to
reset signal port of capture flip-flop.

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 International Journal of Innovative Technology and Exploring Engineering (IJITEE)
ISSN: 2278-3075, Volume-8, Issue-7S, May 2019

Here i1(0), i2(0.3), i3(0.5) are input signals to i2(0) 0.3 -0.05 -0.35
combinational circuit and values inside them are signal arrival i3(0) 0.5 2.1 1.6
times from source i.e., flip-flop output, values inside gates a(2) 2.4 2.05 -0.35
indicate gate propagation delays and values above wires b(2) 4.6 5.15 0.55
indicate wire delays, clock frequency considered here is c(3) 5.55 5.2 -0.35
1GHz, so clock period=1 ns. d(2) 7.8 7.45 -0.35
Step-2: Converting circuit into directed acyclic graph o1(0) 7.9 7.55 -0.35
(DAG) known as timing graph where complete circuitry (all
input ports, output ports, gates) is represented in nodes form as To get positive sla ck at some nodes we do path based
shown in Fig. 3.3 analysis (PBA) instead of graph based analysis(GBA). GBA is
nothing but the previous process we have done.In calculation
of AAT if we consider min value instead of worst value then
we may get positive slack, this is known as PBA.
Step-6: Convert pins to nodes and compute AAT, RAT and
slack
For detailed and accurate timing analysis, we go for PBA.
For this we make timing graph with pin node conventions. The
points before gates and after gates, input, output ports are
considered as pins and all these pins are converted to nodes
and will make timing graph. Then computation of AAT, RAT
Fig . 3.3 Timing graph and slack follows the same process as before.
Step-3: Calculation of actual arrival time (AAT) Step-7: Setup and Hold analysis equation
AAT is calculated at every node by moving forward (launch The timing analysis equations are given for the circuit shown
flip-flop to capture flip-flop) in timing graph. It is done by in Fig. 3.4
adding up node delay(at which node we are calculating) and
wire delay previous to that(where the signal is coming from)
to previous node AAT. If a node has more than one receiving
signal then worst/max/late values of all arrival times are
considered as AAT.
Step-4: Calculation of required arrival time (RAT)
RAT is described as time at any node where we expect the
latest transition in a single clock cycle; it is a requirement,
specification. RAT is also calculated at every node by moving
backward from capture flip-flop to launch flip-flop in timing
graph. It is done by subtracting the previous node delay, wire Fig. 3.4 Circuit for setup analysis with single clock
delay from previous node RAT. If a node consists of two
Setup analysis equation:
RATs then min/best/early value is considered.
Step-5: calculation of slack
Where θ =clk-to-q delay + combinational logic delay
Setup slack=RAT-AAT ∆1=sum of launch F/F clock network buffer delays
=Delay of (1+2+3) buffers
Hold slack=AAT-RAT
T= Time period of clock
Slack value should be positive or zero but should not be ∆2 =Sum of capture F/F clock network buffer delays
negative. If negative slack occurs then there is a violation, =Delays of (1+2+4) buffers
have to modify to get positive slack. At every node slack is S=setup time
calculated to identify which node is causing negative slack so Su=setup uncertainty=Parameter used to model jitter.
that we can do changes to make slack value positive and this Actual setup equation is showing that signal reaching
process of making positive slack is known as “Engineering from clock pin of launch F/F to capture F/F D pin which
Change Order”(ECO). The AAT,RAT and slack values from includes path of clock network, combinational logic, clock-to-
the timing graph is given in below table 1. Here the RAT at q delay (internal delay of flip-flop) should arrive within a
output port is taken as 7.55ns. All the values are considered in clock cycle. With inclusion of clock network buffers, we add
ns time units. those values on both sides (∆1, ∆2). Signal should arrive
within time period excluding setup time and jitter.
Table 1. Arrival times and Slack values at nodes
Node AAT RAT Slack
S 0 -0.35 -0.35
i1(0) 0 3.05 3.05

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 Static Timing Analysis and Timing Violations of Sequential Circuits

The left hand side equation refers to arrival time of data and =0.0104+0.0344+0.0168+0.0408+0.0256+0.0664=0.01994ns
right hand side refers to required time of data.
Hold analysis equation: =(1+0.01994-0.01-0.09) ns=1.0994ns
Where H=hold time Slack=RT-AT=1.0994-1.115=-0.0206ns
Hu=Hold uncertainty of jitter It shows negative slack which indicates setup violation. It
Equation describes that time needed to launch the data has arises because of OCV and to avoid timing violation we have
limitation of θ >H i.e., time needed to reach the data from to remove additional pessimism (AP) introduced in it.
launch F/F clock pin to D pin of capture F/F should be at least In Δ1 and , we havecommon buffer delays b1 and b2.When
greater than hold time.LHS side of equation refers to data we observe these delay values there exists different cell delay
arrival time and RHS side refers to data required time. values due to OCV. In general a cell can’t have two different
Step-8: Graphical to textual representation To have timing delay values at a time. So we have to equalize it.
reports conversion of all the information in graphical form to Step-9: AP removal
textual form is needed. Textual representation of setup The difference between common path delays is termed as
analysis is: additional pessimism. This AP value may have get added in
or lost in due to OCV. So let’s add AP to Δ2 to
equalize common path delays. This addition or removal of AP
= (0.9+0.013+0.043+0.021+0.051+0.032+0.055) ns to or should be in such a way that to get
= 1.115ns positive slack.
Where = sum of delays of buffers 1, 2, 3
=net delay (wire delay) of buffer 1 Δ
= cell delay of buffer 1 = 0.128-0.1024=0.0256ns
Similar indications for buffers 2 and 3.All the values above are Addition of AP to =0.1024+0.0256=0.128ns equal to
considered values from a foundry for a circuit with known common path delay.
specifications for analysis purpose. RT=1.12ns
Slack=RT-AT=1.12-1.115=0.005ns= positive slack showing
= no violation.
Thus STA with OCV consideration before fabrication
=(1+0.013+0.043+0.021+0.051+0.032+0.083-0.01_0.09) ns makes the chip gets fabricated without any violation. The
=1.143ns same OCV theory and AP removal is applicable to hold
Slack=RT-AT=1.143-1.115=0.028ns analysis also. Now textual representation of hold analysis:
It shows a positive slack, so there is no setup violation. But
this not the real scenario while dealing with fabricated chips. =>
The delay values may vary depending upon on-chip variation =>
(OCV) derates. This is due to etching and oxidation process of
fabrication. For example consider OCV derates as +20%, - =>0.14+0.013+0.043+0.021+0.051+0.032+0.055 >
20%, the percentage varies from foundry to foundry and 0.01+0.013+0.043+0.021+0.051+0.052+0.083+0.05
indicates that the delay values in clock network may get =>Slack=AT-RT=0.355-0.303=0.052ns=positive slack
increased or decreased by 20%.For example a 100 ns delay =>no violation.
value can range between 80 to 120 ns. So there will be 4ways Here θ value is less compared to setup analysis because min
of variation in clock network delays. Those variations are delays are considered while computing hold analysis.
a) Increase of delay values in AT(∆1 ) by 20%, increase Consider OCV for hold analysis and worst case for this
of delay values in RT(∆2 ) by 20% analysis is both clock pull-in in AT and clock push-out in RT.
b) Increase of delay values in AT( ∆1 )by 20%, decrease Then and values after decrease in delay values by 20%
of delay values in RT by 20% in and increase in delay values in by 20%/ are:
c) Decrease of delay values in AT( Δ1) by 20%, =0.0104+0.0344+0.0168+0.0408+0.0256+0.044
increase of delay values in RT( Δ2 ) by20% =0.0156+0.0516+0.0252+0.0612+0.0384+0.0996
d) Decrease of delay values in AT(Δ1) by 20%, =>Slack=AT-RT= -.0396ns= negative slack indicating
decrease of delay values in RT( Δ2 ) by20%. violation.
Increase in delay value in clock network is termed as ‘clock =>AP=0.1536-0.1024=0.0512ns
push-out’ while decrease in delay value of clock network is Subtracting AP in Δ2
termed as ‘clock pull-in’. Now considering STA with OCV =>RT=0.3516-0.0512=0.3004ns
derates. Let us do the worst case analysis i.e., clock pull-in in => Slack=AT-RT=0.312-0.3004=0.0116ns
RT (Δ2) so that violation arises and can eliminate it by the
process of common path pessimism removal (CPPR). Δ2
values after clock pull-in which decreases delay values by
20% are

Published By:
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Retrieval Number: G10240587S19/19©BEIESP 118 & Sciences Publication
 International Journal of Innovative Technology and Exploring Engineering (IJITEE)
ISSN: 2278-3075, Volume-8, Issue-7S, May 2019

It shows positive slack so that hold violation is removed after

pessimism removal.

IV. TIMING VIOLATIONS

Timing violations makes the chip entirely not to run in a
proper mode of operation. From [1] detection and correction
circuits for timing violations have been proposed based on
timing equations analysis. To avoid violations many
techniques have been proposed like adjustable delay buffers
[3]-[6], time borrowing principle [7], etc. Details of detection (a)
and correction circuits are given in [1]. Mostly setup and hold
time violations are seen and have to be avoided.

V. DESIGNS, SIMULATED WAVEFORMS AND

DISCUSSION
Designs and Simulated Waveforms
Detection and correction circuits are
designed in 90nm technology. Block diagram, designed
circuits and waveforms are shown in following figures.

(b)

(a)

(b)

(c)
Fig. 5.2 (a), (b) and (c) represents circuit diagram,
designed circuit and simulated waveform of correction
circuit

(c)
Fig. 5.1(a), (b) and (c) represents circuit diagram, designed
circuit and its simulated waveform of detection circuit

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 Static Timing Analysis and Timing Violations of Sequential Circuits

Fig. 5.3 Block diagram of a Digital circuit associated with (a)

detection and correction circuits

(a)

(b)

(b)

(c)
Fig. 5.5 (a), (b) and (c) represents second sequential
circuit, second sequential circuit associated with detection
and correction circuits and its waveform respectively

(c) VI. DISCUSSION

Fig . 5.4 (a), (b) and (c) represents designs of sequential Detecting clock and data edges and
circuit, sequential circuit associated with detection and comparing the edges and indicating it with control signals is
correction circuits and its waveform done by detection circuit to detect violation. When there is a
violation indication from detection circuit then the correction
circuit modifies the clock by selecting one of the versions of
clock signal so that violation gets avoided. In this paper some
sequential circuits are inserted in between detection and

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 International Journal of Innovative Technology and Exploring Engineering (IJITEE)
ISSN: 2278-3075, Volume-8, Issue-7S, May 2019

correction circuits to observe how the detection and correction 13. Hari Kishore, K., Aswin Kumar, C.V.R.N., Vijay Srinivas, T.,
Govardhan, G.V., Pavan Kumar, C.N., Venkatesh, R.V. Design and
circuits are performing. The circuit diagram, designed circuit
analysis of high efficient UART on spartan-6 and virtex-7 devices (2015)
and simulated waveform of detection circuit is shown in Fig. International Journal of Applied Engineering Research, 10 (9), pp. 23043-
5.1. The correction circuit diagram, designed circuit and 23052.
simulated waveform of correction circuit are shown in Fig. 14. Kante, S., Kakarla, H.K., Yadlapati, A. Design and verification of AMBA
AHB-lite protocol using Verilog HDL (2016) International Journal of
5.2. The two sequential circuits associated with detection and
Engineering and Technology, 8 (2), pp. 734-741.
correction circuits are shown in figures 5.4 and 5.5 15. Bandlamoodi, S., Hari Kishore, K. An FPGA implementation of phase-
respectively. From above associated sequential circuits locked loop (PLL) with self-healing VCO (2015) International Journal of
observation of detection and correction circuits is done. STA Applied Engineering Research, 10 (14), pp. 34137-34139.
16. Murali, A., Hari Kishore, K., Rama Krishna, C.P., Kumar, S., Trinadha
can be done using Open Timer software which is an open
Rao, A. Integrating the reconfigurable devices using slow-changing key
source high performance timing analysis tool, introduced by technique to achieve high performance (2017) Proceedings - 7th IEEE
Tsung-Wei Huang [9]. International Advanced Computing Conference, IACC 2017, art. no.
7976849, pp. 530-534.
17. Surendar, K. H. Kishore, M. Kavitha, A. Z. Ibatova, V. Samavatian
VII. CONCLUSION
“Effects of Thermo-Mechanical Fatigue and Low Cycle Fatigue
In this paper reg2reg setup and hold analysis for an example Interaction on Performance of Solder Joints” IEEE Transactions on
Device and Materials Reliability, P-ISSN: 1530-4388, E-ISSN: 1558-
circuit is described and circuits for detection and correction 2574, Vol No: 18, Issue No: 4, Page No: 606-612, December-2018
circuits are observed by associating sequential circuits to 18. N Bala Dastagiri K Hari Kishore “A 14-bit 10kS/s Power Efficient 65nm
them. Before going to fabrication step, STA including OCV SAR ADC for Cardiac Implantable Medical Devices” International
derates helps to avoid timing violations such as setup and hold Journal of Engineering and Technology (UAE), ISSN No: 2227-524X,
Vol No: 7, Issue No: 2.8, Page No: 34-39, March 2018.
time violations. Setup violation makes the chip operate under 19. N Bala Dastagiri, Kakarla Hari Kishore "Reduction of Kickback Noise in
reduced frequency while hold violation makes the chip doesn’t Latched Comparators for Cardiac IMDs” Indian Journal of Science and
run at all. These violations make the circuit go into metastable Technology, ISSN No: 0974-6846, Vol No.9, Issue No.43, Page: 1-6,
stage. November 2016.
20. N Bala Dastagiri, K Hari Kishore "Analysis of Low Power Low Kickback
Noise in Dynamic Comparators in Pacemakers” Indian Journal of Science
REFERENCES and Technology, ISSN No: 0974-6846, Vol No.9, Issue No.44, page: 1-4,
November 2016.
1. Roozbeh Abdollahi, Khayrollah Hadidi,and Abdullah Khoei, “A Simple
21. Meka Bharadwaj, Hari Kishore "Enhanced Launch-Off-Capture Testing
and Reliable System to Detect and Correct Setup/Hold Time Violations in
Using BIST Designs” Journal of Engineering and Applied Sciences, ISSN
Digital Circuits”, IEEE transactions on circuits and systems—i: regular
No: 1816-949X, Vol No.12, Issue No.3, page: 636-643, April 2017.
papers, vol. 63, no. 10, October 2016.
22. Dr. Seetaiah Kilaru, Hari Kishore K, Sravani T, Anvesh Chowdary L,
2. M.Hashimoto, J. Yamaguchi, and T. Sato et al., “Timing analysis
Balaji T “Review and Analysis of Promising Technologies with Respect
considering temporal supply voltage fluctuation,” in Proc. Asia and South
to fifth Generation Networks”, 2014 First International Conference on
Pacific Design Automation Conf. (ASP-DAC 2005), Jan. 18–21, 2005,
Networks and Soft Computing,ISSN:978-1-4799-3486-7/14,pp.248-
vol. 2, pp. 1098–1101.
251,August 2014.
3. Y.-S. Su, W.-K. Hon and C.-C. Yang et al., “Clock skew minimization in
23. P Bala Gopal, K Hari Kishore, R.R Kalyan Venkatesh, P Harinath
multi-voltage mode designs using adjustable delay buffers,” IEEE
Mandalapu “An FPGA Implementation of On Chip UART Testing with
Trans.Comput.-Aided Des. Integr. Circuits Syst., vol. 29, no. 12, pp.
BIST Techniques”, International Journal of Applied Engineering
1921–1930,Dec. 2010.
Research, ISSN 0973-4562, Volume 10, Number 14 , pp. 34047-34051,
4. C.-C. Kao and K.-C. Lin, “Clock skew minimization with adjustable
August 2015.
delay buffers restriction,” in Proc. IEEE Int. Symp. Next-Generation
24. Avinash Yadlapati, Hari Kishore Kakarla “Design and Verification of
Electron.(ISNE), Feb. 25–26, 2013, pp. 321–324.
Asynchronous FIFO with Novel Architecture Using Verilog HDL”
5. W.-P. Tu, S.-H. Huang, and H.-H. Lu, “PVT-variations-tolerant clock
Journal of Engineering and Applied Sci ences , ISSN No: 1816-
design using self-correcting adjustable delay buffers,” in Proc. 2014
949X, Vol No: 14, Issue No: 1, Page No: 159-163, January 2019.
Int.Symp. Next-Generation Electron. (ISNE), May 7–10, 2014, pp. 1–2.
25. K.Sarath Chandra, K Hari Kishore “Electrical Characteristics of Double
6. K.-H. Lim, D. Joo, and T. Kim, “An optimal allocation algorithm of
Gate FINFET under Different Modes of Operation” International Journal
adjustable delay buffers and practical extensions for clock skew
of Innovative Technology and Exploring Engineering, ISSN: 2278-3075,
optimization in multiple power mode designs, ”IEEE Trans.Comput.-
Volume-8, Issue No: 6S, Page No: 172-175, April 2019.
Aided Des. Integr. Circuits Syst., vol. 32, no. 3, pp. 392–405, Mar. 2013.
26. Avinash Yadlapati, K Hari Kishore “Implementation of Asynchronous
7. K. Chae and S. Mukhopadhyay, “A dynamic timing error prevention
FIFO using Low Power DFT” International Journal of Innovative
technique in pipelines with time borrowing and clock stretching,” IEEE
Technology and Exploring Engineering, ISSN: 2278-3075, Volume-8,
Trans. Circuits Syst. I, Reg. Papers, vol. 61, no. 1, pp. 74–83, Jan. 2014.
Issue No: 6S, Page No: 152-156, April 2019.
8. https://www.udemy.com/vlsi-academy-sta-
27. Mahesh Madavath, K Hari Kishore “RF Front-End Design of Inductorless
checks/learn/lecture/5034088#overview.
CMOS LNA Circuit with Noise Cancellation Method for IoT
9. Tsung-Wei Huang and Martin D. F.Wong,“ Open Timer:A High-
Applications” International Journal of Innovative Technology and
Performance Timing Analysis Tool”, Special Session Paper: Incremental
Exploring Engineering, ISSN: 2278-3075, Volume-8, Issue No: 6S, Page
Timing and CPPRAnalysis,978-1-4673-8388-2/15/$31.00 ©2015 IEEE.
No: 176-183, April 2019.
10. Yadlapati, A., Kakarla, H.K. An Advanced AXI Protocol Verification
28. P.Ramakrishna, M. Nagarani, K Hari Kishore “A Low Power 8-Bit
using Verilog HDL (2015) Wulfenia, 22 (4), pp. 307-314.
Current-Steering DAC Using CMOS Technology” International Journal
11. Bindu Bhargavi, K., Hari Kishore, K. Low Power Bist on Memory
of Innovative Technology and Exploring Engineering, ISSN: 2278-3075,
Interface Logic (2015) International Journal of Applied Engineering
Volume-8, Issue No: 6S, Page No: 137-140, April 2019.
Research, 10 (8), pp. 21079-21090.
12. Charan, N.S., Kishore, K.H. Recognization of delay faults in cluster based
FPGA using BIST (2016) Indian Journal of Science and Technology, 9
(28).

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