International Journal of Engineering Research & Technology (IJERT)

ISSN: 2278-0181
Vol. 2 Issue 6, June - 2013

VLSI Implementation of Digital Image Watermarking

Rahate Kunal B. Dr. A. S. Bhalchandra S. S. Agrawal

PG student Professor Assistant Professor

Dept. of Electronics and Dept. of Electronics and Dept. of Electronics and
Telecommunication Telecommunication Telecommunication
Govt. College of Govt. College of Govt. College of
Engineering. Engineering.. Engineering..

Aurangabad(M.S.) Aurangabad(M.S.) Aurangabad(M.S.)

Abstract is very helpful in hiding the secret messages or

The process of Digital watermark embeds the information in the digital media. Using
data called watermark in digital media like image, watermarking the people can keep their work
video audio file etc so that the owner can claim for copyrighted. The watermarking algorithm
rights. This paper presents invisible fragile incorporates the watermark in the object, whereas
watermarking algorithm and watermark retrieval the verification algorithm authenticates the object
algorithm along with copyright protection by determining the presence of the watermark and
provision. The algorithms are implemented in its actual data bits [2] [3].
RT

spatial domain. The pixel wise manipulation of the Watermark has various forms like text value,
image to be watermarked (base image) is done in image, video and audio clip. Watermarking
accordance with the pixel values of the watermark. technique has some properties to be defined like
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The paper represents the complete software robustness, security, complexity, verification etc.
implementation of both the algorithms and the Robustness is important property because it defines
hardware implementation of the same is done on the survival of watermark in watermarked digital
Spartan3 FPGA. Several attempts have been made media after going through operations like filtering
to achieve low power, low area and high lossy compression or some kind of geometric
performance. For low and optimized area, the IP modification. The attacks on watermarked media
cores of block ROM and division generator are can sometimes lead to removal of watermark. To
used. The task of providing input to the board from avoid such things the improved watermark
PC and getting results from the board to the PC insertion key should be used, such things are taken
are done using serial communication through care by means security. The time required for the
UART protocol. algorithm to embed the watermark in to digital
media and also its retrieval defines the complexity
1. Introduction of watermarking.
The watermarking system can be implemented
One of the ways to protect the intellectual with either software or hardware. Software
property rights of the digital media is digital implementation of watermarking is large whereas
watermarking. With rapid increase in use of hardware implementation is lacking [4]. Generally,
internet and digital media, transmission and hardware watermarking scheme can be done by
reproduction of digital products has become very using each of the domains (spatial or frequency).
convenient but it has some drawbacks also. The Due to the simplicity of spatial domain
digital revolution provides tools to unlimited computational overhead and its easiness for its
copying without loss in fidelity [1]. The people can application if compared to the frequency domain,
easily steal the digital work of others like image, the spatial domain is usually preferred for hardware
videos, and audio clips and claim their rights on the implementation [4] [5] [6] [7].
stolen things. This situation creates the need of The paper is organized as follows: Section 2
copyright protection of digital media. Digital describes the proposed algorithm. Sections 3 and4
watermarking can be used for content describe VLSI design of the embedding unit and
authentication, detection of illegal duplication and the decoding unit respectively using FPGA.
alteration, secret communication as watermarking

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 International Journal of Engineering Research & Technology (IJERT)
ISSN: 2278-0181
Vol. 2 Issue 6, June - 2013

Sections 5 and 6 present results and conclusion 2.2. Watermark Retrieval Algorithm
respectively.
The watermarked image quality is maintained
by only modifying 3LSBs out of 8 bits of base
2. Proposed Scheme for Watermarking image. To extract watermark, these modified bits
are required. Following steps explains the retrieval
2.1. Algorithm for Watermark Insertion algorithm.
1) Set every bit of every pixel to zero except
3LSBs.
Digital image watermarking can be done in both
2) Shift right every pixel by 3 times.
spatial domain and frequency domain but the most
3) The resultant image is the original watermark
straight forward fundamental and simplest schemes
which was initially used to embed into the base
for digital image watermarking can be implemented
image.
in frequency domain because of the less
complexity. Such types of techniques deal with
modification of luminance value of pixels in
spatial domain. In this paper the most common 3. VLSI Architecture
technique of watermarking is presented which
involves the manipulation of least significant bits 3.1. Datapath for Watermark Insertion
(LSB) of overall pixels of base image or the image
to be watermarked. Although the spatial domain The datapath is divided in to four parts. First is
watermarking is less complex, but it is not much UART module. This module is responsible for the
robust as compared to the frequency domain PC to FPGA board interface. The second part is
watermarking. [5] [8]. In this paper the watermarking module which mainly consist of two
watermarking of 8 bit gray scale image is RAMs to store the base image and resultant
presented. According to [5] [6] the number of bits watermarked image. It also has and two gates and a
„m‟ in LSB to be modified can be obtained using: shifter. Two intellectual property core (IP Core) are
m = log2 [M × M] (1) also incorporated in datapath. One is for storing the
RT
Where „[M × M]‟ is the size of the base image. watermark and one is „Division Generator‟.
The reason of particularly modifying only LSBs
of the base image is that, the LSBs contains the
least information of the pixel value and such
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manipulation does not hamper the quality of

watermarked image. The number of LSBs to be
modified can be found out using equation (1). In
this paper the base image size is taken as 128X128
and the 3 LSB bits are manipulated of all the pixels
of base image.
To embed the watermark in to the base image
the LSBs of pixels the base image are replaced by
the same number of MSBs of the watermark pixels.
In other words the least information holding bits of
the base image are replaced by the most
information holding bits of the watermark.
The following steps summarises the embedding
algorithm.
1) The size of the base image is obtained and Fig.1: Data path for Invisible Fragile
the 3 LSBs of all the pixels of base image are set to Watermarking
zero. The designing process is carried out in the
2) The size of watermark is obtained and if the Xilinx project navigator 13.2 and the hardware
watermark size is greater, then it is reshaped to the description language used is Verilog. The design is
size of base image. simulated and the waveforms are verified in the
3) Modify the pixels in watermark in such a ISE simulator. Once the designing process is done,
way that the first 3 MSBs are retained and all other the design is ready to implement in the FPGA
bits are set to zero. board. In the simulation, we can provide the image
4) Left shift all the pixels in watermark 3 times. as a input using the Testbench but to provide the
5) Add pixels of base image with the input to FPGA board from PC, some sort of
corresponding pixels of watermark. interface must be provided. Once the input is given
6) The resultant pixels represent the to the FPGA board, the design can be operated and
watermarked image of the base image. the results are stored in block ram. The RAM

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 International Journal of Engineering Research & Technology (IJERT)
ISSN: 2278-0181
Vol. 2 Issue 6, June - 2013

containing the result has to be given to some sort of to one mapping is maintained for the pixels in base
display like LCD screen or VGA monitor to image RAM and the Block ROM for watermark. A
analyze. In this paper the results are transmitted counter is created which holds the value of address
back to the PC and the displayed in MATLAB. The and this address value is given to both the
architecture of watermarking operates by combined memories. The counter value keeps on
action of all the modules. incrementing till all the pixels are processed. First
pixel value from base image RAM is given to the
3.1.1. UART Module: register REG1. AND operation is performed
between REG1 and another register which holds
The base image to be watermarked is first 1111_1000 value in binary. This resets the last 3
converted to the text format in MATLAB. These LSBs of base image pixel. The first 3 MSBs of the
text values represent the actual image. The base watermark pixel are kept intact and rests of the
image is 8 bit image so the pixels values lies pixels are set to zero by passing through another
between 0000_0000 to 1111_1111 (0-255). For the and gate. Successive 3 bit left shifter shifts this
transmission and the reception, RS 232 port of PC pixel value, and added with the pixel value of the
is used UART protocol is used for the serial base image. The resultant pixels is watermarked
transmission of these text values. Any terminal pixels which is stored in another RAM called
software can be used to send the text values to Watermarked image RAM. This RAM also has the
serial port of the PC. UART protocol is same size as that of the Base Image RAM
asynchronous protocol where the carrier is not used (255X255).
hence the start and end of transmission has to be
specified. In this paper the UART module is 3.1.3. IP Core (Block Memory Generator):
designed which works with one start bit and one
stop bit. The IP Core (Intellectual property Core) refers
to preconfigured logic functions that can be used
design. Xilinx provides a wide selection of IP that
is optimized for Xilinx FPGAs. These can include
functions delivered through the Xilinx CORE
RT
The serial input from PC is received at the Generator software, through the Xilinx
FPGA board. The start bit and stop bit are Architecture Wizard, as standalone archives, from
discarded and the 8 bit data (1byte) is accepted. All third parties, through Xilinx Platform Studio
the pixel values are transmitted and the using the
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(XPS), or through System Generator. Xilinx and its

UART module in FPGA the pixel values are partner companies produce IP ranging in
received and stored in the RAM. The UART complexity from simple arithmetic operators and
module generates the enable signals which drives delay elements to complex system-level building
the another modules. blocks, such as Digital Signal Processing (DSP)
The transmission back to PC from FPGA board filters, multiplexers, transformers and memory.
is done using the same UART module. Start bit and Xilinx IP is delivered through the tools called
stop bit are attached to the 8 bit data and this 10bit CORE Generator System which is a design tool
data is serial transmitted back to PC. The respective that delivers parameterized cores optimized for
control signals required for proper operation are Xilinx FPGAs. It provides you with a catalogue of
generated by watermarking module. ready-made functions ranging in complexity from
simple arithmetic operators such as adders,
3.1.2. Watermarking module: accumulators, and multipliers, to system-level
building blocks such as filters, transforms, FIFOs
The proposed system uses he pixel values in and memories.
decimal which means the maximum 3 digits are The CORE Generator System creates
required to present the decimal values from 0 to customized cores which deliver high levels of
255. The serial communication can be used to performance and area efficiency. This is
transfer only one digit at a time. The problem of accomplished by taking advantage of Xilinx‟s core
receiving the multidigit decimal value is solved by friendly FPGA architectures and Xilinx Smart-IP
using the Pixel Value Combiner which combines technology.
the multidigit decimal value and store in the RAM. The CORE Generator System benefits designers
One by one all the pixels are stored in the base by providing the following features:
image RAM. The base image size is 255X255 so • Physical layout optimized for high
to store these many pixels the RAM size is also performance.
kept same as base image size. • Predictable performance and resource
The watermark is stored in the Block ROM IP utilization.
core. The proposed algorithm is this paper works
by manipulating the bits of base image pixels
according to the respective pixel of watermark. One

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 International Journal of Engineering Research & Technology (IJERT)
ISSN: 2278-0181
Vol. 2 Issue 6, June - 2013

• Reduced power requirements achieved and remainder. The width for all the four
through compact design and interconnect parameters is set to 8 bits.
minimization.
• Performance independent of target device size.
• Ability to use multiple instances of the same
core on the same device without deterioration in
performance.
• Reduced compile time compared to competing
architectures.
One of the IP core used in the proposed
architecture is Block Memory generator. The
architecture of watermarking requires two images, Fig. 2 Pin diagram for Division Generator
one is base image and other is the watermark. The
base image is obtained and stored in FPGA RAM 3.2. Datapath to Retrieve Watermark
using serial communication and the watermark is
initially inside the FPGA using Block Memory
generator IP Core.
One of the problems of memory initialisation in
hardware descriptive languages like Verilog and
VHDL is that, the constructs used for such
initialisations are not synthesisable. The Verilog
uses „initial ‟construct which is not synthesisable.
To solve this problem the Block Memory
Generator is used. The Block memory generator
can be initialised with the „.coe‟ file. The
MATLAB software is used to create .coe file of the
watermark.
The specification of block memory used is as
RT
follows
Table 1: Block memory specifications
Interface type native
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Memory type single port ROM

Algorithm to concatenate minimum area Fig.3: Datapath for Watermark Extraction
Block RAM primitives
The watermark retrievals architecture is
Memory size Read-width-8 bits presented in figure 3. The watermarked image
Read-depth which is obtained using watermarking algorithm is
255x255 transmitted using the same serial communication
standard and UART protocol. The Block memory
3.1.4. IP Core Division Generator: generator is removed as no need to store any
watermark. Only two RAMs are implemented
The Pixel Decombiner module is incorporated using block ram inference. The architecture for
with the Division Generator. The pixel value in watermark extraction lacks one and operation and
RAM for watermarked image varies from 1 digit to only one right shifter is required. Rest of the
maximum 3 digits as the pixel value is in decimal operation (providing input and taking output out)
(0-255). The UART module is capable of are same.
transmitting only one digit at a time. This requires
dividing the multi digit pixel value into single
digits and transmitting each digit individually. 4. Synthesis and Implementation
Division operation is most difficult out of four
arithmetic operations in VLSI domain as it includes The complete RTL schematic of the embedding
shifting the pixel bits in right side. This means the watermark top module is presented in figure 4.
division only with value which is power of 2 is The datapath for image watermarking module
possible and division with other values is only shown in fig 3 consist of mainly four blocks. Each
allowed for simulation but not for synthesis. block is designed separately and all the four blocks
This problem is solved using Division are brought in single top module to work together.
Generator, which accepts two input as „dividend‟ The RTL schematic shows all the four blocks in a
and „divisor‟, and produces two output as quotient single top module. The chip is modelled using a

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 International Journal of Engineering Research & Technology (IJERT)
ISSN: 2278-0181
Vol. 2 Issue 6, June - 2013

Verilog and functional simulation was performed. image size is kept 64X64 and so the size of
The code was synthesized on Spartan 3 technology watermark is also kept same. For the bigger image
on xc3s200-4tq144 device using ISE Project sizes, like 256X256 and 512X512 design works
Navigator (0.61xd) from Xilinx. The clock 50MHz properly but with increased memory size and
was given to the Spartan 3 board. The device extended hardware requirements. The simulation
utilization summary is given in Table 2. results include the complete waveforms
representation of all the signals included in top
module for embedding watermark. The input for
UART module is „rx‟ which receives the bit stream
of the image pixels serially. Two other signals
namely „is_receiving‟ and „recv_error‟ works as a
status signals for reception of image pixels from
PC. The transmission of the image pixels from PC
to FPGA board continues till the inferred RAM
dedicated to store the base image is full. Once the
base image RAM is fully stored the appropriate
control signals are generated which initializes the
watermarking process. The watermarking process
involves interaction of image processing block and
the IP core which stores the watermark.
Appropriate address is placed on the address of IP
core block ROM to get pixel value of watermark.
The processed pixel is sent back to UART module
for transmission and the respective control signals
are activated for transmission. The transmission of
the watermarked pixel from FPGA to PC is done
through the hardware pin named „tx‟. The other
signal which is associated with transmission is
RT
„is_transmitting‟ which represents the status of
transmission. The digits in the pixel value are
Fig. 4: RTL schematic of top module for broken in to individual digits and each digit is
watermark insertion
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transmitted individually. This is happening because

of the use of Pixel Digit Decombiner. The
Table 2: Device Utilization Summary simulation results are shown in fig4.
Logic Utilization Used Available Utilization

Number of Slices 690 1920 35%

Number of Slice
552 3840 14%
Flip Flops

Number of 4 input
1140 3840 29%
LUTs

Number of bonded
44 97 45%
IOBs

Number of BRAMs 2 12 16%

Number of
1 12 8%
MULT18X18s

Number of GCLKs 1 8 12%

6. Conclusion
5. Simulation Results In this paper, watermarking encoder and the
decoder that can perform invisible fragile
The design is implemented on Spartan 3 FPGA watermarking in spatial domain is presented along
board for the 8 bit gray scale image considering the with VLSI realisation using FPGA with developed
memory capability of the hardware design, the base memory efficient hardware architecture. The

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 International Journal of Engineering Research & Technology (IJERT)
ISSN: 2278-0181
Vol. 2 Issue 6, June - 2013

experimental results showed that the proposed

watermarking scheme is imperceptible and robust
against geometric attacks but fragile against the
filtering and image compressions. Great advantages
are gained due to using IP core hardware based
implementation of watermarking algorithms, such
as block ROM and division generator to reduce
hardware scheme area, decrease power
consumption and increase speed of performance.
Therefore a hardware watermarking solution is
often more reliable and economical.

References

[1]Er-Hsinen, “Literature Survey on Digital Image

Watermarking Watermarking,”EE381K
Multidimentional signal Processing, 8/19/98.

[2] C.C.Chang and J. C. Chuan, “An image intellectual

property protection scheme for gray images using visual
secret sharing strategy,” Pattern Recognition Letters, vol.
23, June 2002, pp. 931- 941.

[3] Pankaj U. Lande,Sanjay N.Talbar and G.N. Shinde

“ROBUST IMAGE ADAPTIVE WATERMARKING
USING FUZZY LOGIC AN FPGA APPROACH”
International Journal of Signal Processing, Image
Processing and Pattern Recognition Vol. 3, No. 4,
December, 2010
RT

[4]S. P. Mohanty, N. Ranganathan, and R. K. Namballa,

“VLSI Implementation of Invisible Digital
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a Secure JPEG Encoder,” in Proc. Of the IEEE

Workshop on Signal Processing Systems, pp. 183-188.
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[5] D. Samanta, A. Basu, T. S. Das, V. H. Mankar, A.

Ghosh, M. Das, and S. K Sarkar. SET Based Logic
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[6]A. Basu, T. S. Das, S. Maiti, N. Islam, and S. K.

Sarkar. FPGA Based Implementation of Robust Spatial
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[7] A. Basu, T. Das, S. Sarkar, A. Roy, and N. Islam.

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[8]J. Pan, H. C. Huang, and L. C. Jain. Intelligent

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