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1 - 30 - VLSI Major Project Titles List 2021

The document lists 30 potential VLSI major project titles organized under different categories such as arithmetic projects, memory projects, cryptography projects, BIST projects, error correction techniques, and backend projects. The titles focus on efficient designs and implementations of arithmetic operations, modular adders, dividers, multipliers, memories, AES encryption, Reed Solomon codes, BIST generators, error correction codes, low power circuits, and other digital components for applications such as DSP, cryptography, wireless sensors, and SRAM.

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366 views3 pages

1 - 30 - VLSI Major Project Titles List 2021

The document lists 30 potential VLSI major project titles organized under different categories such as arithmetic projects, memory projects, cryptography projects, BIST projects, error correction techniques, and backend projects. The titles focus on efficient designs and implementations of arithmetic operations, modular adders, dividers, multipliers, memories, AES encryption, Reed Solomon codes, BIST generators, error correction codes, low power circuits, and other digital components for applications such as DSP, cryptography, wireless sensors, and SRAM.

Uploaded by

Chakhila 123
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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VLSI Major Project Titles List

S.NO TITLES
.

ARTHEMATIC PROJECT

DP1 Design Of Generic Floating Point Pipeline Based Arithmetic Operation For DSP
Processor

DP2 Implementation Of Efficient Modulo 2n Adders For Cryptographic Applications

DP3 Design Of Area Optimized Arithmetic And Logical Unit For Microcontroller

DP4 Efficient Modular Adder Designs Based On Thermometer And One-Hot Coding

DP5 Efficient Operand Divided Hybrid Adder for Error Tolerant Applications

DP6 Area Efficient Memory-Based Even-Multiple-Storage Multiplier For Higher Input

DP7 An Efficient Architecture For Signed Carry Save Multiplication

DP8 A Novel Parameterized Fused Division And Square- Root POSIT Arithmetic
Architecture

DP9 Efficient Design of a Reversible Sorting Circuit in Nanotechnology

DP10 Comparative Study of Test Pattern Generation Systems to Reduce Test Application
Time.

DP11 Design Of High Performance Digital Divider


DP12 Design and synthesis of reversible data selectors for low power application

MEMORY

DP13 2- Dimensional Instant Access Memory Design

CRYPTOGRAPHY PROJECTS

DP14 Implementation Of AES Using Composite Field Arithmetic For Iot Applications

DP15 A Unified Architecture For AES/PRESENT Ciphers And Its Usage In An Soc
Datapoint Info Solutions,Flat No: 101, Sri Sai Rams Swarnalatha Estates, Adjacent line of Saradhi Studio, Sai
Saradhi Nagar, Hyderabad-500016. Ph: 040-48598782. Website: www.datapointinfo.com.
Environment

DP16 VLSI Implementation Of Reed Solomon Codes

DP17 VLSI Implementation Of Turbo Coder For LTE Using Verilog HDL

BIST PROJECTS

DP18 Design Of Modified Dual-CLCG Algorithm For Pseudo-Random Bit Generator

ERROR CORRECTION TECHINQUE

DP19 Fast And Power Efficient SEC-DED And SEC-DED-DAEC Codes In Iot Based
Wireless Sensor Networks

DP20 Solution For Ultra-Low Bit-Error-Rate Interface Of Superconductor-Semiconductor By


Using An Error-Correction-Code Encoder

BACK END PROJECTS

DP21 Low Power Design Of 4-Bit Simultaneous Counter Using Digital Switching Circuits For
Low Range Counting Applications

DP22 Estimation Of Power And Delay Of CMOS Phase Detector And Phase-Frequency
Detector Using Nano Dimensional MOS Transistor

DP23 Reduction Of Power And Delay In Shift Register Using MTCMOS Technique

DP24 VLSI Architecture For High Performance Wallace Tree Encoder

DP25 The Method Of Low Power, High Performance And Area Efficient Address Decoder
Design For SRAM

DP26 Design Of Low Power And High Speed Encoder And Decoder Circuits By Re-
Evaluating High Speed Design Values

DP27 A 27 -1 Low-Power Half-Rate 16-Gb/S Charge-Mode PRBS Generator In 1.2V, 65nm


CMOS

DP28 Design Of A Two-Bit Magnitude Comparator Based On Pass Transistor, Transmission


Gate And Conventional Static CMOS Logic

DP29 Non-Dynamic Power Reduction Techniques For Digital VLSI Circuits: Classification
And Review

DP30 Non-Dynamic Power Reduction Techniques for Digital VLSI Circuits: Classification
Datapoint Info Solutions,Flat No: 101, Sri Sai Rams Swarnalatha Estates, Adjacent line of Saradhi Studio, Sai
Saradhi Nagar, Hyderabad-500016. Ph: 040-48598782. Website: www.datapointinfo.com.
and Review

Datapoint Info Solutions,Flat No: 101, Sri Sai Rams Swarnalatha Estates, Adjacent line of Saradhi Studio, Sai
Saradhi Nagar, Hyderabad-500016. Ph: 040-48598782. Website: www.datapointinfo.com.

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