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CHAPTER 5 LOW-POWER COMPUTING

There are several ways you can reduce the power consumption in your embedded system. The use of low-
power devices is the most obvious place to start. The power consumption of different chips varies
considerably, and there are many low power variants of common devices available. RISC processors often
have lower power consumption than comparable CISC processors, so they are often used in preference to
CISC in low-power applications. The PIC and AVR microcontrollers can have current draws of less than 5
mA (and as low as 10 nA when in sleep mode). This is considerably less than the 35 mA used by a 68HC11
microcontroller.
Many memory chips and peripherals will automatically enter a low-power mode when they are not in use.
Others may be placed in low-power mode by toggling a digital input or by an appropriate software
command. The power consumption of some devices can be reduced even further by turning them off when
not in use. If the processor is executing code from RAM and outputting data to a serial port, then the power
to the ROMs and any other I/O devices may be turned off since they are not in use. Implementing this
requires separate power sources for the chips that are to be disabled, switched via software control. Some
voltage regulators (discussed in the next section) have shutdown inputs, allowing the subsystem they are
powering to be turned off.
Further, some low-power devices (such as sensors) may need very little current, so little that they can be
directly powered from the I/O line of a microcontroller. The I/O signal is the power supply for the device.
The devices can be turned on or off under software control by toggling the I/O line. Some processors, such
as the PIC and AVR, can sink relatively large currents (20 mA) through their I/O pins, and these can be
used as ground for some devices (such as LEDs).

5.1 SOURCES OF ENERGY CONSUMPTION

“Power is considered as the most important constraint in embedded systems.”
“Power demands are increasing rapidly, yet battery capacity cannot keep up.”

Power and Energy are related

In many cases, faster execution also means less energy, but the opposite may be true if power has to be
increased to allow faster execution.
Low Power vs. Low Energy

Minimizing the power consumption is important for

The design of the power supply

The design of voltage regulators
The dimensioning of interconnect
Cooling (short term cooling)
• High cost (estimated to be rising at $1 to $3 per Watt for heat dissipation [Skadron et al. ISCA
2003])
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• Limited space
Minimizing the energy consumption is important due to
restricted availability of energy (mobile systems)
limited battery capacities (only slowly improving)
very high costs of energy (solar panels, in space)
long lifetimes, low temperatures

Main sources:
Dynamic power consumption
• charging and discharging capacitors
Short circuit power consumption
• Short circuit path between supply rails during switching
Leakage
• leaking diodes and transistors
• becomes one of the major factors due to shrinking feature sizes in semiconductor technology

5.2 INSTRUCTION-LEVEL STRATEGIES FOR POWER MANAGEMENT

[A] Low Power vs. Low Energy

Heat-Limited application (HLA): Low Power

power supply

Heat depends on power consumption

600 MHz Alpha: 109.0 W @ 2.30V Vdd
Energy-Limited application (ELA): Low Energy
Battery life depends on energy consumption (mobile system)

High costs
Limited space
[B] Energy-efficient System Design

[C] System Design Stage

Power reduction techniques
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1. Static power consumption

2. Dynamic power consumption
3. Leakage current

1. Voltage scaling
2. Clock gating
3. Dynamic Voltage Scaling and Dynamic Frequency Scaling

1. CPU power consumption

2. Cache organization
3. Memory

1. Instruction level power analysis

[D] System Management
Digital system during their operation
System-level software
1. Manages and controls the HW platform, including peripherals
2. Was not designed originally with energy efficiency in mind
3. Some support for low-power execution was introduced only recently
The main purpose of this design phase
To equip the system with an energy-efficient runtime support system (Dynamic Power
Management)
Turning off (or reducing the performance of) system components when they are idle
[E] DPM (Dynamic Power Management)

Two assumptions

Systems (and their components) experience non-uniform workloads during operation time
It is possible to predict, with a certain degree of confidence, the fluctuations of workloads
Power Manageable Components
Functional units within a chip, a chip, a board, an individual functional block
Managed internally or externally, according to the physical location of the implementation
The physical realization style
Timer, hard-wired controller, software routine
PM (Power Manager)
A control procedure (Policy) based on some observations and/or assumptions about the workload
An example: a simple policy – timeout

[F] Dynamic Power-Management Techniques

Tn: period of inactivity

The actual time spent in the target state + the time spent to enter and exit it
TBE : the break-even time
the minimum inactivity time required to compensate the cost of shutting down a component
☞ Tn ≥ TBE
when does a DPM make a transition to the idle state?
Need to know when the future input event occurs
Predictive techniques
Stochastic control
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5.3 MEMORY SYSTEM POWER CONSUMPTION

[A] Sources of Power Consumption

Embedded system = HW platform + SW

Three major components of a HW platform
Computation units
Communication units
Storage units
Energy-efficient design
The reduction and balance of power consumption in all three constituents
IC components and components with other technologies
We mainly focus on the IC components in this section
SW
Choices of SW implementation affect the energy consumption of the three components
[B] Power consumption in Intel CPUs

Most modern CPUs are designed with power consumption in mind to some degree

5.4 SYSTEM-LEVEL POWER MANAGEMENT

Static techniques are applied at design time.

- Compilation for low power: instruction selection considering their power profile, data placement in
memory, register allocation.

- Algorithm design: find the algorithm which is the most power efficient.

- Task mapping and scheduling.

• Dynamic techniques are applied at run time.

- These techniques are applied at run-time in order to reduce power consumption by exploiting idle or
low-workload periods.

System Level Power Optimization

Three techniques will be discussed:
1. Dynamic power management: a dynamic technique.
2. Task mapping: a static technique.
3. Task scheduling with dynamic power scaling: static & dynamic.
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DPM techniques are used in laptops, personal digital assistants (PDAs), and other portable appliances in
order to shut down or place in stand-by unused devices.
The goal is power saving.
☞ DPM techniques are implemented in the operating system (including Windows 2000 running on
laptops).
☞ The power breakdown for a laptop computer:
- 36% of total power consumed by the display
- 18% by hard-disk
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- 18% by wireless LAN interface

- 7% by keyboard, mouse, etc.
- 21% by digital VLSI circuits.

Changing the power state takes time (several seconds) and extra energy.
• Tsd : shutdown delay
• Twu : wake-up delay
Send the device to sleep only if the saved energy justifies the overhead!
☞ The main Problems:
• Don’t shut down such that delays occur too frequently.
• Don’t shut down such that the savings due to the sleeping are smaller than the power overhead of the sate
changes.
Power Management Policies
• Power management policies are concerned with predictions related to idle periods:
- For shut-down: try to predict how long the idle period will be in order to decide if a shut-down should be
performed.
- For wake-up: try to predict when the idle period ends, in order to avoid user delays due to Twu.
It is quite difficult, and often the wake-up is started simply when a request has arrived.