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Question Paper Code:: Reg. No.

This document provides information for an exam on advanced digital system design, including questions and topics that will be covered. The exam has two parts: Part A consists of 10 short answer questions worth 2 marks each. Part B consists of 5 longer answer questions worth 16 marks each. The questions cover topics such as sequential circuits, state machines, hazards, PLDs, FPGA programming, VHDL modeling and testing.

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1K views2 pages

Question Paper Code:: Reg. No.

This document provides information for an exam on advanced digital system design, including questions and topics that will be covered. The exam has two parts: Part A consists of 10 short answer questions worth 2 marks each. Part B consists of 5 longer answer questions worth 16 marks each. The questions cover topics such as sequential circuits, state machines, hazards, PLDs, FPGA programming, VHDL modeling and testing.

Uploaded by

rameshkarthik1588
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 2

Reg. No.

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Question Paper Code: W7602

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M.E. DEGREE EXAMINATION, JANUARY 2010

First Semester

4
Applied Electronics

AP 9212 — ADVANCED DIGITAL SYSTEM DESIGN

(Common to M.E. VLSI Design)

(Regulations 2009)

Time: Three hours Maximum: 100 Marks

Answer ALL Questions

1
PART A — (10 × 2 = 20 Marks)
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1. What is the difference between a mealy machine and a Moore machine?

2. State two reasons why a state table might be incompletely specified.

3. Define a primitive flow table.


4

4. What is the most important consideration in making state assignments for


asynchronous networks?

5. Define test coverage.

6. What are propagation D-cuts?

7. Differentiate the three basic types of PLD.


1

8. What are the limitations of PLDs using AND OR structure?


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9. Write down the syntax for declaring a package.

10. Define test bench.


4
PART B — (5 × 16 = 80 Marks)

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11. (a) Design a sequential circuit to convert BCD to excess 3 codes. (16)

Or

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(b) A Moore sequential network has one input and one output. The output
should be 1 if the total number of 1’s received is odd and the total number
of 0’s received is an even number greater than 0. Derive the state graph
and table. (16)

4
12. (a) How can essential hazards be determined and eliminated from a
network? (16)

Or

(b) Design a vending machine controller with suitable circuits. (16)

13. (a) Explain the procedure for designing fault-secure PLA with suitable
example. (16)

(b) (i)
1
Or

Explain how the Boolean difference method is used for test


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generation with example. (8)

(ii) Explain the logic diagram of built in logic block observer. (8)

14. (a) Design a 4 bit binary counter using PAL chip. (16)
4

Or

(b) Explain how FPGA can be programmed to implement a finite state


machine. (16)

15. (a) Using structural modeling write a VHDL for a 4 bit shift register. Also
write a test bench for it. (16)

Or
(b) Write a VHDL code for the following circuits:
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(i) 8 : 1 multiplexer (4)


(ii) Serial added using finite state machine approach. (12)
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————————
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2 W 7602

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