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Verilog Project: Verilog Code For ALU

The document describes a Verilog project to design an 8-bit arithmetic logic unit (ALU) and test bench. It includes a module for the ALU that takes 8-bit inputs A and B, a 4-bit selection input to choose the operation, and outputs the 8-bit result and carry flag. The test bench instantiates the ALU, applies different input combinations and selection codes, and checks the outputs over time. It aims to simulate and verify the functionality of the ALU design.

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Syed rohan
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840 views8 pages

Verilog Project: Verilog Code For ALU

The document describes a Verilog project to design an 8-bit arithmetic logic unit (ALU) and test bench. It includes a module for the ALU that takes 8-bit inputs A and B, a 4-bit selection input to choose the operation, and outputs the 8-bit result and carry flag. The test bench instantiates the ALU, applies different input combinations and selection codes, and checks the outputs over time. It aims to simulate and verify the functionality of the ALU design.

Uploaded by

Syed rohan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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PROJECT QUESTION:-

Verilog project: Verilog code for ALU


module alu(

input [7:0] A,B, // ALU 8-bit Inputs

input [3:0] ALU_Sel,// ALU Selection

output [7:0] ALU_Out, // ALU 8-bit Output

output CarryOut // Carry Out Flag

);

reg [7:0] ALU_Result;

wire [8:0] tmp;

assign ALU_Out = ALU_Result; // ALU out

assign tmp = {1'b0,A} + {1'b0,B};

assign CarryOut = tmp[8]; // Carryout flag

always @(*)

begin

case(ALU_Sel)

4'b0000: // Addition

ALU_Result = A + B ;

4'b0001: // Subtraction

ALU_Result = A - B ;

4'b0010: // Multiplication

ALU_Result = A * B;

4'b0011: // Division

ALU_Result = A/B;
4'b0100: // Logical shift left

ALU_Result = A<<1;

4'b0101: // Logical shift right

ALU_Result = A>>1;

4'b0110: // Rotate left

ALU_Result = {A[6:0],A[7]};

4'b0111: // Rotate right

ALU_Result = {A[0],A[7:1]};

4'b1000: // Logical and

ALU_Result = A & B;

4'b1001: // Logical or

ALU_Result = A | B;

4'b1010: // Logical xor

ALU_Result = A ^ B;

4'b1011: // Logical nor

ALU_Result = ~(A | B);

4'b1100: // Logical nand

ALU_Result = ~(A & B);

4'b1101: // Logical xnor

ALU_Result = ~(A ^ B);

4'b1110: // Greater comparison

ALU_Result = (A>B)?8'd1:8'd0 ;

4'b1111: // Equal comparison

ALU_Result = (A==B)?8'd1:8'd0 ;

default: ALU_Result = A + B ;
endcase

end

endmodule

Verilog project: test bench for ALU

// `timescale 1ns / 1ps

module tb_alu;

//Inputs

reg[7:0] A,B;

reg[3:0] ALU_Sel;

//Outputs

wire[7:0] ALU_Out;

wire CarryOut;

// Verilog code for ALU

integer i;

alu test_unit(

A,B, // ALU 8-bit Inputs

ALU_Sel,// ALU Selection


ALU_Out, // ALU 8-bit Output

CarryOut // Carry Out Flag

);

initial

begin

// hold reset state for 100 ns.

A = 8'h0A;

// B = 4'h02;

B = 8'h02;

// ALU_Sel = 4'h0;

ALU_Sel = 4'b0000;

#100

for (i=0;i<=15;i=i+1)

begin

// ALU_Sel = ALU_Sel + 8'h01;

//#10

ALU_Sel = ALU_Sel + 1'b1;

#10;

end

A = 8'hF6;

B = 8'h0A;

end
endmodule
SIMULATION

1. Another window of simulation will appear. Click “Add wave” as shown in figure to
observe the waveforms results.
2. Run simulation from run button as shown in figure

3. Results of the waveforms of outputs of ALU based on input select lines is shown below:

Timing diagram
.

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