L4973V3.3 - L4973V5.

1
 L4973D3.3 - L4973D5.1

3.5A STEP DOWN SWITCHING REGULATOR

UPTO 3.5ASTEP DOWNCONVERTER MULTIPOWER BCD TECHNOLOGY

OPERATING INPUT VOLTAGE FROM 8V TO
55V
3.3V AND 5.1V (±1%) FIXED OUTPUT, AND
ADJUSTABLE OUTPUTS FROM:
0V TO 50V (3.3V type)
5.1V TO 50V (5.1 type)
FREQUENCY ADJUSTABLE UP TO 300KHz POWERDIP (12+3+3) SO20(12+4+4)
VOLTAGE FEED FORWARD
ZERO LOAD CURRENT OPERATION (min ORDERING NUMBERS:
1mA) L4973V3.3 (Powerdip)
L4973D3.3 (SO20)
INTERNAL CURRENT LIMITING (PULSE BY L4973V5.1 (Powerdip)
PULSE AND HICCUP MODE) L4973D5.1 (SO20)
PRECISE 5.1V (1.5%) REFERENCE VOLT-
AGE EXTERNALLY AVAILABLE
INPUT/OUTPUT SYNCHRONIZATION FUNC-
TION
INHIBIT FOR ZERO CURRENT CONSUMP-
TION (100µA Typ. at VCC = 24V) DESCRIPTION
PROTECTION AGAINST FEEDBACK DIS-
The L4973 is a step down monolithic power
CONNECTION switching regulator delivering 3.5A at fixed volt-
THERMAL SHUTDOWN ages of 3.3V or 5.1V and using a simple external
OUTPUT OVERVOLTAGE PROTECTION divider output adjustable voltage up to 50V.
SOFT START FUNCTION Realized in BCD mixed technology, the device
TYPICAL APPLICATION CIRCUIT (POWERDIP)

VCC (8V to 55V)

7 8 10 12
CBOOT
ROSC
9
1
L4973 VO(3.3V or 5.1V)
CIN C2 4,5,6, 3
L1
13,14,15 16 17 11 2

RCOMP
COSC CSS D1 COUT

CCOMP

D97IN554A

April 2000 1/16

L4973V3.3 - L4973V5.1 - L4973D3.3 - L4973D5.1

uses an internal power D-MOS transistor (with a verter includes pulse by pulse current limit, hiccup
typical Rdson of 0.15ohm) to obtain very high effi- mode for output short circuit protection, voltage
ciency and very fast switching times. feed forward regulation, soft start, input/output
Switching frequency up to 300KHz are achievable synchronization, protection against feedback loop
(the maximum power dissipation of the packages disconnection, inhibit for zero current consump-
must be observed). tion and thermal shutdown.
A wide input voltage range between 8V to 55V Packages available are in plastic dual in line, DIP-
and output voltages regulated from 3.3V to 40V 18 (12+3+3) for standard assembly, and SO20
cover the majority of the today applications. (12+4+4) for SMD assembly.
Features of this new generation of DC-DC con-

PIN CONNECTIONS (Top view)

OSC 1 18 SYNC OSC 1 20 SYNC

OUT 2 17 SS OUT 2 19 SS

OUT 3 16 V5.1 OUT 3 18 V5.1

GND 4 15 GND GND 4 17 GND

GND 5 16 GND
GND 5 14 GND
GND 6 15 GND
GND 6 13 GND
GND 7 14 GND
VCC 7 12 VFB
VCC 8 13 VFB
VCC 8 11 COMP VCC 9 12 COMP
BOOT 9 10 INH BOOT 10 11 INH
D94IN162A D94IN163A

POWERDIP (12+3+3) SO20 (12+4+4)

BLOCK DIAGRAM

INH V5.1 VCC VCC

10(11) 16(18) 7(8) 8(9)

CBOOT
CHARGE

ZERO CURRENT VREF INTERNAL

INTERNAL 5.1V
INHIBIT GOOD 5.1V SUPPLY
REFERENCE
3.3V

17(19) SOFT HICCUP CURRENT

SS
START LIMITING

11(12)
COMP
THERMAL CURRENT
SHUTDOWN LIMITING
5.1V BOOT
3.3V + R Q 9(10)
E/A -
VFB - PWM S Q
12(13) +

SYNC OSCILLATOR
18(20)
DRIVER
4,5,6,13,14,15
1(1) (4,5,6,7,14,15,16,17) 2(2) 3(3)
OSC GND OUT OUT D94IN161B

Pin x = Powerdip
Pin (x) = S020

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 L4973V3 - L4973V5 - L4973D3 - L4973D5

THERMAL DATA
Symbol Parameter Powerdip SO20 Unit
Rth(j-pin) Thermal Resistance Junction to pin Max. 12 15 °C/W
Rth(j-amb) Thermal Resistance to Ambient Max. 60 (*) 80 (*) °C/W
(*) Package mounted on board.

ABSOLUTE MAXIMUM RATINGS

Symbol
Parameter Value Unit
DIP-18 S0-20
V7,V8 V9,V8 Input voltage 58 V
V2,V3 V2,V3 Output DC voltage -1 V
Output peak voltage at t = 0.1µs f=200KHz -5 V
I2,I 3 I2,I3 Maximum output current int. limit.
V9-V8 V10-V8 14 V
V9 V10 Bootstrap voltage 70 V
V11 V12 Analogs input voltage (VCC = 24V) 12 V
V17 V19 Analogs input voltage (VCC = 24V) 13 V
V12 V13 (VCC = 20V) 6 V
-0.3 V
V18 V20 (VCC = 20V) 5.5 V
-0.3 V
V10 V11 Inhibit Vcc V
-0.3 V
Ptot Power dissipation a Tpins ≤ 90°C DIP 5 W
(Tamb = 70°C no copper area) 12+3+3 1.3 W
(Tamb = 70°C 4cm copper area on PCB) 2 W
Power dissipation a Tpins = 90°C SO20 4 W
TJ,TSTG Junction and storage temperature -40 to 150 °C

PIN FUNCTIONS
Powerdip SO20 NAME DESCRIPTION
11 12 COMP E/A output to be used for frequency compensation
10 11 INH A logic signal (active high) disables the device (sleep mode operation).
If not used it must be connected to GND; if floating the device is disabled.
9 10 BOOT A capacitor connected between this pin and the output allows to drive the
internal D-MOS.
18 20 SYNC Input/Output synchronization.
7,8 8,9 Vcc Unregulated DC input voltage
2,3 2,3 OUT Stepdown regulator output.
12 13 VFB Stepdown feedback input. Connecting the output directly to this pin results
in an output voltage of 3.3V for the L4973V3.3 and 5.1V. An external
resistive divider is required for higher output voltages. For output voltage
less than 3.3V, see note ** and Figure 32.
16 18 V5.1 Reference voltage externally available.
4,5,6 4,5,6,7 GND Signal ground
13,14,15 14,15,16,17
1 1 OSC An external resistor connected between the unregulated input voltage and
Pin 1 and a capacitor connected from Pin 1 to ground fixes the switching
frequency. (Line feed forward is automatically obtained)

3/16
L4973V3.3 - L4973V5.1 - L4973D3.3 - L4973D5.1

ELECTRICAL CHARACTERISTICS ( Refer to the test circuit,VCC = 24V; Tj = 25°C, COSC = 2.7nF;
ROSC = 20KΩ; unless otherwise specified) • = specifications referred to TJ from 0 to 125°C.
Symbol Parameter Test Conditions Min. Typ. Max. Unit
DYNAMIC CHARACTERISTICS
Input Voltage Range (*) VO = VREF to 40V; IO = 3.5A • 8 55 V

Output Voltage IO = 1A 5.05 5.1 5.15 V

L4973V5.1 IO = 0.5A to 3.5A 5.00 5.1 5.20 V
VCC = 8V to 55V • 4.95 5.1 5.25 V
Output Voltage IO = 1A 3.326 3.36 3.393 V
L4973V3.3 IO = 0.5A to 3.5A 3.292 3.36 3.427 V
VCC = 8V to 40V • 3.26 3.36 3.46 V
R DSON VCC = 10.5V 0.15 0.22 Ω
IO = 3.5A • 0.35 Ω
Maximum Limiting Current VCC = 8V to 55V • 4 4.5 5.5 A
η Efficiency VO = 5.1V; IO = 3.5A 90 %
VO = 3.3V; IO = 3.5A 85 %
Switching Frequency • 90 100 110 KHz
Supply Voltage Ripple Vi = VCC +2VRMS 60 dB
Rejection VO = Vref; IO = 1A; fripple = 100Hz
∆fsw Switching Frequency Stability VCC = 8V to 55V 2 5 %
vs, Supply Voltage
REFERENCE SECTION
Reference Voltage 5.025 5.1 5.175 V
Iref = 0 to 20mA; • 4.950 5.1 5.250 V
VCC = 8 to 55V
Line Regulation Iref = 0mA; 5 10 mV
VCC = 8 to 55V
Load Regulation Vref = 0 to 5mA; 2 10 mV
VCC = 0 to 20mA 6 25 mV
Short Circuit Current 30 65 100 mA
SOFT START
Soft Start Charge Current 30 45 60 µA
Soft Start Discharge Current 15 22 30 µA

INHIBIT
High Level Voltage • 3.0 V
Low Level Voltage • 0.8 V
Isource High Level VINH = 3V • 10 16 50 µA
Isource Low Level VINH = 0.8V • 10 15 50 µA
DC CHARACTERISTICS
Total Operating Quiescent Duty Cycle = 50% 4 6 mA
Current
Quiescent Current Duty Cycle = 0 2.7 4 mA
Total stand-by quiescent VCC = 24V; VINH = 5V 100 200 µA
current VCC = 55V; VINH = 5V 150 300 µA
ERROR AMPLIFIER
High Level Output Voltage 11.0 V
Low Level Output Voltage 0.65 V
Source Bias Current 1 2 3 µA
Source Output Current 200 300 600 µA

4/16
 L4973V3 - L4973V5 - L4973D3 - L4973D5

ELECTRICAL CHARACTERISTICS (continued)

Sink Output Current 200 300 µA

Supply Voltage Ripple VCOMP = VFB 60 80 dB
Rejection CREF =4.7µF 1-5mA load
current
DC Open Loop Gain RL = ∞ 50 60 dB
Transconductance Icomp = -0.1 to 0.1mA; 2.5 mS
Vcomp = 6V
OSCILLATOR SECTION
Ramp valley 0.78 0.85 0.92 V
Ramp peak VCC = 8V 1.9 2.1 2.3 V
VCC = 55V 9 9.6 10.2 V
Maximum Duty Cycle 95 97 %
Maximum Frequency Duty Cycle = 0%; R OSC = 500 KHz
13KΩ; COSC = 820pF;

SYNC FUNCTION
High Input Voltage VCC = 8V to 55V 3.5 V
Low Input Voltage VCC = 8V to 55V 0.9 V
Slave Sink Current 0.15 0.25 0.45 mA
Master Output Amplitude Isource = 3mA 4 4.5 V
Output Pulse Width no load, Vsync = 4.5V 0.20 0.35 µs

(*) Pulse testing with a low duty cycle.

(**) The maximum power dissipation of the package must be observed.

Figure 1. Evaluation Board Circuit

VCC
(DIP18)
R2
7,8
12
1
9
17 L4973 C8
C1 C2 C7 L1 VO
16 4,5,6 2,3
11 10 13,14,15
R3

3x
C3 C4 C5 D1 C0 C12
R1
C6
R4

D97IN515B
C1=1000µF/63V
C2=220nF/63V
C3=470nF L4973 V3.3 L4973 V5.1
C4=1µF/50V
C5=220pF VO(V) R3(KΩ) R4(KΩ) VO(V) R3(KΩ) R4(KΩ)
C6=22nF 3.3 0 5.1 0
C7=2.7nF
C8=220nF/63V 5.1 2.7 4.7 12 6.2 4.7
C0=100µF/40V(C9,C10,C11) 12 12 4.7 15 9.1 4.7
C12=Optional (220nF)
L1=150µH KOOLµ 77310 - 40 Turns - 0.9mm 15 16 4.7 18 12 4.7
R1=9.1K 18 20 4.7 24 18 4.7
R2=20K
D1=GI SB560 24 30 4.7

5/16
L4973V3.3 - L4973V5.1 - L4973D3.3 - L4973D5.1

Typical Performance (Using Evaluation Board) fsw = 100kHz

Output Line Regulator Load Regulator
Output Voltage Efficiency
Ripple Io = 3.5A VCC = 8 to 50V VCC =35V IO = 1 to 3.5A
3.3V 20mV 81.5 (%) 3mV 6mV
5.1V 20mV 86.7 (%) 3mV 6mV
12V 30mV 93.5 (%) 3mV (VCC =15 to 50V) 4mV

Figure 1a: Evaluation Board (Components Side)

Figure 1b: Evaluation Board (Solder Side)

6/16
 L4973V3 - L4973V5 - L4973D3 - L4973D5

Figure 1c: Application Circuit (see fig. 1 part list)

VCC INH SYNC

R2
7,8 10 18 9
C8
1
17 L4973V5.1
C1 C2 C7 L1 Vo
16 4,5,6 2,3
11 13,14,15 12

C3 C4 C5 D1 3x C12
R1 C0
C6

D97IN665A

Figure 1d: Application Circuit (see fig. 1 part list)

VCC INH SYNC

R2
7,8 10 18 9
C8
1
17 L4973V3.3
C1 C2 C7 L1 Vo
16 4,5,6 2,3
11 13,14,15 12

C3 C4 C5 D1 3x C12
R1 C0
C6

D97IN664A

Figure 2: Quiescent Drain Current vs. Input Figure 3: Quiescent Drain Current vs. Junction
Voltage (0% Duty Cycle) Temperature

Ibias D97IN633A Ibias D97IN634

(mA) (mA)
200KHz-R2=22K 200KHz-R2=22K
C7=1.2nF
C7=1.2nF
5.0
Tamb=25°C
0% DC
4.5 4.0

100KHz-R2=20K
4.0 C7=2.7nF
100KHz-R2=20K
C7=2.7nF 3.5
0% DC
3.5 VCC = 35V
0Hz
3.0
3.0
0Hz
2.5

2.0 2.5
0 10 20 30 40 50 VCC(V) -50 0 50 100 Tj(°C)

7/16
L4973V3.3 - L4973V5.1 - L4973D3.3 - L4973D5.1

Figure 4: Stand by Drain Current vs. input Figure 5: Reference Voltage vs. Junction
Voltage Temperature (Pin 16)

Ibias D97IN635A VREF D97IN637

(µA) (V)

Vinh = 5V Pin 16

150 5.15

Vcc=35V
25°C
5.1
100
125°C

5.05
50

5.0
0 10 20 30 40 50 VCC(V) -40 -20 0 20 40 60 80 100 Tj(°C)

Figure 6: Reference Voltage vs. Input Voltage Figure 7: Reference Voltage vs. Reference Input
(Pin 16) Current
VREF D97IN636A VREF D97IN638
(V) (V)

Tj=25°C
Pin 16
5.15 5.2

Vcc=40V
5.1 5.1
Vcc=10V

5.05 5.0
Tj=25°C

5.0 4.9
0 10 20 30 40 50 VCC(V) 0 10 20 30 40 50 IREF(mA)

Figure 8: Inhibit Current vs. Inhibit Voltage Figure 9: Line Regulation (see fig. 1)
(Pin 10)
Iinh D97IN651 VO D97IN639A
(µA) (V)

Vcc=35V Tj=0°C
Pin 10
100 5.12
Tj=125°C

5°
C
=2
Tj

50 5.1 Tj=25°C

Tj=125°C

0 5.08 IO = 1A

-50 5.06
0 5 10 15 Vinh(V) 0 10 20 30 40 50 VCC(V)

8/16
 L4973V3 - L4973V5 - L4973D3 - L4973D5

Figure 10: Load Regulation (see fig. 1c) Figure 11: Line Regulation (see fig. 1d)

VO D97IN640 VO D97IN660A
(V) (V)

VCC = 35V 3.35

5.15
Tj=125°C
3.34
Tj=125°C
Tj=25°C
5.1 3.33
Tj=25°C

3.32
5.05
IO = 1A
3.31

5.0 3.3
0 1 2 3 IO(A) 0 10 20 30 40 50 VCC(V)

Figure 12: Load Regulation (see fig. 1d) Figure 13: Switching Frequency vs.R2 and C7
(fig. 1)
fsw D97IN630
VO D97IN661
(KHz)
(V)
VCC = 35V 500 Tamb=25°C

3.35
0.8
2nF
200
3.34 1.2
nF
Tj=125°C 100
2.2n
F
3.33
50 3.3n
F
Tj=25°C
3.32 4.7n
20 F
5.6n
F
3.31 10

3.3 5
0 1 2 3 IO(A) 0 20 40 60 80 R2(KΩ)

Figure 14: Switching Frequency vs. Input Voltage Figure 15: Switching Frequency vs. Junction
temperature (see fig. 1)
fsw D97IN631 fsw D97IN632
(KHz) (KHz)

Tamb=25°C

105 105

100 100

95 95

90 90
0 10 20 30 40 50 VCC(V) -50 0 50 100 Tj(°C)

9/16
L4973V3.3 - L4973V5.1 - L4973D3.3 - L4973D5.1

Figure 16: Dropout Voltage Between pin 7,8 and Figure 17: Efficiency vs. Output Voltage
2,3 (see fig.1)

∆V D97IN643 η D97IN641
(V) (%)

Tj=125°C
98
100KHz
°C
0.6 Tj=
25 96

94
200KHz
0.4 92
Tj=0°C

90
0.2 IO = 3A
88 VCC = 50V

86
0
0 1 2 3 IO(A) 0 10 20 30 40 VO(V)

Figure 18: Efficiency vs. Output Voltage Figure 19: Efficiency vs. Output Current
(Diode STPS745D) ( see fig.1c)

η D97IN642 η D97IN645
(%) (%)
98
VO = 5.1V
100KHz fsw = 100KHz
96 95
Vcc=12V

94 200KHz

92 90 Vcc=24V

90
Vcc=48V
IO = 3A 85
88 VCC = 35V

86
80
0 5 10 15 20 25 30 VO (V) 0 1 2 3 IO(A)

Figure 20: Efficiency vs. Output Current Figure 21: Efficiency vs. Output Current
(see fig.1c) (see fig.1d)
η D97IN646 η D97IN644
(%) (%)

Vcc=12V V O = 3.3V
fsw = 100KHz
90 90
Vcc=24V Vcc=12V

85 85 Vcc=24V

Vcc=48V

80 VO = 5.1V
80 Vcc=48V
fsw = 200KHz

75 75
0 1 2 3 IO (A) 0 1 2 3 IO(A)

10/16
 L4973V3 - L4973V5 - L4973D3 - L4973D5

Figure 22: Efficiency vs. Output Current Figure 23: Power dissipation vs. Input Voltage
(see fig.1d) (Device only) (see fig.1c)

η D97IN662 Pdiss D97IN647A

(%) (W)
VO = 5.1V
fsw = 100KHz
VO = 3.3V
90 fsw = 200KHz
1.5
Vcc=12V IO =3.5A

85
Vcc=24V IO =3A
1.0
80
IO=2.5A
Vcc=48V

0.5 IO =2A
75

70 0
0 0.5 1 1.5 2 2.5 3 3.5 IO (A) 0 10 20 30 40 50 Vcc(V)

Figure 24: Power dissipation vs. Output Voltage Figure 25: Pulse by Pulse Limiting Current vs.
(Device only) Junction Temperature
Pdiss D97IN648 Ilim D97IN652
(W) (A)
3.0
VCC = 35V I O =3.5A 5.2
fsw = 100KHz
2.5
5
2.0 I O=3A

4.8
1.5 IO =2.5A
Vcc=35

1.0 IO =2A
4.6

0.5 I O =1A 4.4

0 4.2
0 5 10 15 20 25 30 V O(V) -40 -20 0 20 40 60 80 100 120 Tj(°C)

Figure 26: Load Transient Figure 27: Line Transient

IO D97IN649 VCC D97IN650

(A) (V)
3 30

2 20

1 10
T
VO VO
2 1
(mV) (mV)
200µs/DIV
I O = 1A
100 f sw = 100KHz
100
T
1 0 2 0

VCC = 35V -100 -100

fsw = 100KHz 1ms/DIV

11/16
L4973V3.3 - L4973V5.1 - L4973D3.3 - L4973D5.1

Figure 28: Source Current Rise and Fall Time, Figure 29: Soft Start Capacitor Selection vs.
pin 2, 3 (See fig1) Inductor and VCC max (ref. AN938)

Lomax D97IN653
(µH)
Css=1µF
Css=820nF
300
fsw = 100KHz

250
Css=680nF
200

Css=470nF
150

100 Css=220nF

50 Css=100nF

0
25 30 35 40 45 50 Vi(V)

Figure 30:Soft Start Capacitor Selection vs. In- Figure 31: Open Loop Frequency and Phase of
ductor and VCC max (ref. AN938) Error amplifier
Lomax D97IN654 GAIN D97IN663
(µH) (dB) Phase
nF
nF

56
68

s=
s=

f sw = 200KHz 50
Cs
Cs

150 GAIN
nF

0 0
47
s=
Cs

100 -50 45
3nF
s=3
Cs
-100 90
50 2nF
=2 Phase
s
Cs
-150 135

0 -200
15 20 25 30 35 40 45 50 Vi(V) 10 102 103 104 105 106 107 108 f(Hz)

Figure 32: 3.5A at VO< 3.3V (see part list fig. 1)

VP R5 R3
1 3.6K 4.7K
1.5 2K 2K R3
VCC INH SYNC VO=3.36-1.74•
2 4.7K 3.6K R5
2.5 7.5K 3.6K
R2 7,8 10 18 9
C8 3 5.1K 1K
1
17 L4973V3.3 L1 Vo
2,3
C1 C2 C7
4,5,6
11 16 13,14,15 12

R5 R3
D1 3x
C3 C5 R1 C0
C4
C6

D97IN666A

12/16
 L4973V3 - L4973V5 - L4973D3 - L4973D5

Figure 33: 12V to 3.3V High Performance Buck Converter (fsw = 200kHz)

INH SYNC

VCC R2
12V±5% 7,8 10 18 9 C8 η
22k
220nF (%)
1
C7 17 L4973V3.3 L1
92
1.2nF
2,3
C1 16 4,5,6 90
560uF-25V 11 13,14,15 12 Vo=3.33V
C2
HFQ Io=3.5A 88
220nF
Panasonic C3 C4 C5
33nF 1uF 220pF R1 D1
C9 86
9k1
470uF-25V
C6 HFQ 84
22nF Panasonic
82

L1 KoolMm 77120- 24 Turns- 0.9mm 80

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Io(A)
D1 STPS1025 D97IN668A

Figure 34: Synchronization Example

VCC2 V CC1 VCC

7,8 7,8 7,8 7,8

18 18
1 18 18 1 1
L4973 L4973 L4973 L4973
4,5,6 4,5,6 4,5,6 4,5,6
13,14,15 13,14,15 13,14,15 1 13,14,15

D97IN669

Figure 35: Multioutput not Isolated (Pin out referred to DIP12+3+3)

V CC INH SYNC

C8 D2 Vo2
R2 7,8 10 18 9
1
17 L4973 n2
C1 C2 C7 L1 Vo1
16 4,5,6 2,3
11 13,14,15 12 n1

C3 C4 C5
R1
D1 C9 C10 C11
C6

n1 + n 2
V O2 = VO1
n1 D97IN667A

PO2 < 20% P O1

13/16
L4973V3.3 - L4973V5.1 - L4973D3.3 - L4973D5.1

mm inch
DIM. OUTLINE AND
MIN. TYP. MAX. MIN. TYP. MAX. MECHANICAL DATA

a1 0.51 0.020

B 0.85 1.40 0.033 0.055

b 0.50 0.020

b1 0.38 0.50 0.015 0.020

D 24.80 0.976

E 8.80 0.346

e 2.54 0.100

e3 20.32 0.800

F 7.10 0.280

I 5.10 0.201

L 3.30 0.130
Powerdip 18
Z 2.54 0.100

14/16
 L4973V3 - L4973V5 - L4973D3 - L4973D5

mm inch OUTLINE AND

DIM.
MECHANICAL DATA
MIN. TYP. MAX. MIN. TYP. MAX.

A 2.35 2.65 0.093 0.104

A1 0.1 0.3 0.004 0.012

B 0.33 0.51 0.013 0.020

C 0.23 0.32 0.009 0.013

D 12.6 13 0.496 0.512

E 7.4 7.6 0.291 0.299

e 1.27 0.050

H 10 10.65 0.394 0.419

h 0.25 0.75 0.010 0.030

L 0.4 1.27 0.016 0.050

SO20
K 0° (min.)8° (max.)

L
h x 45°

B e K A1 C
H

20 11

1 0
1

SO20MEC

15/16
L4973V3.3 - L4973V5.1 - L4973D3.3 - L4973D5.1

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