The following is the path for opening S-Edit tool :

Start  All Programs  Tanner EDA  Tanner V 15  S-Edit V15.0 32 Bit

To do schematic entry , run S-Edit tool

To create a new design : File  New Design

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Enter the design name and give the path where it should be saved.

Example : techlabs_designs is the design folder

C:\Documents and Settings\phanendra\My Documents\Tanner_lab is the target location of

design folder

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Add component libraries. The path for component libraries is given below.

My Documents\Tanner EDA\Tanner Tools v15.0\Process\Generic_250nm

Click add in S-Edit window for adding the libraries and follow the path of process folder.

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Double click all the component libraries under Generic_250nm and add all tanner database files
(.tdb).

To add Spice commands and Spice Elements for setting spic e simulation follow the path.

My Documents\Tanner EDA\Tanner Tools v15.0\Process\Standard Libraries

Now , we need to create a new cell.

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Give a new name for cell

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Scroll mouse for Zoom In and Zoom Out. And to view entire design press home button on
keyboard.

Click on Generic_250nm_Devices folder on libraries

To add any component either drag the component on to the design area (black region
with grids) or click Instance , then Instance Cell pops up where a user can change the
properties . Keeping the icon on the design area , components icon can be placed N
number of times. Either press ESC button on keyboard or Done on Instance Cell window
to stop placing of cells.

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In the same way place PMOS component on the design area.

To Zoom the design area scroll the mouse or press home button on keyboard.

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Now place Vdd and Gnd Instances from the Misc folder under Library.

Now place a DC Voltage and Pulse Voltage source from the Spice Elements folder under Library.

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To place a Voltage Source, Click Spice Elements, Under Spice Elements Click Voltage Source and
then Instance.

To place a DC voltage source, change the interface to DC and edit the voltage value . Click done
only after placing the voltage source on design area.

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To place a Pulse voltage source, change the interface to DC and edit the voltage value . Click
done only after placing the voltage source on design area.

Place Vdd and Gnd even for the voltage sources as shown.

Now place Input and Output ports.

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When an input port is placed, In port window pops up where we can edit the port name , font size
and orientation. Even the port orientation can be changed by pressing r button on key board.

Now we have placed all the components on the design window. And connections are made using
the wire as shown below

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Now we need to set up simulation.

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Now , give the path of library file.

My Documents\Tanner EDA\Tanner Tools v15.0\Process\Generic_250nm\

Generic_250nm_Tech \Generic_250nm.lib

After giving the path of Generic_250nm.lib, add TT as shown below.

My Documents\Tanner EDA\Tanner Tools v15.0\Process\Generic_250nm\

Generic_250nm_Tech \Generic_250nm.lib TT

TT is the corner model used . There are different types of Corner models in .lib file

* TT : Typical model for NMOS & PMOS

* SS : Slow NMOS Slow PMOS model

* FF : Fast NMOS Fast PMOS model

* SF : Slow NMOS Fast PMOS model

Set Transient Analysis as shown below .

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Run Simulation.

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To view waveforms , place PrintVoltage from Spice Commands library.

Now , Run Simulation.

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Waveforms can be viewed on W-Edit tool once Simulation is Run again.

Waveforms can be expanded by clicking Chart  Expand Traces on W-Edit window.

To extract the spice netlist from schematic, go to S-Edit and click the T-Spice option.

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The following spice netlist is extracted from the schematic which contains the information of the
circuit connections across its nodes, analysis setup , voltages applied and type of library used for
simulation.

Save the netlist as inverter_sch.sp

********* Simulation Settings - General Section *********

.lib "C:\Documents and Settings\phanendra\My Documents\Tanner EDA\Tanner Tools
v15.0\Process\Generic_250nm\Generic_250nm_Tech\Generic_250nm.lib" TT
*-------- Devices With SPICE.ORDER == 0.0 --------
***** Top Level *****

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MNMOS_2_5v_1 Out In Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $
$x=4793 $y=3700 $w=414 $h=600
MPMOS_2_5v_1 Out In Vdd Vdd PMOS25 W=3u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=4793 $y=4700 $w=414 $h=600
*-------- Devices With SPICE.ORDER > 0.0 --------
VVoltageSource_2 Vdd Gnd DC 5 $ $x=1800 $y=3800 $w=400 $h=600
VVoltageSource_1 In Gnd PULSE(0 5 0 5n 5n 95n 200n) $ $x=3400 $y=3600 $w=400 $h=600
.PRINT TRAN V(In) $ $x=2850 $y=4350 $w=1500 $h=300 $r=180
.PRINT TRAN V(Out) $ $x=6250 $y=4050 $w=1500 $h=300
********* Simulation Settings - Analysis Section *********
.tran 50n 1u start=0
********* Simulation Settings - Additional SPICE Commands *********
.end

L-EDIT

CMOS Inverter Structure: -

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The following is the path for opening L-Edit tool :

Start  All Programs  Tanner EDA  Tanner V 15  L-Edit V15.0 32 Bit

To do Layout , run L-Edit tool. Follow window pops up.

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Go to File  New

Click Browse  My Documents\Tanner EDA\Tanner Tools v15.0 \Process \Generic_250nm

\Generic_250nm_Tech and add Generic_250nm_TechSetup.tdb file and click ok.

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Go to Cell  New

Name the Cell

Grids spacing can be minimized or maximized using – or + sign

To change the technology Goto setup-> Design

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Select Lambda or microns accordingly and click ok

Before designing layout we need to remember following equations

N Diffusion = N Implant and Active – (1)

P Diffusion = P Implant and Active - (2)

From layer palette, we can select layer then for drawing layer we need to switch at Drawing boxes
as follows

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Now we can start layout designing. We are Taking Example of CMOS Layout design

Background of L-Edit is P-Substrate by default

We need to design PMOS, First draw active

Now draw P Implant over Active with keeping in mind Lambda based design rules

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Now draw poly over it accordingly

Now draw Contact for Active region

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Now draw metal1 around Contact

We have designed source, gate and drain.

Now we have to design bulk by creating a N+ diffusion

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Now we need to put this in N-Well

We can perform DRC (Design Rule Check) at every stage

If we are violating any Design rule then it will be shown in Error verification navigator

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By clicking on the error, the tool points to the error that occur on layout.

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By increasing the poly density area in the layout we can minimize that error. And again run DRC
check.

We need to design Gate contact.

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To define port, go to (A)

We can now find the port name added to gate .

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Similarly we do NMOS layout.

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After connecting NMOS and PMOS , CMOS layout looks like as follows.

Now we can extract netlist by doing some settings

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32
Click options in Setup Extract above, and uncheck all Hiper Verify Options.

Run Extraction, An spice file will open as follows

This netlist is saved as inverter_layout.spc

VVoltageSource_1 Vdd Gnd DC 5

VVoltageSource_2 vin Gnd PULSE(0 5 0 5n 5n 95n 200n)
.PRINT TRAN V(vin)
.PRINT TRAN V(vout)
.tran 1ns 500ns

Final netlist

.lib "C:\Documents and Settings\phanendra\My Documents\Tanner EDA\Tanner Tools

v15.0\Process\Generic_250nm\Generic_250nm_Tech\Generic_250nm.lib" TT

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M1 Vout Vin GND GND_ NMOS25 l=1.95e-006 w=2.55e-006 ad=5.1e-012 as=4.08e-012 pd=9.1e-006
ps=8.3e-006 $(24.65 -272199 26.6 -272197)
M2 Vout Vin VDD VDD PMOS25 l=1.95e-006 w=2.55e-006 ad=5.2275e-012 as=3.9525e-012 pd=9.2e-
006 ps=8.2e-006 $(24.65 -272194 26.6 -272192)

VVoltageSource_1 Vdd Gnd DC 5

VVoltageSource_2 Vin Gnd PULSE(0 5 0 5n 5n 95n 200n)
.PRINT TRAN V(Vin)
.PRINT TRAN V(Vout)
.tran 1ns 500ns
.end

After saving spice file, we can simulate it, W-Edit will invoked and we can check the response:

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 LVS
(Layout Vs Schematic)

We got two output files (one from S-Edit and second from L-Edit), Now we can compare results
by using LVS

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Double click on LVS, and file -> new &

Select file type-> LVS setup, then ok

We need to browse spice netlist files for layout netlist and Schematic netlist

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After including these files, we need to run verification as follows &

Results can be checked from Verification Window.

Both netlists are equal.

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Experiment No. 5:

5. Schematic Entry and SPICE simulation of MOS differential amplifier. Determination

of gain, bandwidth, output impedance and CMRR.

Theory :

A differential amplifier is a type of electronic amplifier that multiplies the difference between

two inputs by some constant factor (the differential gain).

Many electronic devices use differential amplifiers internally. The output of an ideal differential
amplifier is given by:

Where   and   are the input voltages and Ad is the differential gain.
In practice, however, the gain is not quite equal for the two inputs. This means, for instance, that

if   and   are equal, the output will not be zero, as it would be in the ideal case. A more
realistic expression for the output of a differential amplifier thus includes a second term.

Ac is called the common-mode gain of the amplifier.

As differential amplifiers are often used when it is desired to null out noise or bias-voltages that
appear at both inputs, a low common-mode gain is usually considered good.

The common-mode rejection ratio, usually defined as the ratio between differential-mode gain
and common-mode gain, indicates the ability of the amplifier to accurately cancel voltages that
are common to both inputs. Common-mode rejection ratio (CMRR):

In a perfectly symmetrical differential amplifier, Ac is zero and the CMRR is infinite. Note that a
differential amplifier is a more general form of amplifier than one with a single input; by
grounding one input of a differential amplifier, a single-ended amplifier results. An operational
amplifier, or op-amp, is a differential amplifier with very high differential-mode gain, very high
input impedances, and a low output impedance. Some kinds of differential amplifier usually
include several simpler differential amplifiers. For example, an instrumentation amplifier, a fully
differential amplifier, an instrument amplifier, or an isolation amplifier are often built from
several op-amps.

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Differential amplifiers are found in many systems that utilise negative feedback, where one input
is used for the input signal, the other for the feedback signal. A common application is for the
control ofmotors or servos, as well as for signal amplification applications. In discrete electronics,
a common arrangement for implementing a differential amplifier is the long-tailed pair, which is
also usually found as the differential element in most op-amp integrated circuits. A differential
amplifier is used as the input stage emitter coupled logic gates.

Design :

In S-Edit, draw the circuit as shown below.

Convert the schematic to symbol

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Using the lines for drawing, create a symbol for op-amp as below.

Make the connections accordingly.

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Again create a symbol for the above circuit and make the connections accordingly.

Vpwr and Vpwr/2 are the instance name of the voltage souces.

Now place the spice commands for finding out the gain, bandwidth.

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Simulation setup

Then click run simulation

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Gain , Frequency and Bandwidth can be viewed from simulation window above.

And waveforms can be viewed from w-Edit

6th Experiment is already shown in the Tanner working Flow.

7th Experiment is 10 Bit Number Controlled Oscillator.

The following schematic shows 10 bit VCO. By changing the values of D0 – D9 the input pulse
applied varies accordingly.

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