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Using Icarus Verilog

This document provides instructions for using Icarus Verilog, VVP and GTKwave to design and simulate Verilog code. Icarus Verilog can be downloaded and installed, which also installs VVP and GTKwave. Verilog files can be compiled with Icarus Verilog and simulated with VVP. GTKwave can then be used to view the simulation results in waveform format. An example of a full adder circuit and testbench is provided, along with instructions for compiling, simulating and viewing the results.

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234 views

Using Icarus Verilog

This document provides instructions for using Icarus Verilog, VVP and GTKwave to design and simulate Verilog code. Icarus Verilog can be downloaded and installed, which also installs VVP and GTKwave. Verilog files can be compiled with Icarus Verilog and simulated with VVP. GTKwave can then be used to view the simulation results in waveform format. An example of a full adder circuit and testbench is provided, along with instructions for compiling, simulating and viewing the results.

Uploaded by

gaweng
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Using Icarus Verilog, VVP and GTKwave

Icarus verilog (iverilog) can be downloaded from https://bleyer.org/icarus/ and it is included together with
VVP and GTKwave. The latest version is iverilog-v11-20200824-x64_setup.exe [18.0MB]. Once iverilog is
installed, VVP and GTKwave is also installed.
During installation, make sure the option for PATH is ticked. This will enable the verilog compiler being run
from anywhere in the computer.
iverilog and vvp were DOS based programs, some knowledge in dealing with DOS commands is useful.
1. Create a folder anywhere on the computer disk for storing the verilog files. Eg D:\test
2. Create a Verilog file of the circuit you want to design using notepad and save it in the folder. Example
given here is a full adder circuit. The file name is fa.v. The `timescale compiler directive specifies the
time unit and precision for the modules that follow it. If not included, then the time unit is 1 second.
Statements after the // are comments.

//full adder code: structural model


`timescale 1ns/100ps //optional
module fa ( a, b, c, sum, carry);
input a, b, c;
output sum, carry ;
wire s1, c1, c2; //internal
xor(s1, a, b);
xor(sum, s1, c);
and(c2, s1, c);
and(c1, a, b);
or(carry, c1, c2);
endmodule

The fa.v file in the D:\test folder looks like this.

3. To open the D:\test folder in DOS window, highlight the address bar, type cmd and then press enter.

4. The DOS window is will now open. The location is at D:\test.

Mohd Uzir Kamaluddin / September 2020


5. Compile the file fa.v by typing at the DOS prompt D:\test>iverilog fa.v and press enter.

6. If there is syntax error/s, correct it and compile again. No message is displayed when there is no error/s.
When there is no error/s reported, it means that the verilog code for the circuit is correct, but its
functionality is not tested yet. We need to test the circuit for functionality by applying logic signals to its
inputs i.e. a, b, c. This is done by writing a code called the testbench.
The testbench code can be written in a separate file or in the same file with the module code. In this
example the testbench code is written in same file with the module code.

7. Example given is the module with its testbench code and is saved as fa.v.
//full adder code: structural model
`timescale 1ns/100ps //optional
module fa ( a, b, c, sum, carry);
input a, b, c;
output sum, carry ;
wire s1, c1, c2; //internal
xor(s1, a, b);
xor(sum, s1, c);
and(c2, s1, c);
and(c1, a, b);
or(carry, c1, c2);
endmodule

//***Testbench Module***
module testb;
reg a, b, c;
wire sum, carry;
fa uut ( .a(a), .b(b),.c(c), .sum(sum), .carry(carry));
initial
begin
$dumpfile("test1.vcd");
$dumpvars(); //for gtkwave display
$monitor("a=%b, b=%b, c=%b, carry=%b, sum=%b \n", a, b, c, carry, sum);
a=0; b=0; c=0; //input signals for full adder
#10 a=0; b=0; c=1;
#10 a=0; b=1; c=0;
#10 a=0; b=1; c=1;
#10 a=1; b=0; c=0;
#10 a=1; b=0; c=1;
#10 a=1; b=1; c=0;
#10 a=1; b=1; c=1;
#10 a=0; b=0; c=0;
#10 $finish;
end
endmodule

Mohd Uzir Kamaluddin / September 2020


8. Compile again the file fa.v by typing at the DOS prompt D:\test>iverilog fa.v and press enter.
9. If there is syntax error/s, correct it and compile again. No message displayed when there is no error/s.
An output files called a.out and test1.vcd are created in the D:\test folder.

10. To display the tabulated of the input and output signals, type at the DOS prompt D:\test>vvp a.out and
press enter.

Thus we can see the results of the simulation, and we can prove that the circuit works as a full adder.
11. To see the output in waveform format, we use the gtkwave software.
12. Type D:\test>gtkwave test1.vcd. This will open the gtkwave software and the vcd file at the same time.

13. Click the + symbol with the name testb, and then click on uut. All the signals are displayed in the Signals
window below.
14. Select and drag one by one the input and output signals of the full adder circuit, and place it in the
Signals window. The signal waveforms will appear in the Waves window.
15. Click the unzoom button until the signals is displayed properly.

Mohd Uzir Kamaluddin / September 2020


Note: The gtkwave can be launched by typing D:\test>gtkwave and press enter. Then open the vcd
file by: File -> Open New Tab. Navigate to the vcd file and press ok.

The following is the verilog code of a synchronous counter that counts 1-2-3-5-7…. using JK flip-
flops complete with its testbench.

Mohd Uzir Kamaluddin / September 2020


module JK_FF (j, k, clk, reset, q, qb);
output reg q, qb; //flip-flop output must be of type reg
input j, k, clk, reset;
always @ (posedge clk) //flip-flop operates on rising edge of clock
begin
if (reset) begin
q <= 0; //flip-flop is reset (reset=1)
qb <= 1;
end
else begin
if (j!=k) begin //flip-flop is not reset (reset=0)
q <= j;
qb <= k;
end
else if (j==1 && k==1) begin
q <= ~q;
qb <= ~qb;
end
end
end
endmodule

//*****Counter counting 1,2,3,5,7...**********


module counter1(clock, reset, q, qb);
input clock, reset;
output [0:2]q, qb; //3bits wide (must declare output as vector)
wire ja, jc;
and a1(ja, q[1], q[2]);
JK_FF jk0(.j(ja), .k(q[1]), .clk(clock), .reset(reset), .q(q[0]), .qb(qb[0]));
JK_FF jk1(.j(1'b1), .k(q[2]), .clk(clock), .reset(reset), .q(q[1]), .qb(qb[1]));
and a2(jc, qb[0], qb[1]);
JK_FF jk2(.j(1'b1), .k(jc), .clk(clock), .reset(reset), .q(q[2]), .qb(qb[2]));
endmodule

//*********Testbench***********************
module testcount;
reg clock, reset;
wire [0:2]q, qb;
counter1 uut(.clock(clock), .reset(reset), .q(q), .qb(qb));
initial clock=0;
always #1 clock=~clock; //clock for the counter
initial begin
$dumpfile("ctr1.vcd");
$dumpvars(); //for gtkwave
$monitor("Output=%b%b%b", q[0], q[1], q[2]);
reset=1;
#10 reset=0;
#100 $finish;
end
endmodule

Mohd Uzir Kamaluddin / September 2020


Results:

A short view:

The full view:

Thank you.

Mohd Uzir Kamaluddin / September 2020

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