FED-CEC Online Help
FED-CEC Online Help
This manual describes the FED HMIcontrol system based on the CoDeSys control software.
The documentation covers:
- FED-CEC control modules factory-loaded with CoDeSys run-time,
- FED local I/O subsystems
- CANopen distributed I/O interface.
This manual is not intended to be a reference for CoDeSys programming. If you need a CoDeSys
programming manual please refer to the appropriate documentation
FED-CEC Ethernet interface supports also basic TCP/IP Ethernet connectivity for FED and CANopen
master interface
The FED-CEC modules physical memory configuration is described in Table 1. The table refers to
CoDeSys firmware version V4.01K and above.
Note: the CoDeSys implementation on FED-CEC modules correspond to a single-task model with
no multithreading; the CoDeSys kernel has a system execution time fixed at operating system
level, to 10ms; this means that the fastest possible reaction on I/O image is limited to 10ms
CoDeSys is the complete development environment for the FED-CEC PLC modules. CoDeSys offers
the PLC programmer a simple approach to the powerful IEC languages.
The original documentation of CoDeSys will be installed when the software is installed. The available
documentation includes a clear and detailed presentation of the software and contains also a useful
“First Steps with CoDeSys” that should be your first guide in getting confidence with the system.
The main technical data of the FED-CEC control modules are shown in the table.
Local I/O
Figure 1
Local I/O
Remote I/O
Figure 2
Figure 3
Version
FED Designer 6.03 or higher
FED Firmware 5.12 or higher
CoDeSys 2.3.2 or higher
Table 3
All the FED units have only one slot available for the communication or control module and, if one
iPLC module is used, it is no longer possible to plug one additional communication module.
Note: The current implementation of CoDeSys on FED-CEC does not include drivers for Ethernet
distributed I/O.
Figure 4
Internal I/O modules are compatible with FED 500, FED 1000, FED 2000 and FED 5000 models.
Figure 5
Figure 7
Figure 8
When defining a new channel, the type and all the relevant parameters can be defined in the dialog
box shown in Figure 9.
Figure 9
Default parameters for both serial port connection and Ethernet connection are correct for operation
with FED.
When defining the driver for Ethernet connection, the “Address” parameter shown in Figure 10 must
contain the IP address assigned to the FED-CEC module.
Figure 10
Two options related to the Internal Controller are available for each FED port:
Application Mode ports should always be assigned to the Internal Controller in Application
Mode if it has to be used for normal operations such as application
downloading and debugging
Service Mode Service Mode is reserved for special Internal Controller maintenance and
should not be used
The Port is assigned to the Internal Controller in Application Mode when the corresponding row of the
System Menu displays the text “Application”. This message is reduced to “A” for displays with 20
characters per row.
When the PC/Printer port is not assigned to the Internal Controller, it reports the printer status as
usual.
When the PLC port is not assigned to Internal Controller and the Designer project does not use an
external controller, the System Menu contains the string “NOT IN USE” in the PLC row. In case an
external controller is used, the PLC row reports the communication error code as usual.
Note any modification to the port assignment done in System Menu becomes effective after you
exit the menu.
Communication with the Internal Controller is possible both when the panel is in Configuration Mode
and when it is in Operation Mode.
Standard FED programming cables can be used to connect the CoDeSys software FED. A gender
changer may be required to connect to the FED PLC port.
1.2.6.2.1 Limitations
There are some limitations in the configurations available for programming the Internal Controller.
This chapter provides an overview.
1. If FED contains a valid project that uses the PLC port to communicate with an external controller
and it is in Operation Mode, then communication with the Internal Controller is not allowed
through the PLC Port, because it is already assigned to the PLC communication.
3. If FED contains a valid project configured to use the UniNet network and the PC/Printer port is
assigned to network communication, the same FED port cannot be used to communicate with the
FED Internal Controller. A similar consideration applies in case the PLC port is used as network
port: communication with the PLC is not allowed through the same port.
4. If FED contains a valid project where the external controller is configured with a protocol that
requires a TCM module, then the Internal Controller may not work properly. Operations with
external controllers that require Ethernet interface via FED-CEC are instead always allowed.
The table below summarizes the most common cases in the connection with the Internal Controller.
FED Mode Communication Selection in Connect Internal Controller to
Ports System Menu
Configuration PC/Printer+PLC - PLC Port
PC/PLC - Programmable only in Operation Mode
Operation PC/Printer+PLC PLC: Application PLC Port
PC/Printer+PLC Printer: Application PC/Printer Port
PC/PLC Printer: Application PC/PLC Port
Table 4
Note If the Designer project is configured to use the Internal Controller and FED-CEC module is
not installed on the panel, the project will not run properly. Additionally, using a TCMxx
module with a project configured to use the Internal Controller may result in an unexpected
behavior.
Figure 12
Internal Controllers appear in the list of available data sources in the Source Selection dialog box.
See figure below.
Figure 13
Figure 14
A new version of the “.sym” file is created each time the project is built. Symbol files should be re-
imported in Designer Tag Editor to update the Designer’s tag list every time they are updated.
The CoDeSys symbol file can be imported in Designer selecting the “Import tags” command from the
“File” menu of the Tag Editor. The first step of the import process is shown in Figure 15; in the list of
the available controllers the CoDeSys is listed as “iPLC CoDeSys”.
Figure 16
Support for CoDeSys native tag format is provided selecting the “Native Driver Tags format” radio
button.
Any new set of tags imported in Tag Editor after the first one will be imported as a new Dictionary.
The new Dictionary should be properly linked to the Designer project when enabling the Tag Support
under “Project\Configure Tag Dictionaries…”.
Note: When the “Clean all” command is executed in the CoDeSys programming software, all the
absolute tag addresses are re-calculated by the CoDeSys compiler and the tag file needs to
be imported again in the Designer Tag Editor.
Figure 17
If the Internal Controller set-up is configured to use a combination of internal PLC and an external
controller, the “Network” tab allows the source selection of the variable to be added as shown in
Figure 18.
Figure 20
The “Enable Tag” checkbox allows browsing the Tag list created or imported in the Designer project.
See chapter “The Tag Editor” for detailed description of the Tag Editor tool.
Segment Type
0 %M Memory
1 %I Input
2 %Q Output
Table 5
If the option “Retain in own segment” is on, retain variables are in segment 3.
Global and POU (Program Organization Unit) local variables without direct address are in the
subsequent segments, starting with segment 4. If the option “Retain in own segment” is off, they start
at segment 3.
The reference to variables in the CoDeSys system consists of “POUref” (the segment), Offset and
size. Detailed description will be given in the following sections.
All variables used in a CoDeSys program must be declared in the “Declaration Editor”. The CoDeSys
“Declaration Editor” is shown in Figure 22.
The Declaration Editor is used to declare variables of POUs and global variables, for data type
declarations, and in the Watch and Receipt Manager
Figure 22
Figure 23
The different data types must be used depending on the PC Configuration built into the CoDeSys PLC
program; the mnemonics are compatible.
The content of retain variables is saved when the device is turned off and restored at the following
power-up.
Note FED firmware can allocate memory for retentive variables ONLY when the panel is in
Operation Mode.
There is a limit to the maximum number of retentive variables that can be defined. The current
implementation will support a maximum of up to 2048 bytes.
Retain settings are shown in the “Target Settings” dialog box as shown in Figure 26. They are fixed
and can not be changed by the user.
At programming time it will be responsibility of the programmer to ensure that the maximum amount of
available memory will not be exceeded. When compiling the project, the CoDeSys software will use
the specific Target Settings information to check if the total amount of retentive variables has been
exceeded.
As FED-CEC module has no on-board battery backup, removing the controller from the unit will result
in losing the information of the retentive memories.
The content of retentive memories will also be lost in the following cases:
- a new project file has been downloaded to FED
- a new firmware has been downloaded to FED
- the FEC-CEC module is moved from one FED panel to another
- a new PLC program is downloaded to the controller
Note: the Retentive Memory mechanism requires a specific sequence for its activation; after
CoDeSys project download or FED firmware update the power of the panel MUST be cycled
for TWO times to activate the mechanism.
Figure 26
Figure 27
The array must contain bytes elements declared in CoDeSys as unsigned short integer (USINT).
The absolute address into the controller memory segment of a variable declared in CoDeSys is only
visible in the symbol file created by the programming software at compile time.
The CoDeSys array structure ensures that all its elements have contiguous addresses; the first
element of the array can be used as offset reference for the RDA area.
Figure 28
If the “Keep RDA Contiguous” check box is enabled, Designer calculates the proper address of the
RDA segments, showing the absolute memory address into the PLC memory.
Considering the example of variable declaration shown in Figure 27, the Keyboard area is mapped as
shown in the Figure 29.
F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1
…. …..
1.3.5 Alarms
The Alarm area in the Internal Controller memory is organized as bytes. An array of bytes (USINT)
can be configured to handle Alarms.
Alarm bits are organized according to Figure 33.
This means that the individual bits in the Status word can be identified as follows:
RDA_S0 AT %MX8.0:BOOL;
RDA_S1 AT %MX8.1:BOOL;
RDA_S2 AT %MX8.2:BOOL;
RDA_S3 AT %MX8.3:BOOL;
RDA_S4 AT %MX8.4:BOOL;
RDA_S5 AT %MX8.5:BOOL;
RDA_S6 AT %MX8.6:BOOL;
RDA_S7 AT %MX8.7:BOOL;
RDA_S8 AT %MX8.8:BOOL;
RDA_S13 AT %MX8.13:BOOL;
RDA_S14 AT %MX8.14:BOOL;
RDA_S15 AT %MX8.15:BOOL;
(* MailBox mapping *)
MB_Status AT %MW21:WORD;
MB_CmdResp AT %MW22:WORD;
MB_Param00 AT %MW23:WORD;
MB_Param01 AT %MW24:WORD;
MB_Param02 AT %MW25:WORD;
MB_Param03 AT %MW26:WORD;
MB_Param04 AT %MW27:WORD;
MB_Param05 AT %MW28:WORD;
MB_Param06 AT %MW29:WORD;
MB_Param07 AT %MW30:WORD;
MB_Param08 AT %MW31:WORD;
MB_Param09 AT %MW32:WORD;
MB_Param10 AT %MW33:WORD;
MB_Param11 AT %MW34:WORD;
MB_Param12 AT %MW35:WORD;
MB_Param13 AT %MW36:WORD;
The main advantage of this approach would be the natural possibility to overlay the variables
definition and to give to each word, byte or bit the proper tag for a proper reference into the PLC
program and later into the Designer project.
This approach requires of course accepting that a fixed memory area in the controller memory is
allocated and reserved to FED RDA.
The Data Transfer process has different options based on the different Data Format of the data
involved in the copy process.
Source and target tag data format should be always compatible.
In case more than one variable needs to be copied using data transfer, the physical memory address
of all the elements must be contiguous. The easiest way to obtain this is in CoDeSys is configuring an
array.
Before starting a copy operation the Data Transfer module checks the byte order convention used by
the Source and the Target addresses. In FED the so-called Intel data format (little endian) is
considered not inverted; the Motorola format (big endian) is considered inverted.
When Source and Target are both inverted or not inverted the Data Transfer module does not apply
any transformation.
If Source and Target have different byte ordering, the Data Transfer module applies a byte swap
according to the rules explained in Figure 34.
Figure 34
1) The Designer project is configured to use an external controller along with the FED-CEC
application, the FED COMM LED blinks when an error occurs in the communication link with
Note FED will communicate with the CoDeSys Internal Controller even if the PLC application is not
running.
This chapter includes the basic explanation of the options available in the Festo Target Settings.
A complete explanation of all the options is available in the CoDeSys online help. The tools provided
by 3S to the OEMs allow a high level of customization of the Target Settings dialog depending on the
specific hardware requirements and capabilities. Most of the options described in the on line help are
not available in the Festo Target Support Package. This is not an error but the result of the OEM
decision to keep the interface as simple as possible leaving to the user the possibility to control only
some of the most important options.
Network functionality (Network Global Variables) is supported starting from FED-CEC firmware
version V4.01K. Visualization capabilities are at the moment not supported. The corresponding tab in
Target Setting does not contain any information.
1.4.3.1 EXOR_Ser_init
The function allows to initialize a built-in Uart and connect it to a physical channel.
Once a Uart is "used" and "connected" to a channel same Uart and same Channel cannot be used
within the program.
A call to EXOR_Ser_init with a "used" Uart or a "connected" channel will return a error.
parameters:
return value:
EXOR_Ser_init:SINT; (* 0 = port assigned and initialized, -1 = port not assigned because already
in use *)
1.4.3.2 EXOR_Ser_end
The function allows to make a Uart and connected channel free for other uses
parameters:
return value:
parameters:
return value:
1.4.3.4 EXOR_Ser_get
The function reads some received chars from internal buffer and copy to user buffer
ATTENTION: dimension of user buffer must be large enough to contain number of characters
specified in LEN parameter
parameters:
return value:
1.4.3.5 EXOR_Ser_put
The function writes some received chars from user buffer to TX buffer and start transmission if IDLE
ATTENTION: dimension of user buffer must be large enough to contain number of characters
specified in LEN parameter
parameters:
return value:
nchars := EXOR_ser_test(1);
IF nchars >= 20 THEN
rec_err := EXOR_ser_get(1, 20, ADR(rstr));
END_IF
The implementation of the ModBus Server only requires the call of this global instance of function
block EXOR_ModbusTcpSrv.
Now the server waits for ModBus clients requests. At most 4 client connections (and thus
ModBus functions) can be handled at the same time.
Always when this number is exceeded, the server terminates any client connection in order to get
able
to respond to the new request. There is no priority-controlled distinction of the clients.
The FB returns the following counters for statistic and diagnostic purposes
Example:
VAR
MODBUS_SRV:EXOR_ModbusTcpSrv;
BA:ARRAY [0..99] OF BYTE; (* BIT area *)
WA:ARRAY [0..199] OF WORD; (* WORD area *)
END_VAR
Event
EVENT_START,
EVENT_STOP,
EVENT_BEFORE_RESET,
EVENT_AFTER_RESET,
EVENT_AFTER_READING_INPUTS,
EVENT_BEFORE_WRITING_OUTPUTS,
EVENT_DEBUG_LOOP,
EVENT_BEFORE_DOWNLOAD
The Internal Controller CANopen master interface must be configured adding the I/O devices to the
CanOpenMaster Slot, which is automatically inserted in the PLC configuration upon selection of the
Festo target. Right-click over the CanOpenMaster board to append the elements as shown in Figure
39; available devices list depends on availability of devices eds files in the proper folder of the Target
settings.
Figure 40
However, a “Start All Nodes” telegram, NodeID=0 can be sent from the IEC.
This requires that at the start-up of the control application always sets the flag
bUseStartAllNodes of the master once, e.g. as follows (bInit defined by the application):
Warning: This flag must be set cyclically, since the individual nodes can non longer be started after a
failure.
A complete and detailed description on how the CAN controller should be configured and about the
configuration of CAN slave devices is included in the CoDeSys User Manual in chapter “6.5.7 –
Configuration of CAN Modules”.
CANopen implementation is described in 3S document “CANopen for 3S Runtime Systems
V2_3_5_0.pdf” available in the “Help” subfolder of the Target package installation path.
In addition the CFC Continuous Function Chart language has been included.
Please refer to the CoDeSys documentation for all the necessary information and details about
programming languages.
When opening a program from PLC, CoDeSys requires the specification of the target settings; they
should be as shown in Figure 41.
1.5 FED-UIM
FED-UIM is general purpose (multifunction) I/O board, compatible with FED 500, FED 1000, FED
2000 and FED 5000. FED-UIM should satisfy most of the typical process I/O signals. The main
feature of the FED-UIM is its configurability. Due to the high level of integration, FED-UIM offers a
“one-board solution” for most typical I/O configurations.
Figure 44:Digital input schematic diagram for E inputs: IN2, IN3, IN6, IN7, IN10, IN11, IN14, IN15,
IN16, IN17, IN18, IN19.
Description Specification
Input channels 20 digital optoisolated source active high (+24VDC) inputs.
All inputs are internally connected to 0Vdc of power supply.
Input voltage range 12-30Vdc (min 3mA); 35Vdc max for 500ms
Note: About the input filter delay, please note that the encoder, counter and frequency inputs are
digital ones with lower filter delay (the other characteristics are the same as described in the
above table). Each digital input can be used as a standard, encoder or counter/timer one.
Refer to the next table for the input filter delay specification.
Note: the time delay for the digital input filter refer to the complete input stage
Description Specification
Encoder channels 4 (Phase A, Phase B, Zero encoder and Machine zero index
pulse inputs per channel). All inputs are internally connected to
0Vdc of power supply.
A & B & Z & M channel inputs IN0 & IN1 & IN2 & IN3, IN4 & IN5 & IN6 & IN7,
IN8 & IN9 & IN10 & IN11, IN12 & IN13 & IN14 & IN15
Input frequency 1 MHz max
Count range 32 bit
Input frequency 1 MHz max
Table 8: Encoder channel specifications
Description Specification
Counter channels 4 (pulse and gate input per channel). All inputs are internally
connected to 0Vdc of power supply. The gate input enables the count
of input pulses; the count could be enabled only by SW (so the gate
input is available as a general digital input)
Pulse & gate input pairs IN0 & IN1, IN4 & IN5, IN8 & IN9, IN12 & IN13
Input frequency 1 MHz max
Pulse width 500 ns min
Count range 32 bit
Table 9: Counter inputs specifications
Description Specification
Frequency channels 4 (one input per channel). All inputs are internally connected to
0VDC of power supply.
Frequency inputs IN0, IN4, IN8, IN12
Input frequency 20KHz max, 1 Hz min
Pulse width 50 µs min
Accuracy 0.005%
Table 10: Frequency inputs specifications
Description Specification
Input channels 4 multifunction analog not isolated input channels. All analog
common inputs (COM) are internally connected to M pin of the
panel power supply connector.
Input or measurement type Voltage input
Current input
Temperature measurement (various types of thermocouples or
PT100 RTD) with incorporated external cold junction
compensation
A/D resolution 12 bits
Accuracy @ 25 °C 0.1%
Voltage input type Single-ended (up 8 inputs) or differential configuration (up 4
inputs)
Voltage input range Bipolar (± 100mV, ± 1V, ± 5V, ± 10V)
Unipolar (0 ÷ 100mV, 0 ÷ 1V, 0 ÷ 5V, 0 ÷ 10V)
Voltage input linearity error 0.1%
Voltage input accuracy Bipolar (±100mV) or unipolar (0÷100mV): 0.1% F.S.
Bipolar (±500mV) or unipolar (0÷500mV): 0.2% F.S.
Figure 48: Wiring example: two digital inputs (switches) and two digital outputs connection
Figure 49: Wiring example: logic connection of 4 encoder modules. The encoder modules must be
24V powered (connect 0V reference of the encoder to the 0V of the FED-UIM power supply).
Figure 50: Wiring example: counter inputs (pulse and gate) and/or frequency inputs (frequency) logic
connection. The external modules must be 24V powered (connect 0V reference of the external
module to the 0V of the FED-UIM power supply).
Figure 51: Wiring example: two single-ended voltage sources on the same channel (IN3+, IN3-,
COM), one differential voltage source (IN2+, IN2-), one current source (IN0+, IN0-).
Figure 52: Wiring example: 2-wire PT100 and a single-ended voltage source on the same channel
(IN3+, IN3-, COM), a 3-wire PT100 (IN2+, IN2-, COM), a shielded thermocouple (IN0+, IN0-), a 3-wire
PT100 (EXC, IN, COM dedicated inputs for cold
Figure 53
MEASURE TYPE
Parameter value Measure Mode Units
0 Voltage Differential mV
1 Voltage Single Ended mV
2 Current A
3 Resistance 2 wires m
4 Resistance 3 wires m
5 Voltage Thermocouple mV
Table 14
Different Full Scale can be selected for each Channel Couple as shown in Table 15.
FULL SCALE
Full Scale Full Scale for Voltage Full Scale for Current Full Scale for
parameter value Measurement Measurement Resistance
Measurement
0 / 100mV +/-2mA 0 - 80
1 / 500mV +/-10mA 0 - 400
2 / 1V +/-20mA 0 - 900
3 / 5V +/-20mA 0 - 8K
4 / 10V +/-20mA 0 - 1M
Table 15
Table 16 shows the different meaning assumed by the nine channels of the Analog Input board
depending on the measure mode selected in the configuration parameters.
All the configuration parameters of the FED-UIM Analog Input board can be easily changed run time
using the EXOR_IO_CTRL function with the following Function Codes:
All the configuration parameters of the FED-UIM Analog Output board can be easily changed run time
using the EXOR_IO_CTRL function with Function Codes listed in the next table:
Table 19
Other Function Codes are reserved for factory test procedures and they can not be used.
Each channel of Counter/Timer type consumes up to 4 digital inputs. In case all the 4 Counter/Timer
inputs are enabled, 4 digital inputs are still free for standard operation. Please refer to FED-UIM
hardware manual for additional specification and wiring diagrams.
For each counter/timer input you want to use, a “Counter/Timer” board has to be setup in the PLC
Configuration. Figure 57 shows an example of possible configuration with 2 channels enabled.
The parameter "ChannelNr" specifies the number of the associated counter/timer input; allowed
range is 1…4.
Note: Please note that Channel number must be assigned manually and must be different per each
Counter/timer board in the range 1…4.
Each Counter/timer board is inserted in the configuration using generic names where the channel
numbers are not specified; to complete the configuration the “x” must be replace with unique identifier
as shown for example in Figure 58.
Board parameters have different options and they can be selected at design time.
An explanation of the parameters follows in Table 20, Table 21, Table 22, Table 23 and Table 24.
1.5.14 Diagnostic
FED-UIM is able to report the following diagnostic information using the “FED-UIM - Diagnostic”
board.
The 2 outputs of this board are:
- Missing +24V Flag
- Output short circuit