COMP-261 Computer Organization and

Assembly Language

Course Overvie
Dr Hashim Al

Fall - 2021

Department of IT and Computer Scienc

Pak-Austria Fachhochschule: Institute of Applied Sciences and Technology

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Course Management [1/4]

• Instructor
• Dr Hashim Ali (hashim.ali@fecid.paf-iast.edu.pk

• Lab Engineer
• Engr. Shahbaz Khan (ra .ullah@paf-iast.edu.pk

• Course Material
• MS Teams (class join invitation has been sent.)

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Course Management [2/4]
• Text Book/s
• William Stallings, "Computer Organization and Architecture", 10th edition, Pearson,
2016, ISBN: 978-0134101613

• David A. Patterson, John L. Hennesy, "Computer Organization and Design: The

Hardware/Software Interface", 5th edition, Morgan Kaufmann, 2013, ISBN:
978-0124077263

• Kip Irvine, “Assembly Language for x86 Processors”, 7th edition, Pearson, 2014, ISBN:
978-013376940

• Laboratory Softwares
• Intel 8086/88 Emulator (For Assembly Language)
• Logisim (http://www.cburch.com/logisim/) (For Digital Circuit Simulation)
• Microsoft Of ce and Visio (For documentation)

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 Course Management [3/4]

• Prerequisites (Self-Requirement)
• EC-121 Digital Logic Desig

• Lectures
• Monday 10:00 — 11:3
• Tuesday 10:00 — 11:3

• Of ce Hours
• Friday 02:00 — 03:3

• Venue
• Lecture Hall: A1-30
• Laboratory: A1-301
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Course Management [4/4]

• Marks Distribution
• 80% Theory and 100% Lab attendance is recommended to appear in the nal examination

Theory (100%) Laboratory (100%)

Quizzes 8% Lab Reports 20%
Assignments 12% Lab Performance 40%
Project-I 10% Viva-Voce 10%
Mid-Semester Exam 20% Project-II 30%
Final Exam 50%

• Lab and Project groups must be of max 3 students

• Late Work
• Laboratory reports must be submitted at the end of each lab
• The penalty for any late work is 20% OFF for the rst date and an additional 30% OFF for the second day. No work will be accepted
thereafter.

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Course Goals
• Course Objective
• To introduce the internal working and organization of various building blocks of a digital computer as
well as simple assembly language programming techniques. Upon completion of this course, the
student will have basic understanding of computer system architecture including CPU design, memory
subsystem design and performance enhancement techniques

• Course Learning Outcomes (CLOs)

• CLO 1. Explain the structure and working principles associated in building of a digital computer and
Understand various parts of system memory hierarchies. [C2]
• CLO 2. Analyze mapping techniques for different cache memory systems. [C4
• CLO 3. Design basic and intermediate RISC processor including instruction sets, data paths,
microprogrammed control and ways of dealing with pipeline hazards. [C6
• CLO 4. Perform by writing well-modularized computer programs in Verilog, implementing various
parts of computer system. [P2
• CLO 5. Develop basic simulator and communicate ndings on processor design. [P3]

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Course Outline
• Difference between Architecture and Organizatio
• Introduction to superscalar processors (RISC, CISC
• Introduction to MIPS Assembl
• Design of various parts of computer system and component
• CPU Architecture (Instruction Set Architecture—ISA
• AND, OR, ADD, SUB, ANDi, ORi, ADDi, SUBi, SLT, BEQ, Jump etc
• Processor Design — Single Cycle, Multi-cycl
• Functional Blocks (PC, IR, CU, ALU, Memory etc.
• Instruction set design (Register-to-Register, Memory-reference, Control
• Addressin
• Control structures (BEQ, J
• Memory hierarchies and its managemen
• Design of Cache memory syste
• Interrupts and I/O Structure
• Pipelining — Issues, hurdles, exception handling, branch prediction etc
• Introduction to parallel processing

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COMP-261 Computer Organization and

Assembly Language

Lecture
Digital Logic Design — Revie
Dr Hashim Al

Fall - 2021

Department of IT and Computer Scienc

Pak-Austria Fachhochschule: Institute of Applied Sciences and Technology
Slides taken from “Computer Organization and Architecture” by William Stallings.

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 Lecture Outline
• Number System • Computer Arithmeti • Digital Logi
• The Decimal Syste • The Arithmetic and • Boolean Algebr
• Positional Number Logic Uni • Gate
Syste • Integer • Combinational
• The Binary Syste Representation (Sign- Circuit
• Conversion between magnitude, 2’s • Sequential Circuit
Binary and Decima Complement • Programmable Logic
• Hexadecimal • Integer Arithmetic Devices
Notation
Homework
CH-9,10,11 William Stallings

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Digital Systems
• The General-Purpose Digital Computer is the best-known example of a digital systems

• The major parts of a computer are a memory unit, a central processing unit, and input-output units.

Control Unit

Instruction

Program Program
Input Unit Memory Unit Output Unit
Data Result

Data

ALU Unit
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Typical System Architecture
• Most large digital systems consist of
• Datapat
• Arithmetic units (adders, multipliers
• Data-steering (multiplexers
• Memor
• Places to store data across clock cycle
• Memories, register les, etc
• Contro
• Interacting nite state machine
• Direct how the data moves through the datapath
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Typical System Architecture

• Primitive datapath plus controller

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Computer Arithmetic
Chapter — 10

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Arithmetic & Logic Unit
• Part of the computer that actually performs arithmetic and logical
operations on data

• All of the other elements of the computer system are there mainly to bring
data into the ALU for it to process and then to take the results back out

• Based on the use of simple digital logic devices that can store binary digits
and perform simple Boolean logic operations.

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 ALU Inputs and Outputs

Control
Signals Flags

ALU
Operand Result
Registers Registers

Figure 10.1 ALU Inputs and Outputs

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Integer Representation
• In the binary number system arbitrary numbers can be represented
with:
• The digits zero and on
• The minus sign (for negative numbers
• The period, or radix point (for numbers with a fractional
component

• For purposes of computer storage and processing we do not have the

bene t of special symbols for the minus sign and radix poin
• Only binary digits (0,1) may be used to represent numbers.

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Characteristics of 2’s Complement Representation

Range -2n-1 through 2n-1 - 1

Rpresentation of Zero One

Take the Boolean complement of each bit of the corresponding

Negation positive number, then add 1 to the resulting bit pattern viewed as
an unsigned integer.

Add additional bit positions to the left and ll in with the value of
Expansion of Bit Length
the original sign bit.
If two numbers with the same sign (both positive or both negative)
Over ow Rule are added, then over ow occurs if and only if the result has the
opposite sign.
To subtract B from A, take the twos complement of B and add it to
Subtraction Rule
A.

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Addition — with Over ow Discard carry
5+4=? (-7) + (-6) = ?
0101 = 5 1001 = -7
+ 0100 = 4 + 1010 = -6
1001 = Over ow 1 0011 = Over ow

Result has opposite sign

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Subtraction — with Over ow
7 - (-7) = ? -6-4=?
Minuend (M) = 7 = 0111 Minuend (M) = 1010 = -6
Subtrahend (S) = -7 = 1001 Subtrahend (S) = 0100 = 4
Negation (-S) = 0111 Negation (-S) = 1100
Discard carry

0111 = 7 1010 = -6
+ 0111 = 7 + 1100 = -4
1110 = Over ow 1 0110 = Over ow

Result has opposite sign

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fl
fl
Hardware for Addition and Subtraction
B Register A Register

Complementer

SW

OF Adder

OF = overflow bit
SW = Switch (select addition or subtraction)

Figure 10.6 Block Diagram of Hardware for Addition and Subtraction

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Digital Logic
Chapter — 11

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Boolean Algebra
• Mathematical discipline used to design and analyse the behaviour of the digital
circuitry in digital computers and other digital systems

• Boolean algebra could be used to solve problems in relay-switching circuit design

• Is a convenient tool
• Analysi
• It is an economical way of describing the function of digital circuitry
• Desig
• Given a desired function, Boolean algebra can be applied to develop a
simpli ed implementation of that function.

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Basic Logic Gates

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 An interconnected set of
gates whose output at any

Combinational Circuits time is a function only of the

input at that time

The appearance of the input

is followed almost
immediately by the
appearance of the output,
with only gate delays

Consists of n binary inputs

and m binary outputs

Can be defined in three

ways:
• Truth table
• For each of the 2 n possible
combinations of input signals,
the binary value of each of the
m output signals is listed
• Graphical symbols
• The interconnected layout of
gates is depicted
• Boolean equations
• Each output signal is
expressed as a Boolean
function of its input signals

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Boolean Function of Three Variables
A B C F
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 0
Table 11.3 A Boolean Function of Three Variables

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Product-of-Sums Implementation
A
B
C

A
B
C

A
B F
C

A
B
C

A
B
C

Figure 11.4 Sum-of-Products Implementation of Table 11.3

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Sum-of-Products Implementation

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Algebraic Simpli cation
• Involves the application of the identities to reduce the Boolean expression
to one with fewer elements.

A
C

F
B

Figure 11.6 Simplified Implementation of Table 11.3

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NAND and NOR Implementations

A
B

B
C

Figure 11.11 NAND Implementation of Table 11.3

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Multiplexers
• connect multiple inputs to a single output
D0

D1 4-to-1
multiplexer F
D2

D3

S2 S1

Table 11.7 4-to-1 Multiplexer Truth Table

Figure 11.12 4-to-1 Multiplexer Representation

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Decoders A

B
000
D0

001
D1

• combinational circuits with a number of C

010
output lines, only one of which is D2

asserted at any time

011
D3

100
D4

101
D5

110
D6

111
D7

Figure 11.15 Decoder with 3 Inputs and 23 = 8 Outputs

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Address Decoding
• Decoders nd many uses in digital computers
• One example is address decoding. Suppose we wish
to construct a 1K-byte memory using four 256 * 8-bit
RAM chips
• We want a single uni ed address space, which can be
broken down as follows
Addres Chi
0000-00F
0100-01F
0200-02F
0300-03F
• Each chip requires 8 address lines, and these are
supplied by the lower-order 8 bits of the address. The
higher-order 2 bits of the 10-bit address are used to
select one of the four RAM chips.

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F
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Read-Only Memory (ROM)

• Memory that is implemented with combinational circuit
• Combinational circuits are often referred to as “memoryless” circuits because
their output depends only on their current input and no history of prior inputs is
retaine

• Memory unit that performs only the read operatio

• Binary information stored in a ROM is permanent and is created during the
fabrication proces
• A given input to the ROM (address lines) always produces the same output (data
lines
• Because the outputs are a function only of the present inputs, ROM is a
combinational circuit

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Truth Table of ROM Binary Addition Truth Tables

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4-Bit Adder
A3 B3 A2 B2 A1 B1 A0 B0

Overflow
signal C3 Cin C2 Cin C1 Cin C0 Cin 0

S3 S2 S1 S0

Figure 11.19 4-Bit Adder

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Construction of a 32-Bit Adder Using 8-Bit Adders

A31 B31 A31 B31 A23 B23 A16 B16 A15 B15 A8 B8 A7 B7 A0 B0

C23 C15 C7
Cout 8-bit 8-bit 8-bit 8-bit Cin
adder adder adder adder

S31 S24 S23 S16 S15 S8 S7 S0

Figure 11.21 Construction of a 32-Bit Adder Using 8-Bit Adders

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Sequential Circuit
Current output
depends not only
on the current
input, but also on
the past history
of inputs

Sequential

Circuit

Makes use of
combinational
circuits

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Flip-Flops
• Simplest form of sequential circui
• There are a variety of ip- ops, all
of which share two properties
• The ip- op is a bistable device.
It exists in one of two states and,
in the absence of input, remains
in that state. Thus, the ip- op
can function as a 1-bit memory
• The ip- op has two outputs,
which are always the
complements of each other.

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fl
fl
fl
fl
fl
fl
fl
fl
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Basic Flip-Flops Name Graphical Symbol

S Q S
Truth Table

R Qn+1
0 0 Qn
S-R Ck 0 1 0
1 0 1
R Q 1 1 –

J Q J K Qn+1
0 0 Qn
J-K Ck 0 1 0
1 0 1
K Q 1 1 Qn

D Q D Qn+1
0 0
D Ck 1 1

Figure 11.27 Basic Flip-Flops

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Parallel Register
Data lines

D18 D17 D16 D15 D14 D13 D12 D11

D Q D Q D Q D Q D Q D Q D Q D Q

Clk Clk Clk Clk Clk Clk Clk Clk

Clock
Load

D08 D07 D06 D05 D04 D03 D02 D01

Output lines

Figure 11.28 8-Bit Parallel Register

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5-Bit Shift Register

Serial In D Q D Q D Q D Q D Q Serial Out

Clk Clk Clk Clk Clk

Clock

Figure 11.29 5-Bit Shift Register

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Counter
• A register whose value is easily incremented by 1 modulo the capacity of the
registe
• After the maximum value is achieved the next increment sets the counter value to
• An example of a counter in the CPU is the program counte
• Can be designated as:
• Asynchronou
• Relatively slow because the output of one ip- op triggers a change in the status
of the next ip- o
• Synchronou
• All of the ip- ops change state at the same tim
• Because it is faster it is the kind used in CPUs

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r

fl
fl
s

fl
fl
p

fl
 C B A Jc Kc Jb Kb Ja Ka
0 0 0 0 d 0 d 1 d
0 0 1 0 d 1 d d 1
0 1 0 0 d d 0 1 d
(a) Truth table 0 1 1 1 d d 1 d 1
1 0 0 d 0 0 d 1 d
1 0 1 d 0 1 d d 1
1 1 0 d 0 d 0 1 d
1 1 1 d 1 d 1 d 1

BA BA
(b) Karnaugh maps 00 01 11 10 00 01 11 10

0 1 0 d d d d
Jc = BA C Kc = BA C
1 d d d d 1 1

Design of a 0
00 01

1
BA
11

d
10

d 0
00

d
01

d
BA
11

1
10

Synchronous
Jb = A C Kb = A C
1 1 d d 1 d d 1

BA BA
00 01 11 10 00 01 11 10

Counter Ja = 1 C
0

1
1

1
d

d
d

d
1

1
Ka = 1 C
0

1
d

d
1

1
1

1
d

(c) Logic diagram

High Ja A Jb B Jc C C B A
binary
output
Ck Ck Ck

Ka A Kb B Kc C

Clock

Figure 11.31 Design of a Synchronous Counter

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Adder/Subtractor Design

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Adder Circuit
• Perform bit by bit addition —
similar to the “paper and
pencil” way

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Subtraction Circuit
• Use the formula
• X - Y = X + Y’ + 1

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Combining Addition and

Subtraction
• Use a multiplexer circuit

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Logical Operations

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 Logical Operations: AND, OR
• MIPS logical instructions require bit by bit operation on 32 bit string

• AN
0010 1011 1100 0110 1111 0000 0101 100
0000 1111 0000 1111 0000 1111 0000 111
———————————————————
0000 1011 0000 0110 0000 0000 0000 100

•O
0010 1011 1100 0110 1111 0000 0101 100
0000 1111 0000 1111 0000 1111 0000 111
———————————————————
0010 1111 1100 1111 1111 1111 0101 1111

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Circuit for ‘AND’, ‘OR’ Instructions

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Combining AND, OR,
ADD, SUB — ALU

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Over o
Comparing Two Integers

• Better approach • A simple approach:

• Subtract and check the result • Compare directly

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Assignment —
Deadline 4th October, 2021

• Start learning Logisim Software

• Design 1-bit Adder/Subtractor digital circuit

• Design 1-bit ALU digital circuit having the following operations:
• AND, OR, ADD, SU
• Integrate bit comparison logic to 1-bit ALU

• Submission
• Hard copy containing all necessary work to do the assignment
• Prove accurate working off the design by using some random inputs.
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Subtract and Check the Result

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Extending ALUi for Comparison (slt)

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 ALU for AND, OR,
ADD, SUB, BEQ, SLT

SLT = Set Less The

BEQ = Branch if Equal (or to
check equality of two numbers)

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Assignment —
Deadline 11th October, 2021

• Simulation of 1-bit ALU of Assignment-1 using Logisim

• Design of 4-bit Adder/Subtractor digital circuit using Logisim.

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Multiplier Design

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Multiplication — ‘Paper Pencil’ Method
M 0 1 Multiplication of Unsigned
Binary Numbers [3 and 5]
Q 1 0 Multiplier Logic
Initialisation
———
A+M 0 0 0 0 0
0 1
Shift by 1 0 0 0 1 1
0 0 0
Shift by 2 0 0 0 1 1
0 1 1 x
—————
0 1 1 1 1 Partial
MxQ 0 1 1 1 1
Product

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Hardware Implementation of Unsigned Binary

Multiplication

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Flowchart for Unsigned
Binary Multiplication

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Booth’s Algorith
Signed Binary Multiplication

A Q Q-1 M
0000 0011 0 0111 Initial Values

1001 0011 0 0111 A A - M First

1100 1001 1 0111 Shift Cycle
Second
1110 0100 1 0111 Shift Cycle

0101 0100 1 0111 A ! A + M Third

0010 1010 0 0111 Shift Cycle

Fourth
0001 0101 0 0111 Shift
Cycle

Figure 10.13 Example of Booth's Algorithm (7 ! 3)

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Divider Design

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 Division: Example
0011 Q - Quotient
0100 00001101 A - Dividend
0000 0 x M x 23 Apply subtraction
0001101
M - Divisor 0000 0 x M x 22
001101
0100 1 x M x 21
00101
Partial
0101 1 x M x 20
Reminders
0001 R

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Divider Design

+/

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Flowchart for
Unsigned
Binary
Division

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 Restoring Division — Example (12/3)
M=0011, M’+1=1101
Comment A Q Comment A Q
Initial 0000 110
1- Shift Left 0001 100 3- Shift Left 0000 001x

A←A-M 110 A←A-M 1101

111 1101

If AMSb=1, Q0=0 1110 100 If AMSb=1, Q0=0 1101 0010

Restore(A←A+M) 0000 0010
Restore(A←A+M) 0001 100

4- Shift Left 0000 010x

2- Shift Left 0011 000

A←A-M 1101

A←A-M 110 1101

000 If AMSb=1, Q0=0 1101 0100

If AMSb=0, Q0=1 0000 000 Restore(A←A+M) 0000 0100
No Restore
Reminder Quotient
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 Non-Restoring Division — Example (12/3)

M=0011, M’+1=1101
Comment A Q Comment A Q
Initial 0000 110
1- Shift Left 0001 100 3- Shift Left 0000 001x

If AMSb=0, Sub M 110 If AMSb=0, Sub M 1101

111 1101

If AMSb=1, Q0=0 1110 100 If AMSb=1, Q0=0 1101 0010

2- Shift Left 1101 000 4- Shift Left 1010 010x

If AMSb=1, Add M 001 If AMSb=1, Add M 0011

000 1101

If AMSb=0, Q0=1 0000 000 If AMSb=1, Q0=0 1101 0100

110
To nd Reminder
001
Restore A←A+M
0000 Quotient
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Decisions Involving Negatives

• Simplest solution—convert to positive and adjust sign later

• Note that multiple solutions exist for the equation:

Dividend = Quotient x Divisor + Re min der
• +7 div +2 Quo = +3 Rem = +
• -7 div +2 Quo = -3 Rem = -
• +7 div -2 Quo = -3 Rem = +
• -7 div -2 Quo = +3 Rem = -

• Convention
• Dividend and reminder have the same sig
• Quotient is negative if signs disagre
• These rules ful l the equation above

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Signs in Signed Division

Dividend Divisor Quotient Reminder
+ + + +
+ - - +
- + - -
- - + -

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Shift Operations

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Shift Operations — Logical
Shift left logical 3 bits Shift right logical 3 bits

a31 a30 …… a1 a0 a31 a30 …… a1 a0

a28 a27 …… a1 a0 0 0 0 0 0 0 a31 a30 …… a4 a3

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Circuit for Shifting by 2 bits

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Circuit for Shifting by 0 to 31 bits

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Shift Operations — Arithmetic

Shift right arithmetic 2 bits

a31 a30 …… a1 a0

a31 a31 a31 a30 …… a3 a2

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