Sinais comuns numa Placa Mãe

CLK_CPU_BCLK [1:0] I Bus clock

H_PWRGOOD I Power OK signal
H_CPURESET # I Reset signal
H_VID [6:0] O Voltage identification signal
H_GTLREF I GTL reference voltage

A.
CPU_BSEL [2:0] I/O Bus select signal

IC
H_TEST [1:2] I CPU detection signal

N
H_PROCHOT # I/O CPU overtemperature indication

Ô
H_THRM # I Thermal alarm signal

R
PM_THRMTRIP O Thermal alarm signal

ET
H_IGNNE # I To ignore numerical error signal

EL
H_INIT # I Initialization
H_INTR I EMaskable interrupt
D
H_20M # I Address bit 20 mask signal
S

H_FERR # O Floating-point error signal

SO

H_SMI # I A system management interrupt signal

H_STPCLK # I Stop the clock signal
R

DPRSLPVR I Deep sleep - the regulator signal

U
C

DPRSTP # I Depth stop signal

ET

H_CPUSLP # I CPU sleep signal

H_A [31:3] # I/O Address bus signals
LN

H_D [63:0] # I/O Data bus

BE

H_REQ [4:0] # I/O Command request

H_TRDY # I/O Target ready
LA

H_ADS # I/O Address Strobe

H_ADSTB [1:0] # I/O Address Strobe
H_AP [1:0] # I/O Address parity
H_DBSY # I/O Data bus is busy
H_DP [3:0] # I/O Data parity
MA_A [13:0] O Memory address

1
M_DQ [63:0] I/O Data lines
M_DM [7:0] O Data Masking
M_DQS [7:0] I/O Data strobe
M_CKE [3:0] O Clock allows
M_CK [4:0] / MA_CK # [4:0] O Clock output
M_CS [3:0] # O Chip select

A.
M_BA [1:0] O Bank Select

IC
M_RAS # O Row address

N
M_CAS # O Column address

Ô
M_WE # O Write enable

R
ET
NB_CRT_HSYNC O Horizontal synchronizing signal
NB_CRT_VSYNC O Vertical synchronizing signal

EL
NB_CRT_RED O The red analog signals output
NB_CRT_GREEN O
E
The Green analog signal output
D
NB_CRT_BLUE O The Blue analog signal output
S

NB_CRT_REFSET I Resistance setting

SO

TV_DACB / DACC O TV signal transmission

R

DMA Direct access to memory

U

PCI_AD [31:0] I/O Address data bus

C

PCI_PAR I/O Parity signals

ET

PCI_C / BE [3:0] # I/O Instruction or byte Enable

Bus - Peripheral Component
LN

PCI
Interconnect bus
BE

PCI_REQ # I Request
PCI_GNT # O Guarantee
LA

PCI_RST # O Reset signal

PCI_FRAME # I/O Cycle framework
PCI_IRDY # I/O Master device ready signal
PCI_TRDY # I/O Signal from the device is ready
PCI_STOP # I/O Stop
PCI_DEVSEL # I/O Device select signal

2
PCI_IDSEL I Initialize the device selection
PCI_LOCK # I/O Locking
PCI_CLK_LAN I Network clock
TP_RX [2:0] I Accept data
TP_TX [2:0] I Transfer data
LAN_RSTSYNC O Lan Chip reset signal

A.
EE_SHCLK O EEPROM clock

IC
EE_DIN I EEPROM data input

N
EE_DOUT O EEPROM data output

Ô
EE_CS O Chip select signal

R
ET
OC # I Overcurrent protection
USBP + (-) I/O USB signal

EL
IDE_PDCS1 # O Device chip select
IDE_PDA [2:0] O
E
Device address
D
IDE_PDD [15:0] I/O Device data
S

IDE_PDDREQ I Device requests

SO

IDE_PDDACK # O Device DMA confirmation

R

IDE_PDIOR # O Disk I / O read

U

IDE_PDIOW # O Disk I / O write

C

IDE_PDIORDY I I / O channel ready

ET

SATA0TXP (N) O Transmission of serial ATA0

SATA0RXP (N) I Serial ATA0 accept
LN

SATARBIAS (#) I The Serial ATA resistance bias

BE

SATALED # OD SATA to read and write instructions

LA

SMB Full System Management Bus

SMBDATA I/O Data lines
SMBCLK I/O Clock line
LAD [3:0] I/O Composite line of the address data
LFRAME # I/O LPC framework
LDRQ # I DMA request
ACZ_RST # O Reset signal
3
ACZ_SYNC O Sync signal
ACZ_SDATAOUT O Serial data output
ACZ_SDATAIN [1:0] I Serial data input
HP_JD_SENSE # I Within the external speaker switch
MIC_JD_SENSE # I Within external micphon switching
PWRBTN # O Power button signal

A.
RSMRST # O Restore the normal reset signal

IC
PWROK I Power good signal

N
PLTRST # O Total reset signal

Ô
SLP_S3 ( S4 , S5 ) # I Sleep control signal

R
ET
LRST1 # I LPC reset signal
ROMRD # O The data has been ready.

EL
ROMCS # O Chip select signal
EC_POWER_ON I
E
Power on signal
D
BATT_TEMP Battery Identification
S

ADAPTOR_I Adapter current setting

SO

BAT_V Battery voltage identification

R

BAT_I Charge / still charge

U

EC_BRGHT Light and dark adjustment

C

CHG_I Charging current setting

ET

FAN_CTRL0 Fan Control

CHG_REF Charging reference voltage
LN

SB_RTCRST RTC reset

BE

PM_THROTTING # Over-temperature alarm

LA

CHG_G_LED Charging instructions (Green)

PWR_LED Power Indicator
RF_LED Wireless LAN indicator
BTL_BEEP Alarm tone control
BATOFF_I Battery Close
LCD_SW [2:0] LCD switch
ADAP_IN Adapter access
4
CHG_ON Charging open
LCDSW LCD backlight switch
LID # Sleep-pin switch
AUX_PWRGD AUX voltage is normal
V_RPWRGD CPU voltage is normal
AUX_OFF AUX voltage shutdown signal

A.
AUX_PWR_ON AUX voltage is turned

IC
N
Ô
R
ET
EL
E
D
S
SO
R
U
C
ET
LN
BE
LA