Synthesis of high-speed finite state machines in FPGAs by state

splitting
Valery Salauyou

Bialystok University of Technology (Bialystok, Poland), valsol@mail.ru

Key words — synthesis, finite state machine, high-speed, high performance, state splitting, field programmable gate array, FPGA,
SoC, look up table, LUT.

Abstract. A synthesis method of high-speed finite state machines (FSMs) on LUT-based field programmable gate array
(FPGA) by internal state splitting is offered. The method does not change an FSM type (Mealy or Moore), the method does
not demand introduction of additional blocks or clock signals, and one can be easily included in a designing flow of digital
systems in FPGA. Estimations of a number of LUT levels are presented with an implementation of FSM transition
functions in case of a sequential and parallel decomposition. Algorithms splitting of FSM internal states for synthesis high-
speed FSMs are described. Experimental results showed a high efficiency of the offered method, an FSM performance
increases by 1.52 times on occasion. In conclusions, the experimental results are considered, a possibility of the using
method for creation high-speed FSMs on ASIC is marked, and perspective directions designing of high-speed FSMs are
specified.

1. Introduction
Large-size functional blocks and nodes of a digital system and also itself the digital system, as a rule, include a
control device or a controller. A speed of the digital system and functional blocks making it directly depends on a speed of
their control devices. A mathematical model of the majority of control devices and controllers is a finite state machine
(FSM). Because of this, the synthesis methods of high-speed FSMs are necessary for designing of high-performance digital
systems. During synthesis of high-speed FSMs it is possible ignored a implementation cost as an area on a chip of control
devices makes a small part in comparison with other system components (for example, memory or transceivers).
In modern times, programmable logic devices (PLDs) are widely used for designing of digital systems. Now, two
types of PLD architectures are widely used: on the basis of two programmed matrixes (AND and OR), and on the basis of
functional generators an LUT (Look Up Table). The first type PLDs will be called Complex Programmable Logic Devices
(CPLDs), and the second will be called Field Programmable Gate Arrays (FPGAs). It is possible to represent a structure
FPGA as a great quantity of LUTs united by interconnections. Every LUT allows to realize any Boolean function from a
small number of arguments (as a rule, from 4 to 6). The methods of FSM synthesis in CPLD have been considered in [1]. In
given paper, a synthesis method of high-speed FSMs in FPGA is considered.
Many articles are devoted a problem of high-speed FSM designing in PLD, which are characterized by the big
variety of approaches for the decision of the given task. In [2], the technique for improving the performance of a
synchronous circuit configured as a look-up table based FPGA without changing the initial circuit configuration is
presented. Only the register location is altered. It improves clock speed and data throughput at the expense of latency. In
[3], the methods and tools for state encoding and combinational synthesis of sequential circuits based on new criteria of
information flow optimization are considered. In [4], the timing optimization technique for a complex FSM that consists of
not only random logic but also data operators is proposed. The technique, based on the concept of catalyst , adds a
functionally redundant block (which includes a piece of combinational logic and several other registers) to the circuits
under consideration so that the timing critical paths are divided into stages. In [5,6], styles of the description of FSMs in
language VHDL, and also known methods of a state assignment for implementation of FSMs are researched. In [7],
evolutionary methods are applied to synthesis of FSMs. At the first stage, the task of state assignment by means of genetic
algorithms is resolved. Then evolutionary algorithms are applied to minimization of a chip area and a time delay of FSM
output signals. In [8], a task of a state assignment and an optimization of the combinational circuit at implementation of
high-speed FSMs in CPLD is considered. In [9], a novel architecture that is specifically optimized for implementing
reconfigurable FSMs Transition-based Reconfigurable FSM (TR-FSM) is presented. The architecture shows a considerable
reduction in area, delay and power consumption compared to FPGA architectures. In [10], the new model of the automatic
machine named the virtual finite state machine (Finite Virtual State Machine - FVSM) is offered. For implementation of
the FVSM the architecture based on storage, and a technique of generation of the FVSM from traditional FSMs is offered.
The FVSM implemented on new architecture, have advantage on high-speed performance, in comparison with traditional
implementation of FSMs on storage RAM. In [11], an implementation of FSMs in FPGA with usage of integral units of
storage ROM is considered. Two architecture of FSMs with multiplexers on inputs of blocks ROM which allow to reduce
the area and to increase high-speed performance of the FSM are offered. In [12], the reduction task of arguments of
transition functions by state splitting is considered, it allows to reduce a chip area and a time delay with implementation of
FSMs in FPGA.
 This paper also uses splitting of FSM states, but the purpose of splitting is increase of a performance of FSMs in
LUT-based FPGA. Splitting of FSM states is assigned to operations of the equivalent conversions of an FSM and does not
change an algorithm of its functioning. During splitting of FSM states the machine type (Mealy or Moore) is saved, the
general structure of the FSM does not change, and embedded memory blocks of FPGAs are not used. In the course of state
splitting the hierarchy of the state names of also is saved that simplifies an analysis and debugging of system project.
Because of this the offered synthesis method of high-speed FSMs in FPGA is aimed at practical usage and can be easily
included in a general flow of digital systems designing.
This paper is organized as follows. Section 2 describes estimations of a number of LUT levels with an
implementation of FSM transition functions in case of a sequential and parallel decomposition. Section 3 considers the
synthesis method of high-speed FSMs, which includes two algorithms: the general algorithm and the algorithm for
decomposition of the individual state. The detailed example shows the method. Experimental results are reported in Section
4. Section 5 concludes.

2. Estimations for a number of LUT levels for transition functions

Let A = {a1, …, aM} be the set of internal states, X = {x1, …, xL} be the set of input variables, Y = {y1, …, yN} be the
set of output variables, and D = {d1, …, dR} be the set of transition functions of an FSM.
A one-hot state assignment is traditionally used for synthesis of high-speed FSMs in FPGAs. Thus to each internal
state corresponds the separate flip-flop of FSM’s memory, which setting in 1 means that the FSM is in the given state. The
input of each flip-flop is controlled by transition function di, di  D, i.e. to each internal state of the FSM corresponds own
transition function di, i= 1, M .
Let X(am,ai) be the set of the FSM input variables which values initiate the transition from the state am to the state
ai (am, ai  A). To implement some transition from the state am to the state ai it is necessary to check the value of the flip-
flop output for the active state am (one bit) and the input variable values of the set X(am,ai), which initiate the given
transition. To implement the transition function di it is necessary to check the values of flip-flop outputs for all states from
which transitions lead to the state ai, i.e. |B(ai)| values, where B(ai) is the set of states from which transitions terminate in
the state ai, where |A| is the capacity of the set A. Besides, it is necessary to check the values of all input variables which
initiate transitions to the state ai, i.e. |X(ai)| values, where X(ai) is the set of the input variables which values initiate
transitions to the state a , X ( ai )  X ( a m , ai ) .
i
amB ( ai )

Let ri be a rank of the transition function di, where

ri  B ( ai )  X ( ai )  
Let n be a number of inputs of LUTs. If the rank ri for the some transition function di (i = 1, M ) exceeds n, there
is a necessity in a decomposition of the transition function di and its implementation on the several LUTs.
Note that by splitting of internal states it is impossible to lower the rank of the transition functions below the value
r*  max(| X ( a m , a s ) |)  1, m, s  1, M 
In this method the value r* is used as an upper bound of the ranks of the transition functions at splitting of the
FSM states.
It well-known two basic approaches to the decomposition of Boolean functions: sequential and parallel [1]. In case
the sequential
1 decomposition all the LUTs sequentially are connected in a chain (fig. 1).
n
LUT 2
s

n-1 LUT li

n-1 LUT di

Figure 1. The sequential decomposition of Boolean function

The n arguments of the function di arrive on inputs of the first LUT, and the (n-1) arguments arrive on inputs of all
s
remaining LUTs. Because the number li of the LUT’s levels in case the sequential decomposition of the transition
function di having the rank ri is defined from expression:

r n
lis  int i  1
 n 1   

where int(A) is the least integer more or equal A.

In case of the parallel decomposition the LUTs incorporate in the form of the hierarchical tree structure (fig. 2).
 1
n
LUT
2
1
LUT
n
n
LUT li
p

1
LUT di

n n
LUT
1
LUT
n
n
LUT
Figure 2. The parallel decomposition of Boolean function
The values of the function arguments arrive on inputs of the first level LUTs, and the values of the intermediate
functions arrive on inputs of all next levels of the LUTs. Because the number of the LUT’s levels in case the parallel
decomposition the transition function di having the rank ri is defined by following expression:

lip  int  log n ri   

It is difficult to predict what decomposition (sequential or parallel) used by the specific synthesizer. The
preliminary researches showed that, for example, the design tool Quartus II from Altera simultaneously uses both
sequential, and parallel decomposition. The number li levels of LUTs at implementation in FPGA transition function di with
s p
the rank ri can be between values li and li , i= 1, M .

Let us enter integer coefficient k, k  [0,10], which allows to adapt the offered algorithm with determination of the
number of the LUT’s levels for the specific synthesizer. In this case the number li of the LUT’s levels for implementation
of the transition function di having the rank ri will be defined by following expression:

 10  k p k s 
li  int  li  li 
 10 10   

The specific value of the coefficient k depends on the architecture of an FPGA and the used synthesizer.
The following problem is the answer to a question: when it is necessary to stop splitting of the FSM states? The
matter is that with splitting of the some state ai (i= 1, M ), except the increase of the number M of the FSM states, the
number of the transitions in the states of a set A(ai) also is increased, where A(ai) is the set of the states in which the
transitions from the state ai terminate. With splitting of the state ai the capacities of the sets B(am), am  A(ai), increase for
the states of set A(ai). Therefore according to (1) for states of the set A(ai) the ranks of the transition functions grow that can
s p
lead to increase of the values and li , li , and li.
In the this algorithm the process of state splitting stops, when the following condition is performance:

lmax  int  lmid   

where lmax is the number of the LUT levels which necessary for implementation of the most "bad" function having the
maximum rank; lmid is the arithmetic mean value of the number of LUT levels for all transition functions. Note that in the
process splitting of internal states the value lmid will increase, and the value lmax will decrease, therefore the algorithm
execution always comes to an end.

3. Method for high-speed FSM synthesis

According to the above discussion the algorithm of state splitting for high-speed FSM synthesis is described as
follows.
Algorithm 1.
1. The coefficient k (k  [0,10]) is determined, which reflects the method used by synthesis tool for the decomposition of
Boolean functions.
2. According to (1) ranks ri for all FSM transition functions are defined, i= 1, M .
3. On the basis (3), (4), and (5), for each transition function di the number li of LUT levels is defined.
4. The values lmax and lmid are determined. If conditions (6) are satisfied, then go to step 7, else go to step 5.
5. The state ai, for which ri = max, is selected. If it is several such states, among them the state for which |A(ai)| = min is
selected (i.e. an increase of the ranks for other states is minimized in a result splitting of the state ai).
6. The state ai, which was selected in step 5, splitting by means of the algorithm 2 on the minimum number H of states ai_1,
…,ai_H so that for each state ai_h, h= 1, H , was fulfilled ri_h ≤ r*, where r* is defined according to (2); go to step 2.
7. End.
The further synthesis of the FSM is performed by traditional techniques, for example, automatically by means of a
synthesizer of a design tool. For this purpose, it is enough to describe the FSM received after splitting of internal states in
one of design languages (Verilog or VHDL). The value of the coefficient k (step 1 of algorithm 1) is defined empirically
with synthesis of test examples by used design tool.
For splitting of some state ai, i= 1, M , which is executed in step 6 of algorithm 1, a Boolean matrix W is
constructed as follows. Let C(ai) be the set of transitions to the state ai. Rows of the matrix W correspond to the elements of
the set C(ai). Columns of the matrix W are divided on two parts according to types of arguments of the transition function di.
The first part of the columns of the matrix W corresponds to set of the states B(ai), the transitions from which terminate in a
state ai, and the second part of the columns of the matrix W corresponds to set of the input variables X(ai), which values
initiate transitions in the state ai. An one is put at the intersection of the row t, t= 1, T , T = |C(ai)|, and the column j of the
first part of the matrix W if the transition ct, ct  C(ai), is executed from the state aj, aj  B(ai). An one is put at the
intersection of the row t and the column j of the second part of the matrix W if the input variable xj, xj  X(ai), accepts
significant value (0 or 1) on transition ct, ct  C(ai). Now the task is reduced to a partition of the matrix W on the minimum
number H of row minors W1,…,WH so that the number of the columns, which contain ones in each minor Wh, h= 1, H , did
not exceed the value r * that defined according to (2). The rows of each minor Wh will define transitions in the state ai_h, h=
1, H .
Let wt be some row of the matrix W. For finding of a row partition of the matrix W on the minimum number H of
row minors W1,…,WH the following algorithm can be used.
Algorithm 2.
1. Putting h := 0.
2. Putting h := h + 1. A formation of minor Wh begins. The row wt, which has the maximum number of ones, is selected in
minor Wh as a reference row. The row wt is included in the minor WH and is eliminated from the further reviewing, putting
Wh := {wt}, W := W\{wt}.
3. In the minor Wh rows are added. For this purpose among rows of the matrix W the line wt is selected, for which the next
inequality is satisfied
| Wh  {wt } | r * ,
where | Wh  {wt } | is the total number of ones in columns of the minor Wh and the row wt after their join on OR.
If such rows can be selected several, among them the row wt is selected, which has the maximum number of common ones
with the minor Wh, i.e.
| Wh  {wt } | max ,
The row wt is included in minor Wh and it is eliminated from the further reviewing, putting Wh := Wh  {wt}, W := W\{wt}.
Step 3 repeats until at least the single row can be included in the minor Wh.
4. If in the matrix W all the rows distributed between minors, then go to step 5, else go to step 2.
5. End.
An operation of the offered synthesis method we show on an example. Let it is necessary to synthesize the high-
speed FSM, which graph is shown on fig. 3.
 y=0 y=1 y=0
!(!x1x2!x3x4!x5) 1
a1 a3 a4
!x
1 x2 !
x3 x
4 !x
5
x1
y=1

a2 1
!x1

!x 10
7!
x 8x 9
x
!(!x6x7!x8x9!x10) !x 6

1 a5
a6
y=0 y=1

Fugure. 3. The graph of the initial FSM

The given FSM represents a machine Moore, has 6 states a1,…,a6, 10 input variables x1,…,x10 and one output
variable y, which value on fig. 3 is shown near each state. The transitions from states a3, a4, and a5 are unconditional,
therefore on these transitions the logical value 1 is written as a transition condition. The values of the sets B(ai) and X(ai), and
also the ranks ri of transition functions for the given FSM are presented in Table 1. As for the given example we have max(|
X(am,as)|)=5, then according to (2) the value r* = 6. Let it is necessary to construct the FSM in FPGA for which the
maximum number of inputs of LUTs equally 6, i.e. we have n = 6.
s p
Table 1. Values of B(ai), X(ai), ri, li , and li for initial FSM
State B(ai) X(ai) ri lis lip
a1 {a6} {x6,x7,x8,x9,x10} 6 1 1
a2 {a1,a6} {x1,x2,x3,x4,x5,x6,x7,x8,x9,x10} 12 3 2
a3 {a1} {x1,x2,x3,x4,x5} 6 1 1
a4 {a2,a3} {x1} 3 1 1
a5 {a2,a4} {x1} 3 1 1
a6 {a5} Ø1 1 1 1
Note 1. Ø is an empty set.
s p
According to (3) and (4) the values li and li are defined for each state (they are presented in the appropriate
columns of Table 1). Suppose that we do not know as the compiler performs a decomposition of Boolean functions, therefore
we assume the sequential decomposition (the worst variant). Hence the value of coefficient k in expression (5) putting equal
10, i.e. we have k = 10. As a result the number of LUT levels (which are necessary for implementation of each transition
s
function) is defined by value li = li . Thus, for our example we have int(lmid) = int(8/6) = 2. In other words, splitting of FSM
internal states stops as soon as each transition function can be implemented in two levels of LUTs.
s s
For a considered example we have lmax = l2 = 3, i.e. the condition (9) is broken for a state a2, as lmax = l2 = 3 >
int(lmid) = 2. For this reason the state a2 splitting by means of algorithm 2. The matrix W is constructed for splitting state a2
(fig. 4).
a1 a6 x1 x2 x3 x4 x5 x6 x7 x8 x9 x10
w1 1 0 1 1 1 1 1 0 0 0 0 0
w2 0 1 0 0 0 0 0 1 1 1 1 1

Figure 4. Matrix W for splitting state a2

The matrix W has two rows. The row w1 corresponds to the transition from the state a1 to the state a2, and the row w2
corresponds to the transition from the state a6 to the state a2. The execution of the algorithm 2 leads to a partition of rows of
the matrix W on two subsets: W1 = {w1} and W2 = {w2}. So the state a2 splitting on two states as is shown in fig. 5.
 y=0 y=1 y=0
!(!x1x2!x3x4!x5) 1
a1 a3 a4
!x x
1
2 !x x
3 !4 x5
y=1 x1
a2_1
!x1
x1 1

a2_2 !x1
! x 10 y=1
!(!x6x7!x8x9!x10) x !x 8x 9
!x 6 7

1 a5
a6
y=0 y=1

Figure. 5. The graph of the FSM after splitting state a2

s p
The new values of B(ai), X(ai), ri, li , and li are represented in Table 2. Now we have lmax = lmid = 1 and according
to (6) performance of algorithm 1 is completed.
s p
Table 2. The values of B(ai), X(ai), ri, li , and li after splitting of state a2
State B(ai) X(ai) ri lis lip
a1 {a6} {x6,x7,x8,x9,x10} 6 1 1
a2_1 {a1} {x1,x2,x3,x4,x5} 6 1 1
a2_2 {a6} {x6,x7,x8,x9,x10} 6 1 1
a3 {a1} {x1,x2,x3,x4,x5} 6 1 1
a4 {a2_1,a3} {x1} 3 1 1
a5 {a2_2,a4} {x1} 3 1 1
a6 {a5} Ø1 1 1 1
Note 1. Ø is an empty set.

Thus, for given FSM we reduced by splitting state a2 the number of LUT levels with 3 to 1, in case of a sequential
decomposition, and with 2 to 1, in case of a parallel decomposition.

4. Experimental results
An efficiency of the offered synthesis method was checked with implementation of the initial FSM (fig. 1) and the
FSM after splitting of state a2 (fig. 2) in FPGAs from Altera by means of the design tool Quartus II version 15.0. The main
optimization criterion had been selected the parameter «speed». The method of state assignment for the initial FSM has
been selected «one-hot», and for the FSM after synthesis has been selected «user» (the codes of states are defined from the
FSM description).
Table 3 represents results of experimental researches of a considered synthesis method of high-speed FSMs for
various FPGA families, where nLUT1 and nLUT2 are the number of used LUT with implementation of the initial FSM and
the synthesized FSM respectively; F1 and F2 are the frequency of functioning (in MHz) for the initial FSM and the
synthesized FSM respectively; F1/F2 is a relation of appropriate parameters.
Table 3. Results of experimental researches.

Family nLUT F1 nLUT F2 F2/F1

1 2
Arria II GX 8 1307 7 1269 0.97
Cyclone IV E 9 778 10 793 1.02
Cyclone IV GX 9 729 10 802 1.10
Cyclone V 6 686 6 925 1.35
MAX 10 10 800 11 816 1.02
MAX V 10 343 9 314 0.92
MAX II 10 389 9 593 1.52
 Table 3 analysis shows that application of offered method increased a performance of the FSM for 5 FPGA
families from 7. Thus, for family MAX II the performance is increased by 1.52 times, and for family Cyclone V the
performance increased by 1.35 times. Besides, an implementation cost decreases as a result of an application of the
presented synthesis method for families Arria II GX, MAX V, and MAX II.

5. Conclusion
The represented results of experimental researches showed the following. In despite of the fact that in the
considered example the rank of transition functions has been reduced from 12 to 6 that allowed to reduce the number of
LUT levels from 3 to 1, in case of the sequential decomposition, and from 2 to 1, in case of the parallel decomposition,
however performance of the FSM increased not for all FPGA families. It speaks complexity of the synthesis task of high-
speed FSMs, for example, in comparison with the task of a reduction of the implementation cost. The matter is that a
performance of an FSM depends not only from results of a logical synthesis, but also from results of placing and routing.
The reduction of the implementation cost for some families FPGA, as a result of application of the given method, speaks
simply: with the reduction of the number of LUT levels, an amount LUT also decreases.
Note that the offered method can be applied also with implementation of high-speed FSMs in chips ASIC. For this
purpose it is enough for the specific ASIC architecture to define the estimations (3) and (4) a number of circuit levels. The
further development of synthesis methods of high-speed FSMs can go by the way using of special structural models of
FSMs, using the architectural properties FPGA, special control of a clock signal, using embedded memory blocks, etc.
This research was partially supported by Bialystok University of Technology, Poland, grant no. S/WI/1/2013.

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