MX25L5121E

MX25L1021E

MX25L5121E, MX25L1021E

DATASHEET

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 MX25L5121E
MX25L1021E

Contents
FEATURES................................................................................................................................................................... 4
GENERAL............................................................................................................................................................. 4
PERFORMANCE.................................................................................................................................................. 4
SOFTWARE FEATURES...................................................................................................................................... 4
HARDWARE FEATURES...................................................................................................................................... 4
GENERAL DESCRIPTION.......................................................................................................................................... 5
PIN CONFIGURATIONS .............................................................................................................................................. 6
PIN DESCRIPTION....................................................................................................................................................... 6
BLOCK DIAGRAM........................................................................................................................................................ 7
MEMORY ORGANIZATION.......................................................................................................................................... 8
Table 1-1. Memory Organization (512Kb)............................................................................................................ 8
Table 1-2. Memory Organization (1Mb)................................................................................................................ 8
DEVICE OPERATION................................................................................................................................................... 9
Figure 1. Serial Modes Supported......................................................................................................................... 9
DATA PROTECTION................................................................................................................................................... 10
Table 2. Protected Area Sizes............................................................................................................................. 10
COMMAND DESCRIPTION........................................................................................................................................ 11
Table 3. Command Set........................................................................................................................................ 11
(1) Write Enable (WREN).................................................................................................................................... 12
(2) Write Disable (WRDI)..................................................................................................................................... 12
(3) Read Identification (RDID)............................................................................................................................. 12
Table 4. ID Definitions ........................................................................................................................................ 12
(4) Read Status Register (RDSR)....................................................................................................................... 13
Table 5. Status Register...................................................................................................................................... 13
(5) Write Status Register (WRSR)....................................................................................................................... 14
Table 6. Protection Modes................................................................................................................................... 14
(6) Read Data Bytes (READ).............................................................................................................................. 15
(7) Read Data Bytes at Higher Speed (FAST_READ)........................................................................................ 15
(8) Sector Erase (SE).......................................................................................................................................... 15
(9) Block Erase (BE)............................................................................................................................................ 15
(10) Chip Erase (CE)........................................................................................................................................... 16
(11) Page Program (PP)...................................................................................................................................... 16
(12) Deep Power-Down (DP).............................................................................................................................. 16
(13) Release from Deep Power-Down (RDP)..................................................................................................... 17
POWER-ON STATE.................................................................................................................................................... 18
Program/ Erase flow with read array data........................................................................................................... 19
ELECTRICAL SPECIFICATIONS............................................................................................................................... 20

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 MX25L5121E
MX25L1021E

ABSOLUTE MAXIMUM RATINGS...................................................................................................................... 20

Figure 2. Maximum Negative Overshoot Waveform........................................................................................... 20
CAPACITANCE TA = 25°C, f = 1.0 MHz.............................................................................................................. 20
Figure 3. Maximum Positive Overshoot Waveform............................................................................................. 20
Figure 4. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL............................................................... 21
Figure 5. OUTPUT LOADING............................................................................................................................ 21
Table 7. DC CHARACTERISTICS (Temperature = 0°C to 70°C for Commercial grade, VCC = 2.7V ~ 3.6V) .. 22
Table 8. AC CHARACTERISTICS (Temperature = 0°C to 70°C for Commercial grade, VCC = 2.7V ~ 3.6V) .. 23
Timing Analysis......................................................................................................................................................... 24
Figure 6. Serial Input Timing............................................................................................................................... 24
Figure 7. Output Timing....................................................................................................................................... 24
Figure 8. WP# Disable Setup and Hold Timing during WRSR when SRWD=1.................................................. 25
Figure 9. Write Enable (WREN) Sequence (Command 06)................................................................................ 25
Figure 10. Write Disable (WRDI) Sequence (Command 04)............................................................................... 25
Figure 11. Read Identification (RDID) Sequence (Command 9F)....................................................................... 26
Figure 12-1. Read Status Register (RDSR) Sequence (Command 05).............................................................. 27
Figure 12-2. Read Status Register (RDSR) Sequence (Command 05).............................................................. 27
Figure 13. Write Status Register (WRSR) Sequence (Command 01)................................................................ 28
Figure 14. Read Data Bytes (READ) Sequence (Command 03)....................................................................... 28
Figure 15. Read at Higher Speed (FAST_READ) Sequence (Command 0B).................................................... 29
Figure 16. Sector Erase (SE) Sequence (Command 20)................................................................................... 29
Figure 17. Block Erase (BE) Sequence (Command D8).................................................................................... 30
Figure 18. Chip Erase (CE) Sequence (Command 60 or C7)............................................................................ 30
Figure 19. Page Program (PP) Sequence (Command 02)................................................................................. 30
Figure 20. Deep Power Down (DP) Sequence (Command B9)......................................................................... 31
Figure 21. Release from Deep Power Down (RDP) Sequence (Command AB)................................................ 31
Figure 23. Power-Up Timing................................................................................................................................ 32
Table 9. Power-Up Timing................................................................................................................................... 32
INITIAL DELIVERY STATE.................................................................................................................................. 32
RECOMMENDED OPERATING CONDITIONS.......................................................................................................... 33
Figure 24. AC Timing at Device Power-Up.......................................................................................................... 33
Figure 25. Power-Down Sequence..................................................................................................................... 34
ERASE AND PROGRAMMING PERFORMANCE..................................................................................................... 35
DATA RETENTION .................................................................................................................................................... 35
LATCH-UP CHARACTERISTICS............................................................................................................................... 35
ORDERING INFORMATION....................................................................................................................................... 36
PART NAME DESCRIPTION...................................................................................................................................... 37
PACKAGE INFORMATION......................................................................................................................................... 38

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 ADVANCED INFORMATION
MX25L5121E
MX25L1021E
512K-BIT [x 1] CMOS SERIAL FLASH MEMORY
1M-BIT [x 1] CMOS SERIAL FLASH MEMORY
FEATURES
GENERAL
• Serial Peripheral Interface compatible -- Mode 0 and Mode 3
• 512K: 524,288 x 1 bit structure
1M: 1,048,576 x 1 bit structure
• 16 Equal Sectors with 4K bytes each (512Kb)
32 Equal Sectors with 4K bytes each (1Mb)
- Any Sector can be erased individually
• 1 Equal Blocks with 64K byte each (512Kb)
2 Equal Blocks with 64K byte each (1Mb)
- Any Block can be erased individually
• Program Capability
- Byte base
- Page base (32 bytes)
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V

PERFORMANCE
• Performance
- Fast Read: 45MHz serial clock
- Fast program time: 180us(typ.) and 650us(max.)/page
- Fast erase time: 90ms (typ.)/sector ; 1s (typ.)/block
• Low Power Consumption
- Low active read current: 5mA(max.) at 25MHz, 10mA(max.) at 45MHz
- Low active programming current: 12mA (max.)
- Low active erase current: 15mA (max.)
- Low standby current: 20uA (typ.)
- Deep power down current: 2uA (typ.)
• Typical 100,000 erase/program cycles
• 20 years data retention

SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Block Lock protection
- The BP0~BP1 status bits defines the size of the area to be software protected against Program and Erase
instructions
• Auto Erase and Auto Program Algorithm
- Automatically erases and verifies data at selected sector
- Automatically programs and verifies data at selected page by an internal algorithm that automatically times the
program pulse widths (Any page to be programed should have page in the erased state first)
• Status Register Feature
• Electronic Identification
- JEDEC 1-byte manufacturer ID and 2-bytes device ID

HARDWARE FEATURES
• SCLK Input
- Serial clock input
• SI Input

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 MX25L5121E
MX25L1021E

- Serial Data Input

• SO Output
- Serial Data Output
• WP# pin
- Hardware write protection

• PACKAGE
- 8-pin SOP (150mil)
- 8-pin TSSOP (173mil) for MX25L5121E only
- All Pb-free devices are RoHS Compliant

GENERAL DESCRIPTION

The device feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus.
The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access
to the device is enabled by CS# input.

The device provides sequential read operation on whole chip.

After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the spec-
ified page or sector locations will be executed. Program command is executed on page (32 bytes) basis, and erase
command is executes on sector, or block, or whole chip.

To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.

When the device is not in operation and CS# is high, it is put in Standby Mode and draws less than 30uA (typical:20uA)
DC current.

The device utilizes Macronix proprietary memory cell, which reliably stores memory contents even after typical
100,000 program and erase cycles.

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PIN CONFIGURATIONS PIN DESCRIPTION

8-PIN SOP (150mil) SYMBOL DESCRIPTION
CS# Chip Select
CS# 1 8 VCC SI Serial Data Input (for 1 x I/O)
SO 2 7 NC
SO Serial Data Output (for 1 x I/O)
WP# 3 6 SCLK
GND 4 5 SI SCLK Clock Input
NC NC pin (Not connect)
WP# Write Protection

8-PIN TSSOP (173mil) for MX25L5121E only VCC 2.7V to 3.6V Power Supply
GND Ground
CS# 1 8 VCC
SO 2 7 NC
WP# 3 6 SCLK
GND 4 5 SI

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 MX25L5121E
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BLOCK DIAGRAM

Address

X-Decoder
Generator
Memory Array

Page Buffer

Data
SI Register
Y-Decoder
SRAM
Buffer

Sense
Mode State Amplifier
CS# Logic Machine HV
Generator

SCLK Clock Generator

Output
SO
Buffer

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 MX25L5121E
MX25L1021E

MEMORY ORGANIZATION
Table 1-1. Memory Organization (512Kb) Table 1-2. Memory Organization (1Mb)

Block Sector Address Range Block Sector Address Range

15 00F000h 00FFFFh 31 01F000h 01FFFFh
: : : 1 : : :
3 003000h 003FFFh 16 010000h 010FFFh
0
2 002000h 002FFFh 15 00F000h 00FFFFh
1 001000h 001FFFh : : :
0 000000h 000FFFh 3 003000h 003FFFh
0
2 002000h 002FFFh
1 001000h 001FFFh
0 000000h 000FFFh

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DEVICE OPERATION

1. Before a command is issued, status register should be checked to ensure device is ready for the intended op-
eration.

2. When incorrect command is inputted to this LSI, this LSI becomes Standby Mode and keeps the Standby Mode
until next CS# falling edge. In Standby Mode, all SO pins of this LSI should be High-Z.

3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until
next CS# rising edge.

4. Input data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK.
The difference of Serial mode 0 and mode 3 is shown as Figure 1.

5. For the following instructions: RDID, RDSR, READ and FAST_READ the shifted-in instruction sequence is fol-
lowed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the following
instructions: WREN, WRDI, WRSR, SE, PP, RDP, and DP the CS# must go high exactly at the byte boundary;
otherwise, the instruction will be rejected and not executed.

6. During the progress of Program, Erase operation, to access the memory array is neglected and not affect the
current operation of Program and Erase.

Figure 1. Serial Modes Supported

CPOL CPHA shift in shift out

(Serial mode 0) 0 0 SCLK

(Serial mode 3) 1 1 SCLK

SI MSB

SO MSB

Note:
CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not
transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is
supported.

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DATA PROTECTION

The device is designed to offer protection against accidental erasure or programming caused by spurious system
level signals that may exist during power transition. During power up the device automatically resets the state ma-
chine in the Standby Mode. In addition, with its control register architecture, alteration of the memory contents only
occurs after successful completion of specific command sequences. The device also incorporates several features
to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system noise.

• Valid command length checking: The command length will be checked whether it is at byte base and completed
on byte boundary.

• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before
other command to change data. The WEL bit will return to reset stage under following situation:
- Power-up
- Write Disable (WRDI) command completion
- Write Status Register (WRSR) command completion
- Page Program (PP) command completion
- Sector Erase (SE) command completion
- Block Erase (BE) command completion
- Chip Erase (CE) command completion

• Software Protection Mode (SPM): by using BP0-BP1 bits to set the part of Flash protected from data change.

• Hardware Protection Mode (HPM): by using WP# going low to protect the BP0-BP1 bits and SRWD bit from data
change.

• Deep Power Down Mode: By entering Deep Power Down Mode, the flash device also is under protected from
writing all commands except Release from Deep Power Down Mode command (RDP).

Table 2. Protected Area Sizes

Status bit Protect level
BP1 BP0 MX25L5121E MX25L1021E
0 0 0 (none)
0 (none)
0 1 1 (All) 1 (1 block)
1 0 2 (All) 2 (All)
1 1 3 (All) 3 (All)

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COMMAND DESCRIPTION
Table 3. Command Set
WRSR RDID RDSR FAST READ
Command WREN (write WRDI (write READ (read
(write status (read identific- (read status (fast read
(byte) enable) disable) data)
register) ation) register) data)
1st byte 06 (hex) 04 (hex) 01 (hex) 9F (hex) 05 (hex) 03 (hex) 0B (hex)
AD1
2nd byte AD1
(A23-A16)
AD2
3rd byte AD2
(A15-A8)
AD3
4th byte AD3
(A7-A0)
5th byte Dummy
sets the (WEL) resets the to write new outputs to read out n bytes read n bytes read
write enable (WEL) write values of the JEDEC the values out until CS# out until CS#
latch bit enable latch status register ID: 1-byte of the status goes high goes high
Action
bit Manufacturer register
ID & 2-bytes
Device ID

RDP (Release
Command SE (sector BE (block CE (chip PP (page DP (Deep
from deep
(byte) erase) erase) erase) program) power down)
power down)
1st byte 20 (hex) 52 or D8 (hex) 60 or C7 (hex) 02 (hex) B9 (hex) AB (hex)
2nd byte AD1 AD1 AD1
3rd byte AD2 AD2 AD2
4th byte AD3 AD3 AD3
to erase the to erase the to erase to program enters Deep release from
selected selected whole chip the selected Power Down Deep Power
Action sector block page Mode Down Mode

Note 1: It is not recommended to adopt any other code not in the command definition table, which will potentially
enter the hidden mode.
Note 2: Value "1" should be input to the un-used significant bits of address bits by user (e.g. A17~A23(MSB) in
MX25L1021E ; A16-A23(MSB) in MX25L5121E)

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(1) Write Enable (WREN)

The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, SE,
BE, CE and WRSR which are intended to change the device content, should be set every time after the WREN in-
struction setting the WEL bit.

The sequence of issuing WREN instruction is: CS# goes low→ sending WREN instruction code→CS# goes high. (Please
refer to Figure 9)

(2) Write Disable (WRDI)

The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit.

The sequence of issuing WRDI instruction is: CS# goes low→sending WRDI instruction code→CS# goes high. (Please
refer to Figure 10)

The WEL bit is reset by following situations:

- Power-up
- Write Disable (WRDI) instruction completion
- Write Status Register (WRSR) instruction completion
- Page Program (PP) instruction completion
- Sector Erase (SE) instruction completion
- Block Erase (BE) instruction completion
- Chip Erase (CE) instruction completion

(3) Read Identification (RDID)

The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-bytes. The MXIC
Manufacturer ID is C2(hex), the memory type ID is 22(hex) as the first-byte device ID, and the individual device ID
of second-byte ID are listed as table of "ID Definitions". (Please refer to table 4)

The sequence of issuing RDID instruction is: CS# goes low→sending RDID instruction code→24-bits ID data out on
SO→ to end RDID operation can use CS# to high at any time during data out. (Please refer to Figure 11)

While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cy-
cle of program/erase operation which is currently in progress. When CS# goes high, the device is at Standby Mode.

Table 4. ID Definitions

MX25L5121E MX25L1021E
manufacturer memory manufacturer memory
RDID Command memory type memory type
ID density ID density
C2 22 10 C2 22 11

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(4) Read Status Register (RDSR)

The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even
in program/erase condition) and continuously. It is recommended to check the Write in Progress (WIP) bit before
sending a new instruction when a program or erase operation is in progress.

The sequence of issuing RDSR instruction is: CS# goes low→sending RDSR instruction code→Status Register
data out on SO (Please refer to Figure 12-1, Figure 12-2)

The definition of the status register bits is as below:

WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase
progress. When WIP bit sets to 1, which means the device is busy in program/erase progress. When WIP bit sets to 0,
which means the device is not in progress of program/erase register cycle.

WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable
latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/
erase instruction. When WEL bit sets to 0, which means no internal write enable latch; the device will not accept
program/erase instruction.

BP1, BP0 bits. The Block Protect (BP1, BP0) bits, volatile bits, indicate the protected area(as defined in table 1) of
the device to against the program/erase instruction without hardware protection mode being set. To write the Block
Protect (BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be executed. Those bits define
the protected area of the memory to against Page Program (PP), Sector Erase (SE), Block Erase (BE) and Chip
Erase(CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be executed)

SRWD bit. The Status Register Write Disable (SRWD) bit, volatile bit, is operated together with Write Protection (WP#)
pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and WP# pin
signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is no longer ac-
cepted for execution and the SRWD bit and Block Protect bits (BP1, BP0) are read only.

Table 5. Status Register

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
BP1 BP0
SRWD (status WEL WIP
(level of (level of
register write Reserved Reserved Reserved (write enable (write in
protected protected
protect) latch) progress bit)
block) block)
1=write 1=write
1=status
enable operation
register write 0 0 0 (note 1) (note 1)
0=not write 0=not in write
disable
enable operation

Note: 1. See the table "Protected Area Sizes". The default BP0-BP2 values are "1" (protected).
2. The SRWD default value is "0"

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(5) Write Status Register (WRSR)

The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the
Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in ad-
vance. The WRSR instruction can change the value of Block Protect (BP1, BP0) bits to define the protected area
of memory (as shown in table 1). The WRSR also can set or reset the Status Register Write Disable (SRWD) bit in
accordance with Write Protection (WP#) pin signal. The WRSR instruction cannot be executed once the Hardware
Protected Mode (HPM) is entered.

The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Register
data on SI→ CS# goes high. (see Figure 13)

The WRSR instruction has no effect on b6, b5, b4, b1, b0 of the status register.

The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write
in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1
during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL)
bit is reset.

Table 6. Protection Modes

Mode Status register condition WP# and SRWD bit status Memory
Status register can be written
Software protection WP#=1 and SRWD bit=0, or The protected area
in (WEL bit is set to "1") and
mode (SPM) WP#=0 and SRWD bit=0, or cannot
the SRWD, BP0-BP1
WP#=1 and SRWD=1 be program or erase.
bits can be changed
The SRWD, BP0-BP1 of The protected area
Hardware protection
status register bits cannot be WP#=0, SRWD bit=1 cannot
mode (HPM)
changed be program or erase.

Note:
1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 1.

As the table above showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM).

Software Protected Mode (SPM):

- When SRWD bit=0, no matter WP# is low or high, the WREN instruction may set the WEL bit and can change
the values of SRWD, BP1, BP0. The protected area, which is defined by BP1, BP0, is at software protected
mode (SPM).
- When SRWD bit=1 and WP# is high, the WREN instruction may set the WEL bit can change the values of
SRWD, BP1, BP0. The protected area, which is defined by BP1, BP0, is at software protected mode (SPM)

Note: If SRWD bit=1 but WP# is low, it is impossible to write the Status Register even if the WEL bit has previ-
ously been set. It is rejected to write the Status Register and not be executed.

Hardware Protected Mode (HPM):

- When SRWD bit=1, and then WP# is low (or WP# is low before SRWD bit=1), it enters the hardware protected
mode (HPM). The data of the protected area is protected by software protected mode by BP1, BP0 and hard-
ware protected mode by the WP# to against data modification.

Note: to exit the hardware protected mode requires WP# driving high once the hardware protected mode is
entered. If the WP# pin is permanently connected to high, the hardware protected mode can never be entered;
only can use software protected mode via BP1, BP0.

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(6) Read Data Bytes (READ)

The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out
on the falling edge of SCLK at a maximum frequency fC. The first address can be at any location. The address is
automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be
read out at a single READ instruction.

This product does not provide the function of read around. After reading through density 512Kb or 1Mb, CS# must
go high. Otherwise, the data correctness will not be guaranteed. If the device needs to read data again, it must
issue read command once more.

The sequence of issuing READ instruction is: CS# goes low→ sending READ instruction code→ 3-bytes address
on SI→data out on SO→to end READ operation can use CS# to high at any time during data out. (Please refer to
Figure 14)

(7) Read Data Bytes at Higher Speed (FAST_READ)

The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and
data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at
any location. The address is automatically increased to the next higher address after each byte data is shifted out,
so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when
the highest address has been reached.

The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ instruction code→
3-byte address on SI→ 1-dummy byte address on SI→data out on SO→ to end FAST_READ operation can use
CS# to high at any time during data out. (Please refer to Figure 15)

While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any im-
pact on the Program/Erase/Write Status Register current cycle.

(8) Sector Erase (SE)

The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for
any 4K-bytes sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit be-
fore sending the Sector Erase (SE). Any address of the sector (Please refer to table 1) is a valid address for Sector
Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the eighth bit of last address byte been
latched-in); otherwise, the instruction will be rejected and not executed.

Address bits [Am-A12] (Am is the most significant address) select the sector address.

The sequence of issuing SE instruction is: CS# goes low→sending SE instruction code→3-bytes address on SI
→CS# goes high. (Please refer to Figure 16)

The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the
tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset.

(9) Block Erase (BE)

The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for
64K-byte sector erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL)

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MX25L1021E

bit before sending the Block Erase (BE). Any address of the block (see table 2) is a valid address for Block Erase (BE)
instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in);
otherwise, the instruction will be rejected and not executed.

The sequence is shown as Figure 17.

The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the
tBE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset.

(10) Chip Erase (CE)

The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruc-
tion must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). Any address of the
sector (see table 1) is a valid address for Chip Erase (CE) instruction. The CS# must go high exactly at the byte
boundary( the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not ex-
ecuted.

The sequence is shown as Figure 18.

The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE
timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset.

(11) Page Program (PP)

The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction
must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). After the instruction
and address input, data to be programmed is input sequentially. The internal sequence controller will sequentially
program the data from the initial address. If the transmitted data goes beyond the page boundary, the internal se-
quence controller may not function properly and the content of the device will not be guaranteed. Therefore, If the
initial A4-A0 (The five least significant address bits) are set to all 0, maximum 32 bytes of data can be input sequen-
tially. If the initial address A4-A0 (The five least significant address bits) are not set to all 0, maximum bytes of data
input will be the subtraction of the initial address A4-A0 from 32bytes. The data exceeding 32bytes data is not sent
to device. In this case, data is not guaranteed.

The sequence of issuing PP instruction is: CS# goes low → sending PP instruction code → 3-bytes address on SI→
at least 1-byte on data on SI → CS# goes high. (Please refer to Figure 19)

The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte
boundary( the eighth bit of data being latched in), otherwise the instruction will be rejected and will not be executed.

The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 during the
tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset.

(12) Deep Power-Down (DP)

The Deep Power Down (DP) instruction is for setting the device on the minimizing the power consumption (to enter-
ing the Deep Power Down Mode), the standby current is reduced from ISB1 to ISB2. The Deep Power Down Mode
requires the Deep Power Down (DP) instruction to enter, during the Deep Power Down Mode, the device is not ac-

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MX25L1021E

tive and all Read/Write/Program/Erase instruction are ignored.

The sequence of issuing DP instruction is: CS# goes low→sending DP instruction code→ CS# goes high. (Please
refer to Figure 20)

Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power Down Mode (RDP)
instruction. When Power-down, the Deep Power Down Mode automatically stops, and when power-up, the device
automatically is in Standby Mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest
eighth bit of instruction code been latched-in); otherwise, the instruction will not executed. As soon as Chip Select (CS#)
goes high, a delay of tDP is required before entering the Deep Power Down Mode.

(13) Release from Deep Power-Down (RDP)

The Release from Deep Power Down (RDP) instruction is terminated by driving Chip Select (CS#) High. When
Chip Select (CS#) is driven High, the device is put in the Standby Mode. If the device was not previously in the
Deep Power Down Mode, the transition to the Standby Mode is immediate. If the device was previously in the Deep
Power Down Mode, though, the transition to the Standby Mode is delayed by tRES1, and Chip Select (CS#) must
remain High for at least tRES1(max), as specified in Table 8. AC Characteristics. Once in the Standby Mode, the
device waits to be selected, so that it can receive, decode and execute instructions. The RDP instruction is only for
releasing from Deep Power Down Mode.

The sequence is shown as Figure 21. Even in Deep Power Down Mode, the RDP is also allowed to be executed,
only except the device is in progress of program/erase cycle; there's no effect on the current program/erase cycle
in progress.

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POWER-ON STATE

The device is at below states when power-up:

- Standby Mode ( please note it is not Deep Power Down Mode)
- Write Enable Latch (WEL) bit is reset

The device must not be selected during power-up and power-down stage unless the VCC achieves below correct
level:
- VCC minimum at power-up stage and then after a delay of tVSL
- GND at power-down
Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.

An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change
during power up state.

For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not
guaranteed. The read, write, erase, and program command should be sent after the below time delay:
- tVSL after VCC reached VCC minimum level

Note:
- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommend-
ed. (generally around 0.1uF)

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Program/ Erase flow with read array data

start

WREN command

RDSR command*

No
WEL=1?

Yes
Program/erase command

Write program data/address

(Write erase address)

RDSR command

No
WIP=0?

Yes
RDSR command

Read WEL=0

Read array data

(same address of PGM/ERS)

No
Verify OK?

Yes
Program/erase successfully Program/erase fail

Program/erase Yes
another block?

No
Program/erase completed

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ELECTRICAL SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

RATING VALUE
Ambient Operating Temperature Commercial grade 0°C to 70°C
Storage Temperature -40°C to 125°C
Applied Input Voltage -0.5V to 4.6V
Applied Output Voltage -0.5V to 4.6V
VCC to Ground Potential -0.5V to 4.6V

Notes:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is stress rating only and functional operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended period may affect reliability.
2. Specifications contained within the following tables are subject to change.
3. During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, please
refer to Figure 2, 3.

Figure 2. Maximum Negative Overshoot Waveform Figure 3. Maximum Positive Overshoot Waveform

20ns 20ns 20ns

Vss
Vcc + 2.0V

Vss-2.0V
Vcc
20ns
20ns 20ns

CAPACITANCE TA = 25°C, f = 1.0 MHz

SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS

CIN Input Capacitance 6 pF VIN = 0V
COUT Output Capacitance 8 pF VOUT = 0V

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Figure 4. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL

Input timing referance level Output timing referance level

0.8VCC
0.7VCC AC 0.7VCC
Measurement
0.3VCC Level 0.3VCC
0.2VCC

Note: Input pulse rise and fall time are <8ns

Notes: Rise time means 0.2VCC to 0.8VCC; Fall time means 0.8VCC to 0.2VCC.

Figure 5. OUTPUT LOADING

DEVICE UNDER 2.7K ohm

TEST +3.3V

CL
6.2K ohm DIODES=IN3064
OR EQUIVALENT

CL=30pF Including jig capacitance

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Table 7. DC CHARACTERISTICS (Temperature = 0°C to 70°C for Commercial grade, VCC = 2.7V ~ 3.6V)

SYMBOL PARAMETER NOTES MIN. TYP. MAX. UNITS TEST CONDITIONS

VCC = VCC Max,
ILI Input Load Current 1 ±2 uA
VIN = VCC or GND
VCC = VCC Max,
ILO Output Leakage Current 1 ±2 uA
VIN = VCC or GND
VIN = VCC or GND,
ISB1 VCC Standby Current 1 20 30 uA
CS# = VCC
Deep Power Down VIN = VCC or GND,
ISB2 2 8 uA
Current CS# = VCC
f=45MHz,
10 mA SCLK=0.1VCC/0.9VCC,
SO=Open
ICC1 VCC Read 1
f=25MHz,
5 mA SCLK=0.1VCC/0.9VCC,
SO=Open
VCC Program Current Program in Progress,
ICC2 1 12 mA
(PP) CS# = VCC
VCC Write Register Program Status Register in
ICC3 1 15 mA
(WRSR) Current Progress, CS#=VCC
VCC Sector Erase Erase in Progress,
ICC4 1 15 mA
Current (SE) CS#=VCC
VIL Input Low Voltage -0.5 0.2VCC V
VIH Input High Voltage 0.8VCC VCC+0.4 V
VOL Output Low Voltage 0.4 V IOL = 1.6mA
VOH Output High Voltage VCC-0.2 V IOH = -100uA
Low VCC Write Inhibit
VWI 3 2.1 2.3 2.5 V
Voltage

Notes :
1. Typical values at VCC = 3.3V, T = 25°C. These currents are valid for all product versions (package and speeds).
2. Typical value is calculated by simulation.
3. Not 100% tested.

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Table 8. AC CHARACTERISTICS (Temperature = 0°C to 70°C for Commercial grade, VCC = 2.7V ~ 3.6V)
Symbol Alt. Parameter Min. Typ. Max. Unit
fSCLK fC Clock Frequency for FAST_READ 1KHz 45 MHz
Clock Frequency for the following instructions:
fRSCLK fR READ, PP, SE, BE, CE, DP, RDP, WREN, RDID, RDSR, 1KHz 25 MHz
WRSR
@ 25 MHz 18 ns
tCH(1) tCLH Clock High Time
@ 45 MHz 10 ns
@ 25 MHz 18 ns
tCL(1) tCLL Clock Low Time
@ 45 MHz 10 ns
tCLCH(2) Clock Rise Time (3) (peak to peak) 0.1 V/ns
tRISE(2) Clock Rise Time (3) 10 ns/V
tCHCL(2) Clock Fall Time (3) (peak to peak) 0.1 V/ns
tFALL(2) Clock Fall Time (3) 10 ns/V
tSLCH tCSS CS# Active Setup Time (relative to SCLK) 20 ns
tCHSL CS# Not Active Hold Time (relative to SCLK) 20 ns
tDVCH tDSU Data In Setup Time 4 ns
tCHDX tDH Data In Hold Time 6 ns
tCHSH CS# Active Hold Time (relative to SCLK) 20 ns
tSHCH CS# Not Active Setup Time (relative to SCLK) 20 ns
Read 50 ns
tSHSL(3) tCSH CS# Deselect Time
Write/Erase/Program 50 ns
tSHQZ(2) tDIS Output Disable Time 20 ns
@ 25 MHz 18 ns
tCLQV tV Clock Low to Output Valid
@ 45 MHz 18 ns
tCLQX tHO Output Hold Time 0 ns
tWHSL(4) Write Protect Setup Time 20 ns
tSHWL(4) Write Protect Hold Time 100 ns
tW Write Status Register Cycle Time 5 15 ms
tDP(2) CS# High to Deep Power Down Mode 20 us
tRES1(2) CS# High to Standby Mode without Electronic Signature Read 20 us
tPP Page Program Cycle Time (32 Bytes) 180 650 us
tSE Sector Erase Cycle Time (4K Bytes) 90 300 ms
tRPD1 CS# High to Power-Down 100 ns
tBE Block Erase Cycle Time 1 2 s
512Kb 1 2 s
tCE Chip Erase Cycle Time
1Mb 1 2 s
Notes:
1. tCH + tCL must be greater than or equal to 1/ f (fC).
2. Value guaranteed by characterization, not 100% tested in production.
3. Test condition is shown as Figure 4, 5.
4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.

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Timing Analysis

Figure 6. Serial Input Timing

tSHSL

CS#

tCHSL tSLCH tCHSH tSHCH

SCLK

tDVCH tCHCL

tCHDX tCLCH

SI MSB LSB

High-Z
SO

Figure 7. Output Timing

CS#
tCH

SCLK
tCLQV tCLQV tCL tSHQZ

tCLQX tCLQX

SO LSB

SI ADDR.LSB IN

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Figure 8. WP# Disable Setup and Hold Timing during WRSR when SRWD=1

WP#
tSHWL
tWHSL

CS#

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK

SI 01

High-Z
SO

Figure 9. Write Enable (WREN) Sequence (Command 06)

CS#

0 1 2 3 4 5 6 7
SCLK

Command

SI 06

High-Z
SO

Figure 10. Write Disable (WRDI) Sequence (Command 04)

CS#

0 1 2 3 4 5 6 7
SCLK

Command

SI 04

High-Z
SO

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Figure 11. Read Identification (RDID) Sequence (Command 9F)

CS#

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 28 29 30 31
SCLK

Command

SI 9F

Manufacturer ID Device ID
High-Z
SO 7 6 5 3 2 1 0 15 14 13 3 2 1 0

MSB MSB

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Figure 12-1. Read Status Register (RDSR) Sequence (Command 05)

CS#

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK

command

SI 05

Status Register Out Status Register Out

High-Z
SO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7

MSB MSB

Figure 12-2. Read Status Register (RDSR) Sequence (Command 05)

CS#

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK

Command

SI 05
Status Register Out
High-Z
SO 7 6 5 4 3 2 1 0

MSB

CS#

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK

Command

SI 05
Status Register Out
High-Z
SO 7 6 5 4 3 2 1 0

MSB

CS#

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK

Command

SI 05
Status Register Out
High-Z
SO 7 6 5 4 3 2 1 0

MSB

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Figure 13. Write Status Register (WRSR) Sequence (Command 01)

CS#

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK

command Status
Register In

SI 01 7 6 5 4 3 2 1 0

High-Z MSB
SO

Figure 14. Read Data Bytes (READ) Sequence (Command 03)

CS#

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39

SCLK

command 24-Bit Address

SI 03 23 22 21 3 2 1 0
MSB
Data Out 1 Data Out 2
High-Z
SO 7 6 5 4 3 2 1 0 7
MSB

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Figure 15. Read at Higher Speed (FAST_READ) Sequence (Command 0B)

CS#

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
SCLK

Command 24 BIT ADDRESS

SI 0B 23 22 21 3 2 1 0

High-Z
SO

CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

SCLK

Dummy Byte

SI 7 6 5 4 3 2 1 0

DATA OUT 1 DATA OUT 2

SO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7

MSB MSB MSB

Figure 16. Sector Erase (SE) Sequence (Command 20)

CS#

0 1 2 3 4 5 6 7 8 9 29 30 31
SCLK

Command 24 Bit Address

SI 20 23 22 2 1 0
MSB

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Figure 17. Block Erase (BE) Sequence (Command D8 or 52)

CS#

0 1 2 3 4 5 6 7 8 9 29 30 31
SCLK

Command 24 Bit Address

SI D8 23 22 2 1 0
MSB

Note: BE command is D8(hex).

Figure 18. Chip Erase (CE) Sequence (Command 60 or C7)

CS#

0 1 2 3 4 5 6 7
SCLK

Command

SI 60 or C7

Note: CE command is 60(hex) or C7(hex).

Figure 19. Page Program (PP) Sequence (Command 02)

CS#

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
SCLK

Command 24-Bit Address Data Byte 1

SI 02 23 22 21 3 2 1 0 7 6 5 4 3 2 1 0

MSB MSB

CS#
280
281
282
283
284
285
286
287

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

SCLK

Data Byte 2 Data Byte 3 Data Byte 32

SI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

MSB MSB MSB

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Figure 20. Deep Power Down (DP) Sequence (Command B9)

CS#

0 1 2 3 4 5 6 7 tDP

SCLK

Command

SI B9

Standby Mode Deep Power Down Mode

Figure 21. Release from Deep Power Down (RDP) Sequence (Command AB)

CS#

0 1 2 3 4 5 6 7 tRES1

SCLK

Command

SI AB

High-Z
SO

Deep Power Down Mode Standby Mode

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Figure 23. Power-Up Timing

VCC
VCC(max)

Chip Selection is Not Allowed

VCC(min)

tVSL Device is fully

accessible

time

Note: VCC (max.) is 3.6V and VCC (min.) is 3.0V.

Table 9. Power-Up Timing

Symbol Parameter Min. Max. Unit
tVSL(1) VCC(min) to CS# low 300 us
Note: 1. The parameter is characterized only.

INITIAL DELIVERY STATE

The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status
Register contains 00h (all Status Register bits are 0).

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RECOMMENDED OPERATING CONDITIONS

At Device Power-Up

AC timing illustrated in Figure 24 is recommended for the supply voltages and the control signals at device power-
up. If the timing in the figure is ignored, the device may not operate correctly.

Figure 24. AC Timing at Device Power-Up

VCC(min)
VCC
GND tVR tSHSL

CS#
tCHSL tSLCH tCHSH tSHCH

SCLK
tDVCH tCHCL

tCHDX tCLCH

SI MSB IN LSB IN

High Impedance
SO

Symbol Parameter Notes Min. Max. Unit

tVR VCC Rise Time 1 10 500000 us/V
tRH Reset High Time Before Read 5 ms
Notes :
1. Sampled, not 100% tested.
2. For AC spec tSLCH, tDVCH, tCHDX, tCHSH in the figure, please refer to "AC CHARACTERISTICS" table.

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Figure 25. Power-Down Sequence

During power-down, CS# needs to follow the voltage drop on VCC to avoid mis-operation.

VCC

CS#

SCLK

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ERASE AND PROGRAMMING PERFORMANCE

PARAMETER Min. TYP. (1) Max. (2) UNIT
Sector Erase Time 90 300 ms
Block Erase Time 1 2 s
512Kb 1 2 s
Chip Erase Time
1Mb 1 2 s
Page Program Time 180 650 us
Erase/Program Cycle 100,000 cycles
Note:
1. Typical program and erase time assumes the following conditions: 25°C, 3.3V, and checker board pattern.
2. Under worst conditions of 70°C and 2.7V.
3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming com-
mand.
4. Erase/Program cycles comply with JEDEC JESD-47E & A117A standard.

DATA RETENTION
PARAMETER Condition Min. Max. UNIT
Data retention 70˚C 20 years

LATCH-UP CHARACTERISTICS
MIN. MAX.
Input Voltage with respect to GND on all power pins, SI, CS# -1.0V 2 VCCmax
Input Voltage with respect to GND on SO -1.0V VCC + 1.0V
Current -100mA +100mA
Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.

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ORDERING INFORMATION
512Kb
OPERATING STANDBY
CLOCK
PART NO. CURRENT CURRENT TEMPERATURE PACKAGE Remark
(MHz)
MAX. (mA) MAX. (uA)
8-SOP
MX25L5121EMC-20G 45 10 30 0°C~70°C Pb-free
(150mil)
8-TSSOP
MX25L5121EOC-20G 45 10 30 0°C~70°C Pb-free
(173mil)

1Mb
OPERATING STANDBY
CLOCK
PART NO. CURRENT CURRENT TEMPERATURE PACKAGE Remark
(MHz)
MAX. (mA) MAX. (uA)
8-SOP
MX25L1021EMC-20G 45 10 30 0°C~70°C Pb-free
(150mil)

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PART NAME DESCRIPTION

MX 25 L 1021E M C 20 G
OPTION:
G: Pb-free

SPEED:
20: 45MHz

TEMPERATURE RANGE:
C: Commercial (0°C to 70°C)

PACKAGE:
M: 150mil 8-SOP
O: 173mil 8-TSSOP

DENSITY & MODE:

5121E: 512Kb
1021E: 1Mb

TYPE:
L: 3V

DEVICE:
25: Serial Flash

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PACKAGE INFORMATION

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REVISION HISTORY

Revision No. Description Page Date

0.01 1. Corrected 25L5121 ID code P12 APR/07/2010
2. Added VWI into table 7 P22
3. Modified ISB1, ISB2, ICC1, ICC2 & ICC4 P4,22,36
4. Modified tDVCH, tCHDX & tCLQV P23
5. Modified EPN P36,37

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Macronix's products are not designed, manufactured, or intended for use for any high risk applications in which
the failure of a single component could cause death, personal injury, severe physical damage, or other substan-
tial harm to persons or property, such as life-support systems, high temperature automotive, medical, aircraft
and military application. Macronix and its suppliers will not be liable to you and/or any third party for any claims,
injuries or damages that may be incurred due to use of Macronix's products in the prohibited applications.

Copyright© Macronix International Co., Ltd. 2010. All Rights Reserved. Macronix, MXIC, MXIC Logo, MX Logo,
MXSMIO, are trademarks or registered trademarks of Macronix International Co., Ltd.. The names and brands
of other companies are for identification purposes only and may be claimed as the property of the respective
companies.

MACRONIX INTERNATIONAL CO., LTD.

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Headquarters, FAB2 Macronix Asia Limited.
Macronix, International Co., Ltd. NKF Bldg. 5F, 1-2 Higashida-cho,
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Fax: +886-3-5632888 Fax: +81-44-246-9105

Taipei Office Macronix Offices : Korea

Macronix, International Co., Ltd. Macronix Asia Limited.
19F, 4, Min-Chuan E. Road, Sec. 3, Taipei, #906, 9F, Kangnam Bldg., 1321-4, Seocho-Dong, Seocho-Ku,
Taiwan, R.O.C. 135-070, Seoul, Korea
Tel: +886-2-2509-3300
Fax: +886-2-2509-2200 Tel: +82-02-588-6887
Fax: +82-02-588-6828
Macronix Offices : China
Macronix (Hong Kong) Co., Limited. Macronix Offices : Singapore
702-703, 7/F, Building 9, Hong Kong Science Park, Macronix Pte. Ltd.
5 Science Park West Avenue, Sha Tin, 1 Marine Parade Central, #11-03 Parkway Centre,
N.T. Singapore 449408
Tel: +86-852-2607-4289 Tel: +65-6346-5505
Fax: +86-852-2607-4229 Fax: +65-6348-8096

Macronix (Hong Kong) Co., Limited, Macronix Offices : Europe

SuZhou Office Macronix Europe N.V.
No.5, XingHai Rd, SuZhou Industrial Park, Koningin Astridlaan 59, Bus 1 1780
SuZhou China 215021 Wemmel Belgium
Tel: +86-512-62580888 Ext: 3300 Tel: +32-2-456-8020
Fax: +32-2-456-8021
Fax: +86-512-62586799

Macronix (Hong Kong) Co., Limited, Macronix Offices : USA

Shenzhen Office Macronix America, Inc.
Room 1401 & 1404, Block A, TianAN Hi-Tech PLAZA Tower, 680 North McCarthy Blvd. Milpitas, CA 95035,
Che Gong Miao, FutianDistrict, Shenzhen PRC 518040 U.S.A.
Tel: +86-755-83433579 Tel: +1-408-262-8887
Fax: +86-755-83438078 Fax: +1-408-262-8810

http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.

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