GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

GATE SOLVED PAPER - EE

ANALOG & DIGITAL ELECTRONICS

YEAR 2013 ONE MARK

Q. 1 A bulb in a staircase has two switches, one switch being at the ground floor
and the other one at the first floor. The bulb can be turned ON and also can
be turned OFF by any one of the switches irrespective of the state of the other
switch. The logic of switching of the bulb resembles
(A) and AND gate (B) an OR gate
(C) an XOR gate (D) a NAND gate

Q. 2 In a voltage-voltage feedback as shown below, which one of the following statements

is TRUE if the gain k is increased?

(A) The input impedance increases and output impedance decreases

(B) The input impedance increases and output impedance also increases
(C) The input impedance decreases and output impedance also decreases
(D) The input impedance decreases and output impedance increases

Q. 3 In the circuit shown below what is the output voltage Vout

^ if ha silicon transistor
Q and an ideal op-amp are used?

(A) -15 V (B) -0.7 V

(C) +0.7 V (D) +15 V
 YEAR 2013 TWO MARKS

Q. 4 In the circuit shown below the op-amps are ideal. Then,V out in Volts is

(A) 4 (B) 6
(C) 8 (D) 10

Q. 5 In the circuit shown below, Q1 has negligible collector-to-emitter saturation

voltage and the diode drops negligible voltage across it under forward bias. IfVcc
is +5 V, X and Y are digital signals with 0 V as logic 0 and Vcc as logic 1, then
the Boolean expression for Z is

(A) X Y (B) X Y
(C) X Y (D) X Y

Q. 6 The clock frequency applied to the digital circuit shown in the figure below is
1 kHz. If the initial state of the output of the flip-flop is 0, then the frequency of
the output waveform Q in kHz is

(A) 0.25 (B) 0.5

(C) 1 (D) 2
GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

Q. 7 A voltage 1000 sin wt Volts is applied across YZ . Assuming ideal diodes, the
voltage measured across W X in Volts, is

(A) sin wt (B) _sin wt + sin wt i / 2

(C) ^sin wt - sin wt h / 2 (D) 0 for all t

Q. 8 In the circuit shown below, the knee current of the ideal Zener dioide is10 mA
. To maintain 5 V across RL , the minimum value of RL in W and the minimum power
rating of the Zener diode in mW , respectively, are

(A) 125 and 125 (B) 125 and 250

(C) 250 and 125 (D) 250 and 250

YEAR 2012 ONE MARK

Q. 9 In the sum of products function f (X, Y, Z) = /( 2, 3, 4, 5), the prime implicants

are
(A) X Y , X Y (B) X Y , X Y Z , XY Z

(C) X Y Z , X YZ ,XY (D) X Y Z , X YZ , X Y Z ,XY Z

Q. 10 The i -v characteristics of the diode in the circuit given below are

v - 0.7 A, v $ 0.7 V
i = * 500
0A v < 0.7 V

The current in the circuit is

 GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

(A) 10 mA (B) 9.3 mA

(C) 6.67 mA (D) 6.2 mA

Q. 11 The output Y of a 2-bit comparator is logic 1 whenever the 2-bit input A is

greater than the 2-bit input B . The number of combinations for which the output
is logic 1, is
(A) 4 (B) 6
(C) 8 (D) 10

Q. 12 Consider the given circuit

In this circuit, the race around

(A) does not occur
(B) occur when CLK = 0
(C) occur when CLK = 1 and A = B = 1
(D) occur when CLK = 1 and A = B = 0

YEAR 2012 TWO MARKS

Q. 13 The voltage gain A v of the circuit shown below is

(A) A v . 200 (B) A v . 100

(C) A v . 20 (D) A v . 10
Q. 14 The state transition diagram for the logic circuit shown is
GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

Q. 15 The circuit shown is a

1
(A) low pass filter with f3dB = rad /s
( R 1 + R2) C
(B) high pass filter with f3dB = 1 rad /s
R 1C
1
(C) low pass filter with f3dB = rad /s
R 1C
1
(D) high pass filter with f3dB = rad /s
( R 1 + R2) C

YEAR 2011 ONE MARK

Q. 16 The output Y of the logic circuit given below is

(A) 1 (B) 0
(C) X (D) X

Q. 17 A low-pass filter with a cut-off frequency of 30 Hz is cascaded with a high pass

filter with a cut-off frequency of 20 Hz. The resultant system of filters will function
as
(A) an all – pass filter
(B) an all – stop filter
(C) an band stop (band-reject) filter
(D) a band – pass filter
 GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

Q. 18 The CORRECT transfer characteristic is

YEAR 2011 TWO MARKS

Q. 19 The transistor used in the circuit shown below has a b of 30 and ICBO is negligible

If the forward voltage drop of diode is 0.7 V, then the current through collector
will be
(A) 168 mA (B) 108 mA
(C) 20.54 mA (D) 5.36 mA
GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

Q. 20 A two bit counter circuit is shown below

It the state QA QB of the counter at the clock time tn is ‘10’ then the state QA QB
of the counter at t n + 3 (after three clock cycles) will be
(A) 00 (B) 01
(C) 10 (D) 11

Q. 21 A portion of the main program to call a subroutine SUB in an 8085 environment

is given below.
h
LXI D, DISP
LP : CALL SUB
LP + 3
h
It is desired that control be returned to LP + DISP + 3 when the RET instruction
is executed in the subroutine. The set of instructions that precede the RET
instruction in the subroutine are
POP H
DAD D
POP D
INX H
(A) DAD H (B)
INX H
PUSH D
INX H
PUSH H
XTHL
POP H INX D
(C) DAD D (D) INX D
PUSH H INX D
XTHL
Q. 22 A clipper circuit is shown below.

Assuming forward voltage drops of the diodes to be 0.7 V, the input-output

transfer characteristics of the circuit is
 GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

YEAR 2010 ONE MARK

Q. 23 Given that the op-amp is ideal, the output voltage vo is

(A) 4 V
(B) 6 V
(C) 7.5 V
(D) 12.12 V

Q. 24 Assuming that the diodes in the given circuit are ideal, the voltageV0 is

(A) 4 V (B) 5 V
(C) 7.5 V (D) 12.12 V
GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

YEAR 2010 TWO MARKS

Q. 25 The transistor circuit shown uses a silicon transistor with VBE = 0.7, IC . IE and
a dc current gain of 100. The value ofV0 is

(A) 4.65 V (B) 5 V

(C) 6.3 V (D) 7.23 V

Q. 26 The TTL circuit shown in the figure is fed with thewaveform X (also shown).
All gates have equal propagation delay of 10 ns. The output Y of the circuit is

Statement For Linked Answer Questions: 27 and 28

The following Karnaugh map represents a function F .

Q. 27 A minimized form of the function F is

(A) F = X Y + YZ (B) F = X Y + YZ
(C) F = X Y + Y Z (D) F = X Y + Y Z
 GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

Q. 28 Which of the following circuits is a realization of the above functionF ?

Q. 29 When a “CALL Addr” instruction is executed, the CPU carries out the following
sequential operations internally :
Note: (R) means content of register R
((R)) means content of memory location pointed to by R.
PC means Program Counter
SP means Stack Pointer
(A) (SP) incremented (B) ( P C)!Addr
( P C)!Addr ((SP ))!( P C)
((SP ))!( P C) (SP) incremented
(C) ( P C)!Addr (D) ((SP ))!( P C)
(SP) incremented (SP) incremented
((SP ))!( P C) ( P C)!Addr

YEAR 2009 ONE MARK

Q. 30 The following circuit has a source voltage VS as shown in the graph. The current
through the circuit is also shown.
GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

The element connected between a and b could be

Q. 31 The increasing order of speed of data access for the following device is
(I) Cache Memory
(II) CD-ROM
(III) Dynamic RAM
(IV) Processor Registers
(V) Magnetic Tape
(A) (V), (II), (III), (IV), (I) (B) (V), (II), (III), (I), (IV)
(C) (II), (I), (III), (IV), (V) (D) (V), (II), (I), (III), (IV)

Q. 32 The nature of feedback in the op-amp circuit shown is

(A) Current-Current feedback (B) Voltage-Voltage feedback

(C) Current-Voltage feedback (D) Voltage-Current feedback
Q. 33 The complete set of only those Logic Gates designated as Universal Gates is
(A) NOT, OR and AND Gates (B) XNOR, NOR and NAND Gates
(C) NOR and NAND Gates (D) XOR, NOR and NAND Gates

YEAR 2009 TWO MARKS

Q. 34 The following circuit has R = 10 kW, C = 10 mF. The input voltage is a sinusoidal
at 50 Hz with an rms value of 10 V. Under ideal conditions, the current Is from
the source is
 GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

% %
(A) 10p mA leading by 90 (B) 20p mA leading by 90
% %
(C) 10p mA leading by 90 (D) 10p mA lagging by 90
Q. 35 Transformer and emitter follower can both be used for impedance matching at
the output of an audio amplifier. The basic relationship between the input power
Pin and output power Pout in both the cases is
(A) Pin = Pout for both transformer and emitter follower
(B) Pin > Pout for both transformer and emitter follower
(C) Pin < Pout for transformer and Pin = Pout for emitter follower
(D) Pin = Pout for transformer and Pin < Pout for emitter follower

Q. 36 In an 8085 microprocessor, the contents of the Accumulator, after the following

instructions are executed will become
XRA A
MVI B, F0 H
SUB B
(A) 01 H (B) 0F H
(C) F0 H (D) 10 H

Q. 37 An ideal op-amp circuit and its input wave form as shown in the figures. The
output waveform of this circuit will be
GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

YEAR 2008 ONE MARK

Q. 38 The equivalent circuits of a diode, during forward biased and reverse biased
conditions, are shown in the figure.

(I)

(II)

If such a diode is used in clipper circuit of figure given above, the output voltage
V0 of the circuit will be

YEAR 2008 TWO MARKS

Q. 39 Two perfectly matched silicon transistor are connected as shown in the figure
assuming the b of the transistors to be very high and the forward voltage drop
in diodes to be 0.7 V, the value of current I is
 GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

(A) 0 mA (B) 3.6 mA

(C) 4.3 mA (D) 5.7 mA

Q. 40 In the voltage doubler circuit shown in the figure, the switch S‘ ’ is closed a t t = 0
. Assuming diodes D1 and D2 to be ideal, load resistance to be infinite and initial
capacitor voltages to be zero. The steady state voltage across capacitor C1 and
C2 will be

(A) Vc1 = 10 V, Vc2 = 5 V

(B) Vc1 = 10 V, Vc2 =- 5 V
(C) Vc1 = 5 V, Vc2 = 10 V
(D) Vc1 = 5 V, Vc2 =- 10 V

Q. 41 The block diagrams of two of half wave rectifiers are shown in the figure. The
transfer characteristics of the rectifiers are also shown within the block.

It is desired to make full wave rectifier using above two half-wave rectifiers. The
resultants circuit will be
GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

Q. 42 A waveform generator circuit using OPAMPs is shown in the figure. It produces

a triangular wave at point ‘P’ with a peak to peak voltage of 5 V forVi = 0 V.

If the voltage Vi is made +2.5 V, the voltage waveform at point ‘P’ will become

Statement for Linked Answer Questions 43 and 44

A general filter circuit is shown in the figure :
 GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

Q. 43 If R1 = R2 = R A and R3 = R4 = R B , the circuit acts as a

(A) all pass filter
(B) band pass filter
(C) high pass filter
(D) low pass filter

Q. 44 The output of the this filter is given to the circuit in figure :

The gain v / s frequency characteristic of the output (vo) will be

Q. 45 A 3-line to 8-line decoder, with active low outputs, is used to implement a 3-

variable Boolean function as shown in the figure

The simplified form of Boolean function F ( A, B ,C ) implemented in ‘Product of

Sum’ form will be
(A) ( X + Z) ( X + Y + Z ) ( Y +Z )
(B) ( X + Z ) ( X + Y + Z) ( Y + Z )
(C) ( X + Y + Z) ( X + Y + Z) ( X + Y + Z) ( X + Y +Z )
(D) ( X + Y + Z) ( X + Y + Z ) ( X + Y + Z) (X + Y +Z )
GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

Q. 46 The content of some of the memory location in an 8085 accumulator based system
are given below
Address Content
g g
26FE 00
26FF 01
2700 02
2701 03
2702 04
g g
The content of stack (SP), program counter ( PC) and (H,L) are 2700 H, 2100 H and
0000 H respectively. When the following sequence of instruction are executed. 2100
H: DAD SP
2101 H: PCHL
the content of (SP) and ( PC) at the end of execution will be
(A) PC = 2102 H, SP = 2700 H (B) PC = 2700 H,SP = 2700 H
(C) PC = 2800 H,SP = 26FE H (D) PC = 2A02 H,SP = 2702 H

YEAR 2007 ONE MARK

Q. 47 The common emitter forward current gain of the transistor shown is bF = 100

The transistor is operating in

(A) Saturation region (B) Cutoff region
(C) Reverse active region (D) Forward active region

Q. 48 The three-terminal linear voltage regulator is connected to a 10 W load resistor as

shown in the figure. If Vin is 10 V, what is the power dissipated in the transistor ?

(A) 0.6 W (B) 2.4 W

(C) 4.2 W (D) 5.4 W
 GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

Q. 49 The circuit shown in the figure is

(A) a voltage source with voltage rV

R1 < R2
r < R2
(B) a voltage source with voltage V
R1
(C) a current source with current r < R2 V
c R + Rm r
1 2

(D) a current source with current c R 2 V

R1 + R 2m r
Q. 50 A, B, C and D are input, and Y is the output bit in the XOR gate circuit of the
figure below. Which of the following statements about the sum S of A, B, C, D
and Y is correct ?

(A) S is always with zero or odd

(B) S is always either zero or even
(C) S = 1 only if the sum of A, B, C and D is even
(D) S = 1 only if the sum of A, B, C and D is odd

YEAR 2007 TWO MARKS

Q. 51 The input signal Vin shown in the figure is a 1 kHz square wave voltage that
alternates between +7 V and -7 V with a 50% duty cycle. Both transistor
have the same current gain which is large. The circuit delivers power to the load
resistor RL . What is the efficiency of this circuit for the given input ? choose the closest
answer.

(A) 46% (B) 55%

(C) 63% (D) 92%
GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

Q. 52 The switch S in the circuit of the figure is initially closed, it is opened at timet = 0
. You may neglect the zener diode forward voltage drops. What is the behavior
of vout for t > 0 ?

(A) It makes a transition from - 5 V to + 5 V at t = 12.98 ms

(B) It makes a transition from - 5 V to + 5 V at t = 2.57 ms
(C) It makes a transition from + 5 V to - 5 V at t = 12.98 ms
(D) It makes a transition from + 5 V to - 5 V at t = 2.57 ms

Q. 53 IC 555 in the adjacent figure is configured as an astable multi-vibrator. It is

enabled to to oscillate at t = 0 by applying a high input to pin 4. The pin
description is : 1 and 8-supply; 2-trigger; 4-reset; 6-threshold 7-discharge. The
waveform appearing across the capacitor starting from t = 0, as observed on a storage
CRO is
 GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

Q. 54 The Octal equivalent of HEX and number AB.CD is

(A) 253.314 (B) 253.632
(C) 526.314 (D) 526.632

YEAR 2006 ONE MARK

Q. 55 What are the states of the three ideal diodes of the circuit shown in figure ?

(A) D1 ON, D2 OFF , D3 OFF (B) D1 OFF, D2 ON , D3 OFF

(C) D1 ON, D2 OFF , D3 ON (D) D1 OFF, D2 ON , D3ON

Q. 56 For a given sinusoidal input voltage, the voltage waveform at point P of the
clamper circuit shown in figure will be

YEAR 2006 TWO MARKS

Q. 57 Assuming the diodes D1 and D2 of the circuit shown in figure to be ideal ones, the
transfer characteristics of the circuit will be
GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

Q. 58 A relaxation oscillator is made using OPAMP as shown in figure. The supply

voltages of the OPAMP are !12 V . The voltage waveform a t point P will be

Q. 59 Consider the circuit shown in figure. If the b of the transistor is 30 and I CBO is 20
mA and the input voltage is +5 V, the transistor would be operating in
 GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

(A) saturation region (B) active region

(C) breakdown region (D) cut-off region

Q. 60 A TTL NOT gate circuit is shown in figure. Assuming VBE = 0.7 V of both the
transistors, if Vi = 3.0 V, then the states of the two transistors will be

(A) Q1 ON and Q2 OFF (B) Q1 reverse ON and Q2 OFF

(C) Q1 reverse ON and Q2 ON(D) Q1 OFF and Q2 reverse ON

Q. 61 A student has made a 3-bit binary down counter and connected to the R-2R
ladder type DAC, [Gain = (- 1 kW/ 2 R)] as shown in figure to genera te a staircase
waveform. The output achieved is different as shown in figure. What could be the
possible cause of this error ?

(A) The resistance values are incorrect option.

(B) The counter is not working properly
(C) The connection from the counter of DAC is not proper
(D) The R and 2R resistance are interchanged
GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

Q. 62 A 4 # 1 MUX is used to implement a 3-input Boolean function as shown in figure.

The Boolean function F ( A, B ,C ) implemented is

(A) F ( A, B,C ) = S( 1, 2, 4, 6) (B) F ( A, B,C ) = S( 1, 2, 6)

(C) F ( A, B,C ) = S( 2, 4, 5, 6) (D) F ( A, B,C ) = S( 1, 5, 6)

Q. 63 A software delay subroutine is written as given below :

DELAY : MVI H, 255D
MVI L, 255D
LOOP : DCR L
JNZ LOOP
DCR H
JNZ LOOP
How many times DCR L instruction will be executed ?
(A) 255 (B) 510
(C) 65025 (D) 65279

Q. 64 In an 8085 A microprocessor based system, it is desired to increment the contents

of memory location whose address is available in (D,E) register pair and store the
result in same location. The sequence of instruction is
(A) XCHG (B) XCHG
INR M INX H
(C) INX D (D) INR M
XCHG XCHG

YEAR 2005 ONE MARK

Q. 65 Assume that D1 and D2 in figure are ideal diodes. The value of current is

(A) 0 mA (B) 0.5 mA

(C) 1 mA (D) 2 mA

Q. 66 The 8085 assembly language instruction that stores the content of H and L
register into the memory locations 2050H and 2051H , respectively is
(A) SPHL 2050H (B) SPHL 2051H
(C) SHLD 2050H (D) STAX 2050H
 GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

Q. 67 Assume that the N-channel MOSFET shown in the figure is ideal, and that its
threshold voltage is +1.0 V the voltage Vab between nodes a and b is

(A) 5 V (B) 2 V
(C) 1 V (D) 0 V

Q. 68 The digital circuit shown in the figure works as

(A) JK flip-flop
(B) Clocked RS flip-flop
(C) T flip-flop
(D) Ring counter

YEAR 2005 TWO MARKS

Q. 69 The common emitter amplifier shown in the figure is biased using a 1 mA ideal
current source. The approximate base current value is

(A) 0 mA (B) 10 mA
(C) 100 mA (D) 1000 mA

Q. 70 Consider the inverting amplifier, using an ideal operational amplifier shown in the
figure. The designer wishes to realize the input resistance seen by the small-signal
source to be as large as possible, while keeping the voltage gain between-10 and
-25. The upper limit on R F is 1 MW. The value of R1 should be
GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

(A) Infinity (B) 1 MW

(C) 100 kW (D) 40 kW

Q. 71 The typical frequency response of a two-stage direct coupled voltage amplifier is

as shown in figure

Q. 72 In the given figure, if the input is a sinusoidal signal, the output will appear as
shown

Q. 73 Select the circuit which will produce the given output Q for the input signals X1
and X2 given in the figure
 GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

Q. 74 If X1 and X2 are the inputs to the circuit shown in the figure, the outputQ is

(A) X1 + X2 (B) X1 : X2
(C) X1 : X2 (D) X1 : X2

Common Data For Q. 75 and 76

Assume that the threshold voltage of the N-channel MOSFET shown in figure is
+ 0.75 V. The output characteristics of the MOSFET are also shown

Q. 75 The transconductance of the MOSFET is

(A) 0.75 ms (B) 1 ms
(C) 2 ms (D) 10 ms
GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

Q. 76 The voltage gain of the amplifier is

(A) +5 (B) -7.5
(C) +10 (D) -10

Q. 77 In the figure, as long as X1 = 1 and X2 = 1, the output Q remains

(A) at 1
(B) at 0
(C) at its initial value
(D) unstable

YEAR 2004 ONE MARK

Q. 78 The current through the Zener diode in figure is

(A) 33 mA
(B) 3.3 mA
(C) 2 mA
(D) 0 mA

Q. 79 Two perfectly matched silicon transistor are connected as shown in figure. The
value of the current I is

(A) 0 mA
(B) 2.3 mA
(C) 4.3 mA
(D) 7.3 mA
 GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

Q. 80 The feedback used in the circuit shown in figure can be classified as

(A) shunt-series feedback (B) shunt-shunt feedback

(C) series-shunt feedback (D) series-series feedback

Q. 81 The digital circuit using two inverters shown in figure will act as

(A) a bistable multi-vibrator (B) an astable multi-vibrator

(C) a monostable multi-vibrator (D) an oscillator

Q. 82 The voltage comparator shown in figure can be used in the analog-to-digital

conversion as

(A) a 1-bit quantizer

(B) a 2-bit quantizer
(C) a 4-bit quantizer
(D) a 8-bit quantizer

YEAR 2004 TWO MARKS

Q. 83 Assuming that the diodes are ideal in figure, the current in diode D1 is

(A) 9 mA (B) 5 mA
(C) 0 mA (D) - 3 mA
GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

Q. 84 The trans-conductance g m of the transistor shown in figure is 10 mS. The value

of the input resistance R in is

(A) 10.0 kW
(B) 8.3 kW
(C) 5.0 kW
(D) 2.5 kW

Q. 85 The value of R for which the PMOS transistor in figure will be biased in linear
region is

(A) 220 W
(B) 470 W
(C) 680 W
(D) 1200 W

Q. 86 In the active filter circuit shown in figure, if Q = 1, a pair of poles will be realized
with w0 equal to

(A) 1000 rad / s (B) 100 rad / s

(C) 10 rad / s (D) 1 rad / s
 GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

Q. 87 The input resistance Rin = vx / ix of the circuit in figure is

(A) + 100 kW (B) -100 kW

(C) + 1 MW (D) -1 MW
Q. 88 The simplified form of the Boolean expression Y = ( A $ BC +D ) (A $D +B $C )
can be written as

(A) A $ D + B $ C $ D (B) AD + B $ C $ D
(C) ( A + D) (B $ C + D ) (D) A $ D + BC $ D
Q. 89 If the following program is executed in a microprocessor, the number of instruction
cycle it will take from START to HALT is
START MVI A, 14H ; Move 14 H to register A
SHIFT RLC ; Rotate left without carry
JNZ SHIFT ; Jump on non-zero to SHIFT
HALT
(A) 4 (B) 8
(C) 13 (D) 16

Q. 90 A digit circuit which compares two numbers A 3 A 2A 1A 0 and B 3 B 2B 1B 0 is shown

in figure. To get output Y = 0, choose one pair of correct input numbers.

(A) 1010, 1010 (B) 0101, 0101

(C) 0010, 0010 (D) 1010, 1011

Q. 91 The digital circuit shown in figure generates a modified clock pulse at the output.
Choose the correct output waveform from the options given below.
GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

Q. 92 In the Schmitt trigger circuit shown in figure, if VCE (sat) = 0.1 V, the output logic
low level ( VOL) is

(A) 1.25 V (B) 1.35 V

(C) 2.50 V (D) 5.00 V

YEAR 2003 ONE MARK

Q. 93 The variation of drain current with gate-to-source voltage (ID - VGS characteristic)
of a MOSFET is shown in figure. The MOSFET is

(A) an n-channel depletion mode device

(B) an n-channel enhancement mode device
(C) an p-channel depletion mode device
 GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

(D) an p-channel enhancement mode device

Q. 94 In the circuit of figure, assume that the transistor has hfe = 99 and VBE = 0.7 V.
The value of collector current IC of the transistor is approximately

(A) [3.3 / 3.3] mA (B) [3.3 / (3.3 + 3.3)] mA

(C) [3.3 / .33] mA (D) [3.3(33 + 3.3)] mA

Q. 95 For the circuit of figure with an ideal operational amplifier, the maximum phase
shift of the output vout with reference to the input vin is

(A) 0c (B) -90c

(C) +90c (D) !180c
Q. 96 Figure shows a 4 to 1 MUX to be used to implement the sum S of a 1-bit full
adder with input bits P and Q and the carry input Cin . Which of the following
combinations of inputs to I0, I1, I2 and I3 of the MUX will realize the sum S ?

(A) I0 = I1 = C in;I 2 = I 3 = C in (B) I0 = I1 = C in ;I 2 = I 3 = C in

(C) I0 = I3 = Cin;I1 = I 2 = C in (D) I0 = I3 = C in;I 1 = I 2 = C in

Q. 97 When a program is being executed in an 8085 microprocessor, its Program

Counter contains
(A) the number of instructions in the current program that have already been
executed
(B) the total number of instructions in the program being executed.
(C) the memory address of the instruction that is being currently executed
(D) the memory address of the instruction that is to be executed next
GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

YEAR 2003 TWO MARKS

Q. 98 For the n-channel enhancement MOSFET shown in figure, the threshold voltage
Vth = 2 V. The drain current ID of the MOSFET is 4 mA when the drain resistance
R D is 1 kW.If the value of R D is increased to 4 kW, drain current ID will become

(A) 2.8 mA (B) 2.0 mA

(C) 1.4 mA (D) 1.0 mA

Q. 99 Assuming the operational amplifier to be ideal, the gain vout / vin for the circuit
shown in figure is

(A) -1 (B) -20

(C) -100 (D) -120

Q. 100 A voltage signal 10 sin wt is applied to the circuit with ideal diodes, as shown in
figure, The maximum, and minimum values of the output waveform Vout of the
circuit are respectively

(A) + 10 V and -10 V (B) + 4 V and -4 V

(C) + 7 V and -4 V (D) + 4 V and -7 V

Q. 101 The circuit of figure shows a 555 Timer IC connected as an astable multi-vibrator.
The value of the capacitor C is 10 nF. The values of the resistors R A and R B for a
frequency of 10 kHz and a duty cycle of 0.75 for the output voltagewaveform are
 GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

(A) R A = 3.62 kW, R B = 3.62 kW (B) R A = 3.62 kW, R B = 7.25 kW

(C) R A = 7.25 kW, R B = 3.62 kW (D) RA = 7.25 kW, RB = 7.25 kW

Q. 102 The boolean expression X Y Z +XY Z +X YZ +X Y Z +XYZ can be simplified

to
(A) XZ + XZ + YZ (B) X Y + Y Z +YZ
(C) X Y + YZ + XZ (D) X Y + YZ + XZ

Q. 103 The shift register shown in figure is initially loaded with the bit pattern 1010.
Subsequently the shift register is clocked, and with each clock pulse the pattern
gets shifted by one bit position to the right. With each shift, the bit at the serial
input is pushed to the left most position (msb). After how many clock pulses will
the content of the shift register become 1010 again ?

(A) 3 (B) 7
(C) 11 (D) 15

Q. 104 An X-Y flip-flop, whose Characteristic Table is given below is to be implemented

using a J-K flip flop

(A) J = X, K = Y (B) J = X, K = Y
(C) J = Y , K = X (D) J = Y , K = X

Q. 105 A memory system has a total of 8 memory chips each with 12 address lines and
4 data lines, The total size of the memory system is
(A) 16 kbytes (B) 32 kbytes
(C) 48 kbytes (D) 64 kbytes
GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

Q. 106 The following program is written for an 8085 microprocessor to add two bytes
located at memory addresses 1FFE and 1FFF
LXI H, 1FFE
MOV B, M
INR L
MOV A, M
ADD B
INR L
MOV M, A
XOR A
On completion of the execution of the program, the result of addition is found
(A) in the register A
(B) at the memory address 1000
(C) at the memory address 1F00
(D) at the memory address 2000

************
 GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

SOLUTION

Sol. 1 Option (C) is correct.

Let A denotes the position of switch at ground floor and B denotes the position
of switch at upper floor. The switch can be either in up position or down position.
Following are the truth table given for different combinations of A and B
A B Y(Bulb)
up(1) up(1) OFF(0)
Down(0) Down(0) OFF(0)
up(1) Down(0) ON(1)
Down(0) up(1) ON(1)
When the switches A and B are both up or both down, output will be zero (i.e.
Bulb will be OFF). Any of the switch changes its position leads to the ON state
of bulb. Hence, from the truth table, we get
Y = A 5B
i.e., the XOR gate
Sol. 2 Option (A) is correct.
The i / p voltage of the system is given as
Vin = V1 + Vf = V1 + k Vout
= V1 + k A 0 V 1 ^Vout = A 0 V1h
= V1 ^1 + k A 0h
Therefore, if k is increased then input voltage is also increased so, the input
impedance increases. Now, we have
Vout = A 0V1
= A0 Vin = A 0 V in
^1 + k A 0h ^1 + k A 0h
Since, Vin is independent of k when seen from output mode, the output voltage
decreases with increase in k that leads to the decrease of output impedance.
Thus, input impedance increases and output impedance decreases.
Sol. 3 Option (B) is correct.
For the given ideal op-amp, negative terminal will be also ground (at zero voltage)
and so, the collector terminal of the BJT will be at zero voltage.
i.e., VC = 0 volt
The current in 1 kW resistor is given by
I = 5 - 0 = 5 mA
1 kW
This current will flow completely through the BJT since, no current will flow
into the ideal op-amp (I / P resistance of ideal op-amp is infinity). So, for BJT
we have
VC = 0
GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

VB = 0
IC = 5 mA
i.e.,the base collector junction is reverse biased (zero voltage) therefore, the
collector current ( IC ) can have a value only if base-emitter is forward biased.
Hence,
VBE = 0.7 volts
& VB - VE = 0.7
& 0 - Vout = 0.7 & Vout =- 0.7 volt
Sol. 4 Option (C) is correct.

For the given ideal op-Amps we can assume

V - = V + = V (ideal)
2 2 2
V + = V - = V (ideal)
1 1 1

So, by voltage division

V1 = Vout # 1
2
Vout = 2V1
and, as the I / P current in Op-amp is always zero therefore, there will be no voltage
drop across 1 KW in II op-amp
i.e., V2 = 1 V
V - ^-2h
Therefore, V1 - V2 = 2
1 1
or, V1 - 1 = 1 + 2
or, V1 = 4
So,
Vout = 2V1 = 8 volt
Sol. 5 Option (B) is correct.
For the given circuit, we can make the truth table as below
X Y Z
0 0 0
0 1 1
1 0 0
1 1 0
 GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

Logic 0 means voltage is v = 0 volt and logic 1 means voltage is 5 volt

For x = 0, y = 0, Transistor is at cut off mode and diode is forward biased. Since, there
is no drop across forward biased diode.
So, Z = Y =0
For x = 0, y = 1, Again Transistor is in cutoff mode, and diode is forward biased. with
no current flowing through resistor.
So, Z = Y =1
For x = 1, y = 0, Transistor is in saturation mode and so, z directly connected to
ground irrespective of any value of Y .
i.e., Z = 0 (ground)
Similarly for X = Y = 1
Z = 0 (ground)
Hence, from the obtained truth table, we get
Z=XY
Sol. 6 Option (B) is correct.
From the given logic diagram, we obtain
X = ^Q 5 Q h $ ^Q 5 Q h = 0 = 1
So, the input is always ‘1’ at T , since, clock is - ve edge trigged therefore, at the
negative edge Q changes its state as shown in waveform below

Hence, as obtained from the waveform, time period ofQ is double to that of
CLK I / p and so, frequency is 1 of
2 clock frequency

Thus, fQ = FCLK = 1 = 0.5 kHz

2 2
Sol. 7 Option (D) is correct.
Given, the input voltage
VYZ = 100 sin wt
GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

For + ve half cycle

VYZ > 0
i.e., VY is a higher voltage than VZ
So, the diode will be in cutoff region. Therefore, there will no voltage difference
between X and W node.
i.e., VWX = 0
Now, for - ve half cycle all the four diodes will active and so, X and W
terminal is short circuited
i.e., VWX = 0
Hence, VWX = 0 for all t
Sol. 8 Option (B) is correct.

From the circuit, we have

Is = IZ + IL
or, IZ = Is - IL (1)
Since, voltage across zener diode is 5 V so, current through 100 W resistor is
obtained as
Is = 10 - 5 = 0.05 A
100
Therefore, the load current is given by
IL = 5
RL
Since, for proper operation, we must have
IZ $ Iknes
So, from Eq. (1), we write
0.05 A - 5 $ 10 mA
RL
50 mA - 5 $ 10 mA
RL
40 mA $ 5
RL
40 # 10-3 $ 5
RL
1 # RL
40 # 10-3 5
5
-3 # R L
40 # 10
 GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

or, 125 W # R L
Therefore, minimum value of RL = 125 W
Now, we know that power rating of Zener diode is given by
PR = VZ IZ^maxh
IZ^maxh is maximum current through zener diode in reverse bias. Maximum
currrent through zener diode flows when load current is zero. i.e.,
IZ^maxh = Is = 10 - 5 = 0.05
100
Therefore, PR = 5 # 0.05 W = 250 mW
Sol. 9 Option (A) is correct.
Prime implicants are the terms that we get by solving K-map

F=XY+XY
1pr44 2 44 3
im e i mplica nt s
Sol. 10 Option (D) is correct.
Let v > 0.7 V and diode is forward biased. Applying Kirchoff’s voltage law
10 - i # 1k - v = 0

10 - :v - 0.7 D (1000) - v = 0
500
10 - (v - 0.7) # 2 - v = 0
v = 11.4 = 3.8 V > 0. 7 (Assumption is true)
3
So, i = v - 0.7 = 3.8 - 0.7 = 6.2 mA
500 500
Sol. 11 Option (B) is correct.

Y = 1, when A > B

A = a1a0, B = b1b 0

a1 a0 b1 b0 Y
0 1 0 0 1
1 0 0 0 1
1 0 0 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1

Total combination = 6
Sol. 12 Option (A) is correct.
The given circuit is
GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

Condition for the race-around

It occurs when the output of the circuit ( Y1, Y2) oscillates between ‘0’ and ‘1’
checking it from the options.
1. Option (A): When CLK = 0
Output of the NAND gate will be A 1 = B1 = 0 = 1. Due to these input to the next
NAND gate, Y2 = Y1 : 1 = Y 1 and Y1 = Y2 : 1 = Y 2 .
If Y1 = 0, Y2 = Y1 = 1 and it will remain the same and doesn’t oscillate.
If Y2 = 0, Y1 = Y2 = 1 and it will also remain the same for the clock period. So,
it won’t oscillate for CLK = 0.
So, here race around doesn’t occur for the condition CLK = 0.
2. Option (C): When CLK = 1, A = B = 1
A1 = B1 = 0 and so Y1 = Y2 = 1
And it will remain same for the clock period. So race around doesn’t occur for
the condition.
3. Option (D): When CLK = 1, A = B = 0
So, A 1 = B1 = 1
And again as described for Option (B) race around doesn’t occur for the
condition.
So, Option (A) will be correct.
Sol. 13 Option (D) is correct.
DC Analysis :

Using KVL in input loop,

VC - 100IB - 0.7 = 0
VC = 100IB + 0.7 ...(i)
IC - IE = 13.7 - VC = (b + 1) IB
12k
13.7 - VC = 100I
B ...(ii)
12 # 103
Solving equation (i) and (ii),
IB = 0.01 mA
 GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

Small Signal Analysis :

Transforming given input voltage source into equivalent current source.

This is a shunt-shunt feedback amplifier.

Given parameters,
rp = VT = 25 mV = 2.5 kW
IB 0.01 mA
b 100
gm = = = 0.04 s
rp 2.5 # 1000
Writing KCL at output node
v0 + g v + v0 - v p = 0
m p
RC RF
v0 : 1 + 1 D + vp :gm - 1 D = 0
R R R
Substituting RC = C12 kW, F RF = 100 kW,F gm = 0.04 s

v 0 (9.33 # 10-5) + v p (0.04) = 0

v0 =- 428.72Vp ...(i)
Writing KCL at input node
v i = v p + v p + v p - vo
Rs R s rp RF
= vp : 1 + 1 + 1 D - v0
R r R R
= v p (5.1 # 10- ) - v 0
s p F F
4
RF
Substituting Vp from equation (i)
v i = -5.1 # 10-4 v - v0
0
Rs 428.72 RF
vi =- 1.16 # 10-6 v 0 - 1 # 10-5 v0 Rs = 10 kW
3
10 # 10
vi =- 1.116 # 10-5
3
10 # 10
1
Av = v0 = - 8.96
vi 10 # 10 # 1.116 # 10-5
3

Sol. 14 Option (D) is correct.

Let Qn +1 is next state and Qn is the present state. From the given below figure.
D = Y = AX 0 + AX 1
Qn + 1 = D = AX 0 + AX 1
X 0 = Q, X 1 = Q
Qn +1 = A Qn + AQn
If A = 0, Qn + 1 = Qn (toggle of previous state)
If A = 1, Qn + 1 = Qn
So state diagram is
GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

Sol. 15 Option (B) is correct.

First we obtain the transfer function.

0 - Vi (jw) 0 - Vo (jw)
+ =0
jwC + R1
1
R2
Vo (jw) - Vi (jw)
= 1
R2 jwC + R1

Vi (jw) R 2
Vo (jw) =-
R1 - jwC
j1

At w " 0 (Low frequencies), 1 " 3, so V = 0

o
wC
At w " 3 (higher frequencies), 1 " 0, so Vo (jw) =- R 2 Vi (jw)
wC R1
The filter passes high frequencies so it is a high pass filter.
H (jw) = Vo = - R2
Vi R1 - j 1
wC
- R2 R2
H (3) = R 1 = R 1
At 3 dB frequency, gain will be 2 times of maximum gain H6 (3) @
H^jw0h = 1 H (3)
2
So, R2 = b R2 l
1
R 12 + w021C 2 2 R1
2R 2
=R2+ 1 & R2 = 1
1 1 1
w02 C 2 w 2C 2
w
0 = 1
R1 C

Sol. 16 Option (A) is correct.

Y = X 5 X = X X + XX
= XX + X X = X + X = 1
 GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

Sol. 17 Option (D) is correct.

So, it will act as a Band pass filter.

Sol. 18 Option (D) is correct.

The first half of the circuit is a differential amplifier (negative feedback)

Va =- ( Vi)
Second op-amp has a positive feedback, so it acts as an schmitt trigger.
Since
Va =- Vi this is a non-inverting schmitt trigger.
Threshold value
VTH = 12 = 6 V
2
VTL =- 6 V
GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

Sol. 19 Option (D) is correct.

Zener Diode is used as stabilizer.
The circuit is assumed to be as

We can see that both BE and BC Junction are forwarded biased. So the BJT is
operating in saturation.
12 - 0.2 = 5.36 mA
Collector current IC =
2.2k
Y bIB
Note:- In sa turation mode IC -
Sol. 20 Option (C) is correct.
The characteristics equation of the JK flip-flop is
Q n + 1 = JQ n + KQ n Qn +1 is the next state
From figure it is clear that
J = QB ; K = Q B
The output of JK flip flop
QA (n + 1) = QB QA + QB QA = QB (QA + QA) = QB
Output of T flip-flop
QB (n + 1) = Q A

Clock pulse QA QB QA (n + 1) QB (n + 1)
Initially(tn ) 1 0 1 0
tn + 1 1 0 1 0
tn + 2 1 0 1 0
tn + 3 1 0 1 0
Sol. 21 Option (C) is correct.
LXI D, DISP
LP : CALL SUB
LP + 3
When CALL SUB is executed LP + 3 value is pushed(inserted) in the stack.
POP H & HL = LP + 3
DAD D & HL = HL + DE
= LP + 3 + DE
PUSH H & The last two value of the stack will be HL value i.e,LP + DISP + 3
Sol. 22 Option (C) is correct.
We can obtain three operating regions depending on whether the Zener and PN
 GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

diodes are forward biased or reversed biased.

1. vi #- 0.7 V, zener diode becomes forward biased and diode D will be off so
the equivalent circuit looks like

The output vo =- 0.7 V

2. When -0.7 1 v i # 5.7, both zener and diode D will be off. The circuit is

Output follows input i.e vo = vi

Note that zener goes in reverse breakdown(i.e acts as a constant battery) only
when difference between its p-n junction voltages exceeds 10 V.
3. When vi > 5.7 V, the diode D will be forward biased and zener remains off,
the equivalent circuit is

vo = 5 + 0.7 = 5.7 V
Sol. 23 Option (B) is correct.
Since the op-amp is ideal
v + = v - =+ 2 volt
By writing node equation
v - - 0 + v - - vo = 0
R 2R
2 + (2 - vo) = 0
R 2R
4 + 2 - vo = 0
vo = 6 volt
Sol. 24 Option (B) is correct.
Given circuit is,
GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

We can observe that diode D2 is always off, whether D1,is on or off. So equivalent circuit
is.

V0 = 10
10 + 10 # 10
= 5 volt

D1 is ON in this condition and

Sol. 25 Option (A) is correct.

By writing KVL equation for input loop (Base emitter loop)
10 - (10 kW) I B - VBE - V 0 = 0 ...(1)
Emitter current IE = V0
100
IC - I E = bI B
So, V0 = 100I
B
100
IB = V0
10 # 103
Put IB into equation (1)
10 - (10 # 103) V0 - 0.7 - V0 = 0
10 # 103
9.3 - 2V0 = 0
& V0 = 9.3 = 4.65 A
2

Sol. 26 Option (A) is correct.

The circuit is

Output Y is written as
Y =X5 B
Since each gate has a propagation delay of 10 ns.
 GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

Sol. 27 Option (B) is correct.

Function F can be minimized by grouping of all 1’s in K-map as following.

F = X Y + YZ
Sol. 28 Option (D) is correct.
Since F = X Y + YZ
In option (D)

Sol. 29 Option (D) is correct.

CALL, Address performs two operations
(1) PUSH PC & Save the contents of PC ( Program Counter) into
stack.
SP = SP - 2 (decrement)
((SP)) ! ( PC)
(2) Addr stored in PC.
( PC) ! Addr

Sol. 30 Option (A) is correct.

Figure shows current characteristic of diode during switching.
GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

Sol. 31 Option (B) is correct.

The increasing order of speed is as following
Magnetic tape> CD-ROM> Dynamic RAM> Cache Memory> Processor register
Sol. 32 Option (B) is correct.
Equivalent circuit of given amplifier

Feedback samples output voltage and adds a negative feedback voltage (vfb) to input.
So, it is a voltage-voltage feedback.
Sol. 33 Option () is correct.
NOR and NAND gates considered as universal gates.
Sol. 34 Option (A) is correct.
Let voltages at positive and negative terminals of op-amp areV+ and V- respectively, then
V+ = V- = Vs (ideal op-amp)
In the circuit we have,
V- - 0 + V- - V0 (s) = 0
1 R
`Cs j
( RCs) V- + V- - V 0(s ) = 0
(1 + RCs) Vs = V0 (s)
V - V0
Similarly current Is is, Is = s
R
Is = RCs Vs
R
Is = jwCVs
Is = wCVs + + 90
%

Is = 2pf # 10 # 10-6 # 10
Is = 2 # p # 50 # 10 # 10-6 # 10
Is = 10p mA, leading by 90
%

Sol. 35 Option (D) is correct.

Input and output power of a transformer is same
Pin = Pout
for emitter follower, voltage gain (A v ) = 1
current gain ( A i ) > 1
Power (Pout ) = Av AiPin
Since emitter follower has a high current gain so Pout > Pin
 GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

Sol. 36 Option (D) is correct.

For the given instruction set,
XRA A & XOR A with A & A = 0
MVI B , F0 H& B = F0 H
SUB B & A = A - B
A = 00000000
B = 1111 0 0 0 0
2’s complement of (- B) = 0 0 0 1 0 0 0 0
A + (- B) = A - B = 0 0 0 1 0 0 0 0 = 10 H
Sol. 37 Option (D) is correct.
This is a schmitt trigger circuit, output can takes two states only.
VOH =+ 6 volt
VOL =- 3 volt
Threshold voltages at non-inverting terminals of op-amp is given as
VTH - 6 + VTH - 0 = 0
2 1
3 VTH - 6 = 0
VTH = 2 V (Upper threshold)
VT L - (- 3) VT L
Similarly + =0
2 1
3 VTL + 3 = 0
VTL =- 1 V (Lower threshold)
For Vin < 2 Volt, V0 =+ 6 Volt
Vin > 2 Volt, V0 =- 3 Volt
Vin < - 1 Volt V0 =+ 6 Volt
Vin > - 1 Volt V0 =- 3 Volt
Output waveform

Sol. 38 Option (A) is correct.

Assume the diode is in reverse bias so equivalent circuit is
GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

Output voltage V0 = 10 sin wt # 10 = 5 sin wt

10 + 10
Due to resistor divider, voltage across diode VD < 0 (always). So it in reverse bias for
given input.
Output, V0 = 5 sin wt
Sol. 39 Option (C) is correct.

This is a current mirror circuit. Since b is high so IC1 = IC2, IB1 = IB2
VB = (- 5 + 0.7) =- 4.3 volt
Diode D1 is forward biased.
0 - (- 4.3)
So, current I is, I = IC2 = IC1 = = 4.3 mA
1
Sol. 40 Option (D) is correct.
In positive half cycle of input, diode D1 is in forward bias and D2 is off, the
equivalent circuit is

Capacitor C1 will charge upto +5 volt. VC1 =+ 5 volt

In negative halt cycle diode D1 is off and D2 is on.

Now capacitor VC2 will charge upto -10 volt in opposite direction.
Sol. 41 Option () is correct.
 GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

Let input Vin is a sine wave shown below

According to given transfer characteristics of rectifiers output of rectifier P is.

Similarly output of rectifier Q is

Output of a full wave rectifier is given as

To get output V0
V0 = K (- VP + VQ ) K - gain of op-amp
So, P should connected at inverting terminal of op-amp and Q with non-inverting
terminal.
Sol. 42 Option () is correct.
Sol. 43 Option (C) is correct.
For low frequencies,
w " 0, so 1 " 3
wC
Equivalent circuit is,
GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

Applying node equation at positive and negative input terminals of op-amp.

vA - vi + vA - vo = 0
R1 R2
2vA = vi + vo , a R 1 = R2 = R A
Similarly,
vA - vi + vA - 0 = 0
R3 R4
2vA = vin , a R3=R4=RB
So, vo = 0
It will stop low frequency signals.
For high frequencies,
w " 3, then 1 " 0
wC
Equivalent circuit is,

Output, vo = vi
So it will pass high frequency signal.
This is a high pass filter.
Sol. 44 Option (D) is correct.
In previous solution cutoff frequency of high pass filter is given by,
wh = 1
2p RA C
Here given circuit is a low pass filter with cutoff frequency,
wL = 1 = 2
2p R2 C
A
2pRA C
wL = 2wh
When both the circuits are connected together, equivalent circuit is,

So this is is Band pass filter, amplitude response is given by.

 GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

Sol. 45 Option (B) is correct.

In SOP form, F is written as
F = Sm (1, 3, 5, 6) = X Y Z +X YZ +X Y Z +X YZ
Solving from K- map

F = X Z + Y Z + XYZ
In POS form F = ( Y + Z) ( X + Z) ( X + Y + Z )
Since all outputs are active low so each input in above expression is complemented
F = ( Y + Z ) ( X + Z ) ( X + Y + Z)
Sol. 46 Option (B) is correct.
Given that SP = 2700 H
PC = 2100 H
HL = 0000 H
Executing given instruction set in following steps,
DAD SP & Add register pair (SP) to HL register
HL = HL + SP
HL = 0000 H + 2700 H
HL = 2700 H
PCHL & Load program counter with HL contents PC
= HL = 2700 H
So after execution contents are,
PC = 2700 H, HL = 2700 H
Sol. 47 Option (D) is correct.
If transistor is in normal active region, base current can be calculated as following,
By applying KVL for input loop,
10 - IC (1 # 103) - 0.7 - 270 # 103 IB = 0
bIB + 270 IB = 9.3 mA, ` IC = bIB
IB (b + 270) = 9.3 mA
IB= 9.3 mA = 0.025 mA
270 + 100
In saturation, base current is given by,
10 - IC (1) - VCE - IE (1) = 0
10 = I
C (sat) IC - IE
2
VCE - 0
IC (sat) = 5 mA
GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

IC (sat)
IB (sat) = =5 = .050 mA
b 100
IB 1 IB (sat), so transistor is in forward active region.
Sol. 48 Option (B) is correct.
In the circuit

We can analyze that the transistor is operating in active region.

VBE(ON) = 0.6 volt
VB - VE = 0.6
6.6 - VE = 0.6
VE = 6.6 - 0.6 = 6 volt
At emitter (by applying KCL),
IE = IB + IL
IE = 6 - 6.6 + 6 - 0.6 amp
1 kW 10 W
VCE = VC - VE = 10 - 6 = 4 volt
Power dissipated in transistor is given by.
PT = VCE # IC = 4 # 0.6 ` IC - IE = 0.6 amp
= 2.4 W
Sol. 49 Option (D) is correct.
This is a voltage-to-current converter circuit. Output current depends on input
voltage.

Since op-amp is ideal v+ = v- = v1

Writing node equation.
v1 - v + v1 - 0 = 0
R1 R2
+
v1 c 1 R2 m = V
R
R1R 2 R1
v1 = V c R2 m
R1 + R2
Since the op-amp is ideal therefore
 GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

iL = i 1 = v 1 = V R2
r r c R1 + R 2 m
Sol. 50 Option (D) is correct.
In the circuit output Y is given as
Y = [A 5 B] 5 [C 5 D]
Output Y will be 1 if no. of 1’s in the input is odd.
Sol. 51 Option () is correct.
This is a class-B amplifier whose efficiency is given as
h = p VP
4 VCC
where VP " peak value of input signal
VCC " supply voltage
here VP = 7 volt, VCC = 10 volt

so, h = p # 7 # 100 = 54.95% - 55%

4 10
Sol. 52 Option (B) is correct.
In the circuit the capacitor starts charging from 0 V (as switch was initially
closed) towards a steady state value of 20 V.
for t < 0 (initial) for t " 3 (steady state)

So at any time t , voltage across capacitor (i.e. at inverting terminal of op-amp)

is given by
v (t) = v (3) + [v (0) - v ( 3)] e - t RC

c c c c
- t

vc (t) = 20 (1 - e ) RC

Voltage at positive terminal of op-amp

v+ - vout + v+ - 0 = 0
10 100
v+ = 10 vout
11
Due to zener diodes, -5 # vout #+ 5
So, v+ = 10 (5) V
11
Transistor form - 5 V to +5 V occurs when capacitor charges upto v + .
So 20 (1 - e- t / RC ) = 10 # 5
11
1-e - t / RC
= 5
22
17 = e- t / RC
22
GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

t = RC ln` 22 j = 1 # 103 # .01 # 10-6 # 0.257 = 2.57 msec

17
Voltage waveforms in the circuit is shown below

Sol. 53 Option (B) is correct.

In a 555 astable multi vibrator circuit, charging of capacitor occurs through
resistor ( R A + R B ) and discharging through resistor R B only. Time for charging
and discharging is given as.
TC = 0.693 ( R A + RB) C = 0.693 RB C
But in the given circuit the diode will go in the forward bias during charging, so
the capacitor will charge through resistor R A only and discharge through RB only.
a R A = RB
So TC = TD
Sol. 54 Option (B) is correct.
First convert the given number from hexadecimal to its binary equivalent, then binary
to octal.
Hexadecimal no. AB. CD
Binary equivalent S 1 1 0 1 1 $ 1A B
0 10 S 1B0 0C S
11 0 1
A B C D
To convert in octal group three binary digits together as shown
S010 S 101 S 0 1 1 $S
11 0 S
0 11 S
010
2 5 3 6 3 2
So, ( AB.CD ) H = (253.632) 8
Sol. 55 Option (A) is correct.
First we can check for diode D2. Let diode D2 is OFF then the circuit is

In the above circuit diode D1 must be ON, as it is connected with 10 V battery

now the circuit is
 GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

Because we assumed diode D2 OFF so voltage across it VD2 # 0 and it is possible only
when D3 is off.

So, all assumptions are true.

Sol. 56 Option (D) is correct.
In the positive half cycle of input, Diode D1 will be reverse biased and equivalent
circuit is.

Since there is no feed back to the op-amp and op-amp has a high open loop gain
so it goes in saturation. Input is applied at inverting terminal so.
VP =- VCC =- 12 V
In negative half cycle of input, diode D1 is in forward bias and equivalent circuit
is shown below.

Output VP = Vg + V-
Op-amp is at virtual ground so V+ = V- = 0 and VP = Vg = 0.7 V
Voltage wave form at point P is
GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

Sol. 57 Option (A) is correct.

In the circuit when Vi < 10 V, both D1 and D2 are off.
So equivalent circuit is,

Output, Vo = 10 volt
When Vi > 10 V (D1 is in forward bias and D2 is off So
the equivalent circuit is,

Output, Vo = Vi
Transfer characteristic of the circuit is

Sol. 58 Option (C) is correct.

Here output of the multi vibrator is
V0 =! 12 volt
Threshold voltage at positive terminal of op-amp can be obtained as following
When output V0 =+ 12 V, equivalent circuit is,
 GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

writing node equation at positive terminal of op-amp

Vth - 12 + Vth - 0 = 0
10 10
Vth = 6 volt ( Positive threshold)
So, the capacitor will charge upto 6 volt.
When output V0 =- 12 V, the equivalent circuit is.

w
node equation
Vth + 12 + Vth - 0 = 0
2 10
5 Vth + 60 + Vth = 0
Vth =- 10 volt (negative threshold)
So the capacitor will discharge upto -10 volt.
At terminal P voltage waveform is.

Sol. 59 Option (B) is correct.

Assume that BJT is in active region, thevenin equivalent of input circuit is
obtained as
GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

Vth - Vi Vth - (- 12)

15 + 100 =0

20Vth - 20Vi + 3Vth + 36 = 0

23Vth = 20 # 5 - 36, Vi = 5 V
Vth = 2.78 V
Thevenin resistance R th = 15 KW | | 100 KW
= 13.04 KW
So the circuit is

Writing KVL for input loop

2.78 - Rth I B - 0.7 = 0
IB = 0.157 mA

Current in saturation is given as,

IC (sat)
IB (sat) =
b
IC(sat) = 12.2 = 5.4 mA
2.2
So, I B(sat) = 5.45 mA = 0.181 mA
30
Since IB(sat) > IB , therefore assumption is true.
Sol. 60 Option () is correct.
Sol. 61 Option () is correct.
Sol. 62 Option (A) is correct.
Function F can be obtain as,
F = I0S1S0 + I1S 1S 0 +I 2S 1S 0 +I 3S 1S 0
= A B C + A B C + 1 $BC + 0 $BC
= AB C + A BC +BC
= AB C + A BC +BC (A +A )
 GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

= AB C + A BC + ABC +A BC
= S(1, 2, 4, 6)
Sol. 63 Option (A) is correct.
MVI H and MVI L stores the value 255 in H and L registers. DCR L decrements
L by 1 and JNZ checks whether the value of L is zero or not. So DCR L executed
255 times till value of L becomes ‘0’.
Then DCR H will be executed and it goes to ‘Loop’ again, since L is of 8 bit so
no more decrement possible and it terminates.
Sol. 64 Option (A) is correct.
XCHG & Exchange the contain of DE register pair with HL pair So now addresses
of memory locations are stored in HL pair.
INR M & Increment the contents of memory whose address is stored in HL
pair.
Sol. 65 Option (A) is correct.
From the circuit we can observe that Diode D1 must be in forward bias (since current
is flowing through diode).
Let assume that D2 is in reverse bias, so equivalent circuit is.

Voltage Vn is given by
Vn = 1 # 2 = 2 Volt
Vp = 0
Vn > Vp (so diode is in reverse bias, assumption is true)
Current through D2 is ID2 = 0
Sol. 66 Option (C) is correct.
SHLD transfers contain of HL pair to memory location.
SHLD 2050 & L " M[2050H]
H " M[2051H]
Sol. 67 Option (D) is correct.
This is a N-channel MOSFET with VGS = 2 V
VTH =+ 1 V
VDS (sat) = VGS - VT H
VDS(sat) = 2 - 1 = 1 V
Due to 10 V source VDS > VDS (sat) so the NMOS goes in saturation, channel
conductivity is high and a high current flows through drain to source and it acts
as a short circuit.
So, Vab = 0
Sol. 68 Option (C) is correct.
Let the present state is Q(t), so input to D-flip flop is given by,
D = Q (t) 5 X
GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

Next state can be obtained as,

Q (t + 1) = D
= Q (t) 5 X
= Q (t) X + Q (t) X
= Q (t), if X = 1
and Q (t + 1) = Q (t), if X = 0
So the circuit behaves as a T flip flop.
Sol. 69 Option (B) is correct.
Since the transistor is operating in active region.
IE . bIB
IB = IE = 1 mA = 10 mA
b 100
Sol. 70 Option (C) is correct.
Gain of the inverting amplifier is given by, 6
Av =- RF =- 1 # 10 , RF= 1 MW
R1 R1
6
R1 =- 1 # 10
Av
Av =- 10 to -25 so value of R 1
106
R1 = = 100 kW for Av =- 10
10
R1 ' = 10 = 40 kW for A =- 25
6
v
25
R1 should be as large as possible so R1 = 100 kW
Sol. 71 Option (B) is correct.
Direct coupled amplifiers or DC-coupled amplifiers provides gain at dc or very
low frequency also.
Sol. 72 Option (C) is correct.
Since there is no feedback in the circuit and ideally op-amp has a very high value
of open loop gain, so it goes into saturation (ouput is either+ V or - V ) for small
values of input.
The input is applied to negative terminal of op-amp, so in positive half cycle it
saturates to - V and in negative half cycle it goes to + V .
Sol. 73 Option (B) is correct.
From the given input output waveforms truth table for the circuit is drawn as
X1 X2 Q
1 0 1
0 0 1
0 1 0
In option (A), for X1 = 1, Q = 0 so it is eliminated.
In option (C), for X1 = 0, Q = 0 (always), so it is also eliminated.
In option (D), for X1 = 0, Q = 1, which does not match the truth table. Only
option (B) satisfies the truth table.
Sol. 74 Option (D) is correct.
In the given circuit NMOS Q 1 and Q3 makes an inverter circuit. Q4 and Q5 are in
 GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

parallel works as an OR circuit and Q2 is an output inverter.

So output is
Q = X1 + X2 = X1.X2
Sol. 75 Option (B) is correct.
Trans-conductance of MOSFET is given by
gm = 2iD =
(2 - 1) mA
= 1 mS
2VGS (2 - 1) V
Sol. 76 Option (D) is correct.
Voltage gain can be obtain by small signal equivalent circuit of given amplifier.

vo =- gm vgs RD
vgs = vin
So, vo =- gm R Dvin
Voltage gain Av = vo =- gm RD =- (1 mS) (10 kW) =- 10
vi
Sol. 77 Option (D) is correct.
Let Q (t) is the present state then from the circuit,

So, the next state is given by

Q (t + 1) = Q (t) (unstable)
Sol. 78 Option (C) is correct.
Given circuit,

In the circuit
V1 = 3.5 V (given)
Current in zener is.
IZ = V1 - VZ = 3.5 - 3.3 = 2 mA
RZ 0.1 # 103
GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

Sol. 79 Option (C) is correct.

This is a current mirror circuit. Since VBE is the same in both devices, and
transistors are perfectly matched, then
IB1 = IB2 and IC1 = IC 2
From the circuit we have,

a I B1 = I B2
a IC1 = IC2, IC2 = bI B2

IR = IC1 + IB1 + IB2 = IC1 + 2IB2

2I
= IC2 + C2
b
IR = IC2 c1 + 2 m
b
IR
IC2 = I =
2
c1 + bm
IR can be calculate as
-5 + 0.7 =- 4.3 mA
IR =
1 # 103
4.3
So, I = - 4.3 mA
1 + 2
` 100 j
Sol. 80 Option (B) is correct.
The small signal equivalent circuit of given amplifier

Here the feedback circuit samples the output voltage and produces a feed back current Ifb
which is in shunt with input signal. So this is a shunt-shunt feedback configuration.
Sol. 81 Option (A) is correct.
In the given circuit output is stable for both 1 or 0. So it is a bistable multi-
vibrator.
Sol. 82 Option (A) is correct.
Since there are two levels (+ VCC or - VCC ) of output in the given comparator
 GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

circuit.
For an n -bit Quantizer
2n = No. of levels
2n = 2
n =1

Sol. 83 Option (C) is correct.

From the circuit, we can see the that diode D2 must be in forward Bias.
For D1 let assume it is in reverse bias.
Voltages at p and n terminal of D1 is given by Vp and Vn
Vp < Vn (D1 is reverse biased)

Applying node equation

Vp - 5 Vp + 8
+ =0
1 1
2Vp =- 3
Vp =- 1.5
Vn = 0
Vp < Vn (so the assumption is true and D1 is in reverse bias) and current in D1
ID1 = 0 mA

Sol. 84 Option (D) is correct.

The small signal ac equivalent circuit of given amplifier is as following.

Here RB = (10 kW < 10 kW) = 5 kW

gm = 10 ms
a gm rp = b & rp = 50 = 5 kW
10 # 10-3
Input resistance
Rin = RB < rp = 5 kW < 5 kW = 2.5 kW
Sol. 85 Option (D) is correct.
For PMOS to be biased in non-saturation region.
VSD < VSD(sat)
and
VSD(sat) = VSG + VT
GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

VSD(sat) = 4 - 1 "a VSG = 4 - 0 = 4 volt

= 3 Volt
So, VSD < 3
VS - VD < 3
4 - ID R < 3
1 < ID R
ID R > 1, ID = 1 mA
R > 1000 W
Sol. 86 Option () is correct.
Sol. 87 Option (B is correct.
If op-amp is ideal, no current will enter in op-amp. So current ix is
v -v
ix = x 6y ...(1)
1 # 10
v + = v- = v x (ideal op-amp)

vx - vy
+ vx - 0 =
3
0
100 # 10 10 # 103
vx - vy + 10vx = 0

11vx = vy ...(2)
For equation (1) & (2)
ix = vx - 11v x =- 10vx
1 # 106 106
Input impedance of the circuit. 6
Rin = vx =-10 =- 100 kW
ix 10
Sol. 88 Option (A) is correct.
Given Boolean expression,
Y = ( A $ BC + D ) (A $ D + B $ C )
= ( A $ BCD ) + (A BC $ B $C ) + (AD ) +B C D
= A BCD + AD +B C D
= AD (BC + 1) + B C D = AD + B C D
Sol. 89 Option (C) is correct.
The program is executed in following steps.
START MVI A, 14H " one instruction cycle.
RLC & rotate accumulator left without carry
RLC is executed 6 times till value of accumulator becomes zero.
JNZ, JNZ checks whether accumulator value is zero or not, it is executed 5 times.
HALT " 1-instruction cycle.
 GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

So total no. of instruction cycles are

n = 1 + 6 + 5 + 1 = 13
Sol. 90 Option (D) is correct.
In the given circuit, output is given as.
Y = ( A0 5 B0) 9 (A1 5 B 1) 9 (A 2 5B 2) 9(A 3 5B 3)
For option (A)
Y = (1 5 1) 9 (0 5 0) 9 (1 5 1) 9 (0 50)
=0909090=1
For option (B)
Y = (0 5 0) 9 (1 5 1) 9 (0 5 0) 9 ( 1 5 1)
=0909090=1
For option (C)
Y = (0 5 0) 9 (0 5 0) 9 (1 5 1) 9 ( 0 5 0)
=0909090=1
For option (D)
Y = (1 5 1) 9 (0 5 0) 9 (1 5 1) 9 ( 0 5 1)
=0909091=0
Sol. 91 Option (B) is correct.
In the given circuit, waveforms are given as,
GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

Sol. 92 Option (B) is correct.

In the given circuit
Vi = 0 V
So, transistor Q1 is in cut-off region and Q2 is in saturation.
5 - IC RC - VCE (sat) - 1.25 = 0
5 - IC RC - 0.1 - 1.25 = 0
5 - IC RC = 1.35
V0 = 1.35 "a V0 = 5 - IC RC

Sol. 93 Option (C) is correct.

Since there exists a drain current for zero gate voltage ( VGS = 0), so it is a
depletion mode device.
ID increases for negative values of gate voltages so it is ap -type depletion mode
device.
Sol. 94 Option (B) is correct.
Applying KVL in input loop,
4 - (33 # 103) IB - VBE - (3.3 # 103) IE = 0
a IE = (hfe + 1) IB
4 - (33 # 103) IB - 0.7 - (3.3 # 103) ( hfe +1) IB = 0
3.3 = 6(33 # 10 3) + (3.3 # 10 3) ( 99 + 1) @IB
IB = 3.3
33 # 103 + 3.3 # 103 # 100
IC = hfe IB
= 99 # 3.3 mA = 3.3 mA
[0.33 + 3.3] # 100 0.33 + 3.3
Sol. 95 Option (D) is correct.
Let the voltages at positive and negative terminals of op-amp are v+ and v-
respectively. Then by applying nodal equations.
 GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

v- - vin + v- - vout = 0
R1 R1
2 v-- = vin + vout ..(1)
Similarly,
v+ - vin + v+ - 0 = 0
R 1
c jwC m

v+ - vin + v + (jwCR ) = 0
v+ (1 + jwCR ) = Vin ..(2)
By equation (1) & (2)
2vin = vin + vout "a v+ = v- (ideal op-amp)
1 + jwCR
vin ; 2 - 1E = vout
1 + jw CR
(1 - jwCR )
vout = vin
1 + jwCR
Phase shift in output is given by
q = tan -1 (- wC R ) - tan -1 (wCR )
= p - tan -1 (wCR ) - tan -1(wCR )
= p - 2 tan -1 (wCR)
Maximum phase shift q =p
Sol. 96 Option (C) is correct.
In given circuit MUX implements a 1-bit full adder, so output of MUX is given
by.
F = Sum = A 5 Q 5 C in
Truth table can be obtain as.
P Q Cin Sum
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
Sum = P Q Cin + PQ Cin +P Q C in +P Q C in
Output of MUX can be written as
F = P Q $ I 0 + PQ $ I 1 +PQ $I 2 +PQ $I 3
Inputs are, I0 = Cin, I1 = Cin, I2 = Cin, I3 = Cin
Sol. 97 Option (D) is correct.
Program counter contains address of the instruction that is to be executed next.
Sol. 98 Option (A) is correct.
For a n -channel enhancement mode MOSFET transition point is given by,
VDS (sat) = VGS - VT H a VTH = 2 volt
GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

VDS (sat) = VGS - 2

From the circuit,
VDS = VGS
So VDS (sat) = VDS - 2 & VDS = VDS (sat) + 2
VDS > VDS (sat)
Therefore transistor is in saturation region and current equation is given by.
ID = K ( VGS - VTH ) 2
4 = K ( VGS - 2) 2

VGS is given by
VGS = VDS = 10 - ID RD = 10 - 4 # 1 = 6 Volt
So, 4 = K (6 - 2) 2
K =1
4
Now RD is increased to 4 kW, Let current is I ' and voltages are V ' = V '
D DS GS

Applying current equation.

I ' = K ( V ' - V )2
D GS TH
I ' = 1 ( V ' - 2) 2
D
4 GS'
V' = V = 10 - I # R ' = 10 - 4I '
'
GS DS D D D

So, 4I D' = (10 - 4I D' - 2) 2 = (8 - 4ID' ) 2

= 16 (2 - ID' ) 2

I'D = 4 (4 + I'D2 - 4I D' )

4I'D2 - 17 + 16 = 0
I'2D = 2.84 mA
Sol. 99 Option (D) is correct.
Let the voltages at input terminals of op-amp are v- and v+ respectively.
So, v+ = v- = 0 (ideal op-amp)

Applying node equation at negative terminal of op-amp,

0 -1vin + 0 - vx = 0 ...(1)
v -0 v 10
- v vx - 0
At node x 10 + 10 + 1 =0
x x out

vx + vx - vout + 10vx = 0
12 vx = vout
vx = vout
12
From equation (1), vin + vx = 0
1 10
vin =- vout
120
 GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

vout =- 120
vin
Sol. 100 Option (D) is correct.
In the positive half cycle (when Vin > 4 V) diode D2 conducts and D1 will be off
so the equivalent circuit is,

Vout = + 4 Volt
In the negative half cycle diode D1 conducts and D2 will be off so the circuit is,

Applying KVL
Vin - 10I + 4 - 10I = 0
Vin + 4 = I
20
Vin =- 10 V (Maximum value in negative half cycle)
So, I = -10 + 4 =- 3 mA
20 10
Vin - Vout = I
10
-10 - Vout =- 3
10 10
Vout =- (10 - 3)
Vout =- 7 volt
Sol. 101 Option (C) is correct.
In the circuit, the capacitor charges through resistor ( RA + RB) and discharges
through RB . Charging and discharging time is given as.

TC = 0.693 ( RA + RB) C
TD = 0.693 R B C
Frequency f= 1 = 1 = 1
T TD + TC 0.693 (R A + 2R B )C
1 = 10 # 103
0.693 ( RA + 2RB) # 10 # 10-9
14.4 # 103 = R A + 2RB ...(1)
T
duty cycle = C = 0.75
T
GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

0.693 (R A + RB) C 3
=
0.693 ( R A + 2R B ) C 4
4RA + 4RB = 3RA + 6RB
RA = 2RB ...(2)
From (1) and (2) 2R A = 14.4 # 10 3

RA = 7.21 kW
and RB = 3.60 kW
Sol. 102 Option (B) is correct.
Given boolean expression can be written as,
F = X YZ + X Y Z +XY Z +X YZ +X YZ
= X YZ + Y Z (X +X ) +X Y Z( +Z ) = X YZ + Y Z + X Y
= Y Z + Y (X +X Z ) a A +BC = (A +B ) A
( +C )
= Y Z + Y (X +X ) (X +Z ) = Y Z + Y (X +Z ) = Y Z + Y X + YZ
Sol. 103 Option (B) is correct.

X = X1 5 X 0, Y = X 2
Serial Input Z = X 5 Y = [X 1 5X 0] 5X 2
Truth table for the circuit can be obtain as.

Clock pulse Serial Input Shift register

Initially 1 1010
1 0 1101
2 0 0110
3 0 0011
4 1 0001
5 0 1000
6 1 0100
7 1 1010
So after 7 clock pulses contents of the shift register is 1010 again.
Sol. 104 Option (D) is correct.
Characteristic table of the X-Y flip flop is obtained as.
X Y Q Qn + 1
n

0 0 0 1
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 1
 GATE SOLVED PAPER - EE ANALOG & DIGITAL ELECTRONICS

1 0 1 0
1 1 0 0
1 1 0 0
Solving from k-map

Characteristic equation of X-Y flip flop is

Qn + 1 = Y Qn + XQn
Characteristic equation of a J-K flip-flop is given by
Qn + 1 = KQn + J Qn
by comparing above two characteristic equations
J =Y , K=X
Sol. 105 Option (A) is correct.
Total size of the memory system is given by.
= (212 # 4) # 8 bits
= 214 # 8 bits = 214 Bytes = 16 K bytes
Sol. 106 Option (C) is correct.
Executing all the instructions one by one.
LXI H, 1FFE & H = (1F) H, L = (FE) H
MOV B, M & B = Memory [HL] = Memory [1FFE]
INR L & L = L + (1) H = (FF) H
MOV A, M & A = Memory [HL] = Memory [1FFF]
ADD B & A = A + B
INR L & L = L + (1) H = (FF) H + (1) H = 00
MOV M, A & Memory [HL] = A
Memory [1F00] = A
XOR A & A = A XOR A = 0
So the result of addition is stored at memory address 1F00.

***********