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Introduction To Verilog

This document provides an introduction to the Verilog hardware description language. It outlines some key data types like wires and regs, how to specify constants, possible value assignments, operators, and the overall structure of a Verilog program using modules. Modules define functionality and can contain initial blocks, continuous assignments, and always blocks. Continuous assignments are used for combinational logic while always blocks can specify either sequential or combinational logic. An example half-adder circuit is provided to demonstrate continuous assignments. Always blocks are used to describe behavioral descriptions and contain sensitivity lists to determine when the block is reevaluated.

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34 views3 pages

Introduction To Verilog

This document provides an introduction to the Verilog hardware description language. It outlines some key data types like wires and regs, how to specify constants, possible value assignments, operators, and the overall structure of a Verilog program using modules. Modules define functionality and can contain initial blocks, continuous assignments, and always blocks. Continuous assignments are used for combinational logic while always blocks can specify either sequential or combinational logic. An example half-adder circuit is provided to demonstrate continuous assignments. Always blocks are used to describe behavioral descriptions and contain sensitivity lists to determine when the block is reevaluated.

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INTRODUCTION TO VERILOG

DATA TYPES

wire- specifies a combinational signal. (An actual wire)

reg (register)-holds a value. (It need not necessarily correspond to an actual register in an
implementation, although it often will.

CONSTANTS

-represented by prefixing the value with a decimal number specifying its size in bits.

-Example: 4’b0100 specifies a 4-bit binary constant with the value 4, as does 4’d4.

VALUES

❖ The possible values for a register or wire in Verilog are


⮚ 0 or 1, representing logical false or true
⮚ X, representing unknown, the initial value given to all registers and to any wire not connected to
something.
⮚ Z, representing the high-impedance state for tristate gates

OPERATORS

❖ Verilog provides the full set of unary and binary operators from C, including
⮚ The arithmetic operators (+,-,*,/),
⮚ The logical operators (&, |, ),
⮚ The comparison operators (==, !=, >, <, <=, >=),
⮚ The shift operators (<<, >>)
⮚ Conditional operators (?, which is used in the form condition ? expr1: expr2 and returns expr1 if
the condition is true and expr2 if it is false).

STRUCTURE OF A VERILOG PROGRAM

❖ A Verilog Program is structured as a set of modules, which may represent anything from a collection
of logic gates to a complete system.
❖ A Module specifies its input and output ports, which describe the incoming and outgoing
connections of a module.
❖ A Module may also declare additional variables.
❖ The body of a module consists of
⮚ Initial constructs, which can initialize reg variables
⮚ Continuous assignments, which define only combinational logic
⮚ Always constructs, which can define either sequential or combinational logic
⮚ Instances of other modules, which are used to implement the module being defined.
KEY THINGS TO REMEMBER

❖ A module in Verilog is NOT a function in software.


⮚ A function is a piece of code that can be called.
⮚ A module defines a functionality. A module can be USED, NOT CALLED. Once you use a module,
a physical piece of hardware will be allocated in the chip. If you use a module twice, there will be
two pieces of such hardware.
❖ Verilog is a Hardware Description Language.
⮚ You describe what you need.

THE HALF-ADDER. EXAMPLE OF CONTINUOUS ASSIGNMENTS

● Assign: continuous assignments. Any change in the input is reflected immediately in the output.
● Wires may be assigned values only with continuous assignments.

BEHAVIORAL DESCRIPTION – THE ALWAYS BLOCK

ALWAYS

● always @(A, B, Sel) – means that the block is reevaluated every time any one of the signals in the
list changes value.
● NOT A FUNCTION CALL
● If no sensitive list, always evaluated
● Always keep in mind that it is used to describe the behavior of a piece of hardware you wish to
design. Basically, it is used to tell Verilog what kind of gates should be used.
ALWAYS BLOCK CONTINUED

● Only reg variables can be assigned values in the always block – output reg 0;
● When we want to describe combinational logic using an always block, care must be taken to
ensure that the reg does not synthesize into a register.

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