SAR Hybrid Pipeline ADC

Gaurav Singh

Department of Electronics and Nanoengineering

Aalto University, School of Electrical Engineering

20.05.2020
Outline
• ADC requirement and architecture
• Analog Design Challenge due to device scaling
• ADC performance parameter
• SAR ADC
• Pipeline ADC
• Hybrid SAR-Pipeline ADC
• Recent Publications in Hybrid Pipeline SAR ADC
• Assignment
 Real World vs. Bandwidth

Ref: TI.com [2]

ADC Architectures
• There are many different ADC Architectures
• Successive Approximation (SAR)
• Delta-Sigma
• Pipeline
• Flash
• Delta-Sigma converters determine the digital word by
• Oversampling
• Applying Digital Filtering
• SARs determine the digital word by
• Sampling the input signal
• Using an iterative process
• Pipeline converters determine digital word by
• Undersampling
• With Sample / Gain Algorithm Topology
• Multiple stages / Larger Cycle-latency
 ADC Technology: Delta-Sigma

Advantages Disadvantages
• High Resolution • Cycle-latency
• Higher Stability (averages and filters out noise) • Low Speed
• Low power
• Low cost

Ref: TI.com [2]

 ADC Technology: SAR

Advantages Disadvantages
• Zero Cycle Latency • Max sample rates 2-5 MHz
• Low latency-time
• High accuracy
• Typically low power
• Easy to use

Ref: TI.com [2]

 ADC Technology: Pipeline

Advantages Disadvantages
• Higher Speeds • Lower resolution
• Higher Bandwidth • Pipeline Delay/Data Latency
• More Power

Ref: TI.com [2]

 Selecting ADC Topology

Ref: TI.com [2]

Device Scaling: Analog Design Challenges
• CMOS technology has been the predominant choice for
implementing digital circuits because of advantages such as :
• near-zero static power
• high density and
• device scalability
• Analog design benefits have not scaled like digital designs
 Device Scaling: Analog Design Challenges
Circuits like ADC have not been able to take advantage of aggressive scaling, three
Main reasons:

1. Low Voltage Supply

• Scaling requires supply voltage reduction to maintain electric-field within the device unchanged
• Analog circuits rely on large signal swings: for large signal power and wide dynamic range
2. Poor Matching
• Analog circuits rely on good component matching to process analog signals
• Comparators rely on matching b/w transistors to give accurate decisions
3. Poor Linearity
• Short channel: low and non-linear o/p resistance
• Degraded gain and linearity of transistor
• Analog circuits rely on large transistor gain and linearity to process & amplify analog
signals.

Ref: Chun C. Lee [4]

Basic ADC architecture

• The flash ADC architecture is the simplest

• Comparator bank: 2N-1 comparators

• Reference Ladder: provides 2N-1 ref. voltages

• Thermometer to binary encoder

ADC Performance Parameters
• Static Parameters

• Differential Non-Linearity (DNL)

• Integral Non-Linearity (INL)

• Dynamic Parameters

• Signal-to-Noise Ratio (SNR)

• Signal-to-Noise and Distortion Ratio (SNDR)

• Effective Number of Bits (ENOB)

• SFDR (Spurious Free Dynamic Range)

• Figure of Merit (FOM)

Static Parameters
• ADC step-size is defined as the smallest change in input
voltage required, to obtain a unit change in the output
code.

• For an ideal ADC, the step-size is uniform

• DNL, for the ith code transition, is defined as the

difference between the actual step-size and the ideal
step size that causes the transition

• DNLi = Actual step-size for ith code transition – Ideal step-

size
 Static Parameters

• INL, for the ith code, is defined as follows (assuming ADC codes

start from i=0):

• INLi = σ𝑖𝑗=0 𝐷𝑁𝐿𝑗

• Thus DNL and INL parameters capture the deviation in step sizes of

the ADC.

• Both DNL and INL are measured in LSB (Least Significant Bit). One

LSB corresponds to the ideal step size of the ADC

Dynamic Parameters
• Dynamic parameters are a measure of the ADC performance with respect to a time-varying input
signal.

• To measure these parameters, a pure sinusoid input is fed to the ADC and the ADC output
spectrum is analyzed using techniques such as Fast Fourier Transform (FFT).

• SNR is the ratio of sinusoid power to total noise power excluding harmonic distortion.

• SNDR: The ratio of sinusoid power to total noise power at the output is the SNDR of the ADC

• From the SNDR (in dB) we can calculate ENOB as follows:

𝑆𝑁𝐷𝑅(𝑑𝐵)−1.76
• 𝑬𝑵𝑶𝑩 = 6.02
Dynamic Parameters

• The ratio of the sinusoid power to the largest interferer power is the
SFDR of the ADC.

• Spurious free dynamic range (SFDR) is the ratio of the rms value of
the signal to the rms value of the worst spurious signal regardless of
where it falls in the frequency spectrum.
Dynamic Parameters
• Another important ADC parameter is the power consumption of the ADC. Usually a high-speed, or high-resolution
ADC will consume more power as compared to its low-speed or low-resolution counterpart.

• To compare ADCs with different speeds and resolutions a figure-of-merit (FOM) has been devised that normalizes an
ADC’s speed, resolution and power consumption to a single performance parameter

• This FOM is given by:

𝑷
• 𝑭𝒐𝑴 =
𝟐.𝐁𝐖 ∗𝟐𝐄𝐍𝐎𝐁

• Where P is the power consumption of the ADC, ENOB is calculated from SNDR and BW is effective BW or Nyquist
frequency (whichever is smaller) of the ADC

• This FOM has units of energy per conversion-step

SAR ADC
Advantage: SAR ADC
• The architecture uses only one comparator

• No op-amps are required for implementation. Thus the architecture has minimum analog complexity

• Comparator offset can be modeled as an input referred offset for the whole ADC

• Thus comparator offsets don’t cause non-linearity as in the case of other ADC architectures.

• It has very low power consumption because of the absence of op-amps and the use of only one
comparator.

• This architecture shows excellent scalability with process because of the lack of analog building blocks.
Disadvantage: SAR ADC
• The SAR ADC architecture suffers from a few but serious disadvantages that have prevented it from
being used in high-speed, high-resolution ADCs.

• They are as follows:

• The serial nature of SAR architecture limits its speed.

• The number of unit capacitors required for an N-bit SAR ADC is about 2N-1 (for differential implementation it is 2N). This
becomes prohibitively large for N>10.

• Capacitors can be connected in series or a 2C/C capacitor array can be used to reduce the number of unit capacitors
required, but their accuracy gets compromised because of the presence of parasitic capacitors.

• Comparator noise causes performance degradation of the ADC because of the lack of gain in the ADC architecture.
One can put a preamplifier before the comparator to reduce this noise, but at the expense of burning more power in the
preamplifier.

• Because of these reasons, low-power SAR ADCs have been limited to resolutions of 10-bits.
Pipeline ADC
 Pipeline ADC

Ref: Chun C. Lee [4]

 Pipeline ADC

Ref: Chun C. Lee [4]

Advantage: pipeline archtecture
• The pipeline architecture is well suited to implementing ADCs with moderate to high resolutions

(8–14-bit) and moderate to high speeds (10-200MHz)

• The high throughput nature of the architecture makes it a good candidate for implementing

highspeed ADCs

• The presence of redundancy and gain relaxes the comparator offset requirements
Disadvantage: pipeline archtecture
• High gain op-amps are required in the initial stages of the pipeline to reduce errors due to finite op-amp
gain. This is difficult to achieve in low-voltage nanometer CMOS processes.

• Large op-amp bandwidth is also required to reduce errors due to finite settling.

• Thus op-amps dissipate a considerable amount of power in a pipeline ADC.

• Good capacitor matching is also required in the initial stages of the pipeline.

• Capacitor matching in modern CMOS processes is limited to about 11-bits. This makes the
implementation of pipeline ADCs with resolutions >12-bits difficult without the use of calibration for
capacitor mismatch.

• A front-end S/H is usually required in a high-resolution, high-speed pipeline ADC to reduce aperture
errors between the signal sampled by the input sampling capacitors (C1-C4 in Fig) and the sub-ADC.

• The front-end S/H dissipates considerable power and also eats into the noise budget of the whole
ADC.
 SAR Assisted Pipeline Architecture

Ref: Chun C. Lee [8], JSSC

 SAR Assisted Pipeline Architecture

Ref: Chun C. Lee [8]

 SAR Assisted Pipeline Architecture

• Power and Area efficient hybrid ADC

• FoM= 52fJ/Conversion-step

• Resolution= 12bits

• First Stage = 5+1 bits pipeline ADC

• Second Stage= 7-bit SAR ADC

Ref: Chun C. Lee [8]

 SAR Assisted Pipeline Architecture

Ref: Chun C. Lee [8]

A Temperature-Stabilized Single-Channel 1-GS/s 60-dB SNDR SAR-
Assisted Pipelined ADC with Dynamic Gm-R-Based Amplifier

Ref: [5] , Wenning Jiang et. al., JSSC, Feb-2020

 A Temperature-Stabilized Single-Channel 1-GS/s 60-dB SNDR SAR-
Assisted Pipelined ADC with Dynamic Gm-R-Based Amplifier, Wenning
Jiang et. al., JSSC, Feb-2020

Ref: [5] , Wenning Jiang et. al., JSSC, Feb-2020

 A 1GS/s 12-Bit Pipelinned/SAR Hybrid ADC in 40nm CMOS
Technology

Ref: [7] Jianwen Li et. al., EOAJ 2020

 A 1GS/s 12-Bit Pipelinned/SAR Hybrid ADC in 40nm CMOS
Technology

Ref: [7] Jianwen Li et. al., EOAJ 2020

 A 280MS/s 12b SAR-Assisted Hybrid ADC with Time Domain Sub-
Range Quantizer in 45nm CMOS. Zhan Su et. al., CICC 2019

Fig. Block diagram of the proposed 12b hybrid pipelined two-stage ADC with an 8b SAR ADC as the coarse stage and a 6b 2D Vernier TDC as the fine stage

Ref: [6] Zhan Su et. al., CICC 2019

 A 280MS/s 12b SAR-Assisted Hybrid ADC with Time Domain Sub-
Range Quantizer in 45nm CMOS

Ref: [6] Zhan Su et. al., CICC 2019

Conclusion

• SAR ADC architectures are popular for achieving high energy efficiency

but they suffer from resolution and speed limitations.

• On the other hand, pipeline ADC architectures can achieve high resolution

and speed but have lower energy-efficiency and are more complex.

• Hybrid SAR-Pipeline ADCs can achieves low-power, high-resolution and

high-speed operation
References
1. https://en.wikipedia.org/wiki/Successive_approximation_ADC

2. Choose the right A/D converter for your application, Texas Instruments,
https://www.ti.com/europe/downloads/Choose%20the%20right%20data%20converter%20for%20your%20applicatio
n.pdf

3. Understanding ADC Specifications, Microchip, https://microchipdeveloper.com/adc:understanding-adc-specifications

4. Improving Accuracy and Energy Efficiency of Pipeline Analog to Digital Converters, Chun C. Lee, PhD Thesis, The
University of Michigan, 2010

5. A Temperature-Stabilized Single-Channel 1-GS/s 60-dB SNDR SAR-Assisted Pipelined ADC with Dynamic Gm-R-
Based Amplifier, Wenning Jiang et. al., JSSC, Feb-2020

6. A 280MS/s 12b SAR-Assisted Hybrid ADC with Time Domain Sub-Range Quantizer in 45nm CMOS. Zhan Su et. al.,
CICC 2019

7. A 1GS/s 12-Bit Pipelinned/SAR Hybrid ADC in 40nm CMOS Technology, Jianwen Li et. al.,EOAJ, Feb-2020

8. A SAR-Assisted Two-Stage Pipeline ADC, Chun C. Lee et. al., JSSC 2011
Assignment
• Using the given SNDR of Hybrid ADC proposed by Wenning
Jiang et. al. [5], Zhan Su et. al. [6], and Jianwen Li et. al. [7],
calculate the ENOB values for the ADCs.
Thank You!