EE 466/586

VLSI Design
Partha Pande
School of EECS
Washington State University
pande@eecs.wsu.edu
 Lecture 2
The MOS Transistor
(Reference: Chapter 2 of Weste and Harris or Chapter 2 of HJS)
The MOS Transistor

Polysilicon Aluminum
Structural Details
 Channel length L
 Typical values of L today vary from 90nm to 32 nm
 The dimension will continue to scale according to
Moore’s law
 Perpendicular to the plane of the figure is the
channel width W
 Much larger than the minimum length
 Gate oxide thickness tox
 Around 25 Å
 Operational Mechanism
 We consider a NMOS transistor
 N+ source and N+ drain regions separated by p-type
material
 The body or substrate, is a single-crystal silicon wafer
 Suppose, source, drain and body are all tied to ground
and a positive voltage applied to the gate
 A positive gate voltage will tend to draw electrons from the
substrate into the channel region
 A conducting path is created between drain and source
 Current will flow from drain to source in presence of a
voltage difference between the source and the drain
 The gate voltage needed to initiate formation of a conducting
channel is termed as the threshold voltage Vt
Threshold Voltage: Concept
+
S VGS D
G
-

n+ n+

n-channel Depletion
Region
p-substrate

B
The Threshold Voltage

Follow board notes

What is a Transistor?

A Switch! An MOS Transistor

VGS ≥ V T |VGS|

Ron
S D
The Body Effect
0.9

0.85

0.8

0.75

0.7
VT (V)

0.65

0.6

0.55

0.5

0.45

0.4
-2.5 -2 -1.5 -1 -0.5 0
V (V)
BS
Current-Voltage Relations

 Follow board notes

Current-Voltage Relations
-4
x 10
6
VGS= 2.5 V

Resistive Saturation
4
VGS= 2.0 V

Quadratic
ID (A)

3
VDS = VGS - VT Relationship
2
VGS= 1.5 V

1
VGS= 1.0 V

0
0 0.5 1 1.5 2 2.5
VDS (V)
Transistor in Linear

VGS VDS
S
G ID
D

n+ –
V(x)
+ n+

L x

p-substrate

MOS transistor and its bias conditions

Transistor in Saturation
VGS

VDS > VGS - VT

G

D
S

- +
n+ VGS - VT n+

Pinch-off
Current-Voltage Relations
The Deep-Submicron Era
 The quadratic model is valid for long
channel devices
 In DSM, channel length is scaled
 Vertical and horizontal electric fields are
large and they interact with each other
 Saturation in DSM devices occur when the
carriers reach velocity saturation
Effect of high fields

Horizontal Field

Vertical Field
Effect of high fields (Cont’d)

 Effect of the vertical field on the mobility

 The vertical field increases the electron
scattering at the surface of the channel
 Follow board notes
 The horizontal field acts to reduce the
mobility even further
Velocity Saturation
Velocity Saturation (Cont’d)
Current Equations
Current Equation (Cont’d)
Current Equation (Saturation)
Current-Voltage Relations
The Deep-Submicron Era
-4
x 10
2.5

VGS= 2.5 V
Early Saturation
2

VGS= 2.0 V
1.5
ID (A)

Linear
1
VGS= 1.5 V Relationship

0.5 VGS= 1.0 V

0
0 0.5 1 1.5 2 2.5
VDS (V)
Perspective

ID
Long-channel device

VGS = VDD
Short-channel device

V DSAT VGS - V T VDS

 ID versus VGS
-4
x 10 x 10
-4
6 2.5

5
2

4 linear
quadratic 1.5
ID (A)

ID (A)
3

1
2

0.5
1
quadratic
0 0
0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5
VGS(V) VGS(V)

Long Channel Short Channel

 ID versus VDS

-4 -4
x 10 x 10
6 2.5
VGS= 2.5 V
VGS= 2.5 V
5
2
Resistive Saturation
4 VGS= 2.0 V
VGS= 2.0 V 1.5

ID (A)
ID (A)

3
VDS = VGS - VT 1 VGS= 1.5 V
2
VGS= 1.5 V

1
0.5 VGS= 1.0 V
VGS= 1.0 V
0 0
0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5
VDS(V) VDS(V)

Long Channel Short Channel

Simple Model versus SPICE
-4
x 10
2.5

VDS=VDSAT
2

Velocity
1.5
Saturated
ID (A)

Linear
1

VDSAT=VGT
0.5

VDS=VGT
Saturated
0
0 0.5 1 1.5 2 2.5
VDS (V)
A PMOS Transistor
-4
x 10
0
VGS = -1.0V

-0.2
VGS = -1.5V

-0.4
ID (A)

VGS = -2.0V
-0.6 Assume all variables
negative!
-0.8 VGS = -2.5V

-1
-2.5 -2 -1.5 -1 -0.5 0
VDS (V)
Transistor Model
for Manual Analysis
The Transistor as a Switch

VGS ≥ V T
Ron
S D

ID
V GS = VD D

Rmid

R0

V DS
VDD/2 VDD
The Transistor as a Switch