DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

KEC-653 CAD FOR ELECTRONICS LAB

LIST OF EXPERIMENTS:

Part A: PSPICE Experiments:

1. (a) Transient Analysis of BJT inverter using step input.

(b) DC Analysis (VTC) of BJT inverter
2. (a) Transient Analysis of NMOS inverter using step input.
(b) Transient Analysis of NMOS inverter using pulse input.
(c) DC Analysis (VTC) of NMOS inverter.
3. (a) Analysis of CMOS inverter using step input.
(b) Transient Analysis of CMOS inverter using step input with parameters.
(c) Transient Analysis of CMOS inverter using pulse input.
(d) Transient Analysis of CMOS inverter using pulse input with parameters.
(e) DC Analysis (VTC) of CMOS inverter with and without parameters.
4. Transient & DC Analysis of NAND Gate using CMOS inverter.
5. Transient & DC Analysis of NOR Gate inverter.
6. Design and perform the transient analysis of CMOS transmission gate.

Part B :HDL (using VHDL program module & verilog Module)

VHDL PROGRAMS v for vhsic

7. Design and Simulation of Full Adder using VHDL program module
8. Design and Simulation of 4x1 MUX using VHDL program module
9. Design and Simulation of BCD to Excess-3 code using VHDL program module

BEYOND SYLLABUS

1. Design differentiator and integrator using Multisim.

2. Design wein bridge oscillator using Multisim.
3. Design and simulate of Low-Pass Filter using Multisim.

Lab In charge HOD (ECE)

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INTRODUCTION TO SPICE
‫ـــــــــــــــــــــــــــــــــــــــــــــــــــــــــــــــــــــــــــــــــــــــــــــــــــــــــــــــــــــــــــــــــــــــــــــــ‬

Objectives:
• To Be familiar with the Circuit simulation.

• To be familiar with types of analysis in simulation program.

• To make analysis to some examples on each analysis.

Equipments:
Computer – Orcad software program.

Introduction:
SPICE is a powerful general purpose analog and mixed-mode circuit simulator that is used to verify
circuit designs and to predict the circuit behavior. This is of particular importance for integrated circuits.

SPICE- Simulation Program for Integrated Circuits Emphasis.

SPICE can do several types of circuit analyses. Here are the most important ones:
• Non-linear DC analysis: calculates the DC transfer curve.
• Non-linear transient and Fourier analysis: calculates the voltage and current as a function
of time when a large signal is applied; Fourier analysis gives the frequency spectrum.
• Linear AC Analysis: calculates the output as a function of frequency. A bode plot is
generated.
• Noise analysis
• Parametric analysis
• Monte Carlo Analysis

In addition, PSpice has analog and digital libraries of standard components (such as NAND,
NOR, flip-flops, MUXes, FPGA, PLDs and many more digital components ). This makes it a
useful tool for a wide range of analog and digital applications.
All analyses can be done at different temperatures. The default temperature is 300K.
The circuit can contain the following components:
• Independent and dependent voltage and current sources
• Resistors
• Capacitors

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• Inductors
• Mutual inductors
• Transmission lines
• Operational amplifiers
• Switches
• Diodes
• Bipolar transistors
• MOS transistors
• JFET
• MOSFET
• Digital gates

Algorithm of simulating a circuit

The following figure summarizes the different steps involved in simulating a circuit with Capture
and PSpice. We'll describe each of these briefly through a couple of examples.

Figure 1: Steps involved in simulating a circuit with PSpice.

The values of elements can be specified using scaling factors (upper or lower case):

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T or Tera (= 1E12); U or Micro (= E-6);

G or Giga (= E9); N or Nano (= E-9);
MEG or Mega (= E6); P or Pico (= E-12)
K or Kilo (= E3); F of Femto (= E-15)
M or Milli (= E-3);

Types of analysis:
1) BIAS Point or DC analysis
1. Draw the circuit shown in figure 2 on the capture window
2.With the schematic open, go to the PSPICE menu and choose NEW SIMULATION
PROFILE.
3. In the Name text box, type a descriptive name, e.g. Bias.
4. From the Inherit From List: select none and click Create.
5. When the Simulation Setting window opens, for the Analyis Type, choose Bias Point and
click OK.
6. Now you are ready to run the simulation: PSPICE/RUN
7. A window will open, letting you know if the simulation was successful. If there are errors,
consult the Simulation Output file.
8. To see the result of the DC bias point simulation, you can open the Simulation Output file
and it will be as shown below.

Results of the Bias simulation displayed on the schematic.

2) Transient Analysis
1. Draw the circuit as shown in figure
2. Insert the Vsin source from the library Source. Double click on the source and make the
following changes FREQ = 1000, AMPL = 1, VOFF = 0.
3. Set up the Transient Analysis: go to the PSPICE/NEW SIMULATION PROFILE.

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4. Give it a name (e.g. Transient). When the Simulation Settings window opens, select "Time
Domain (Transient)" Analysis. Enter also the Run Time. Lets make it 5 ms(5 periods since
FREQ = 1000). For the Max Step size, you can leave it blank or enter 10us.
5. Run PSpice.
6.The results is shown in figure

1.0V

0.5V

0V

-0.5V

-1.0V
0s 0.5ms 1.0ms 1.5ms 2.0ms 2.5ms 3.0ms 3.5ms 4.0ms 4.5ms 5.0ms
V(D1:2) V(V4:+)
Time

3) AC Sweep Analysis:
The AC analysis will apply a sinusoidal voltage whose frequency is swept over a specified range.
The simulation calculates the corresponding voltage and current amplitude and phases for each
frequency. When the input amplitude is set to 1V, then the output voltage is basically the transfer
function. In contrast to a sinusoidal transient analysis, the AC analysis is not a time domain
simulation but rather a simulation of the sinusoidal steady state of the circuit. When the circuit
contains non-linear element such as diodes and transistors, the elements will be replaced their small-
signal models with the parameter values calculated according to the corresponding biasing point.

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1. Create a new project and build the circuit as shown in figure

2. For the voltage source use VAC from the Sources library.
3. Make the amplitude of the input source 1V.
4. Create a Simulation Profile. In the Simulation Settings window, select AC Sweep/Noise.
5. Enter the start and end frequencies and the number of points per decade. For our example we
use 0.1Hz, 10 kHz and 11, respectively.
6. Run the simulation
7. In the Probe window, add the traces for the output voltage.
8. The results is as shown in figure 4

600mV

400mV

200mV

0V
100mHz 300mHz 1.0Hz 3.0Hz 10Hz 30Hz 100Hz 300Hz 1.0KHz 3.0KHz 10KHz
V(R4:2)
Frequency

4) DC Sweep Analysis:
The DC sweep is used to draw the voltage
transfer characteristic (VTC) between output
and input.
1) we connect the circuit as shown in figure

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2) from dc sweep analysis we choose primary sweep and we put the name of the source V1 and start value
(0),end value (12) and increment (0.1).
3) Then choose secondary sweep and put the name of the current source I2 and start value (-4u),end value
(12u) and increment (4u).
4) we put the current marker above R2 as shown.
5) The result will be as shown in the figure 8.

Output Current

2.0mA

1.0mA

0A

-1.0mA
0V 1V 2V 3V 4V 5V 6V 7V 8V 9V 10V 11V 12V
-I(R2)
V_V1

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EXPERIMENT: - 1 (a)

 AIM: Transient Analysis of BJT inverter using step input

THEORY:-Transistor functions as an inverter, when operated in only the cutoff and the
saturation regions of the transistor amplifier, not in the linear region. When the input voltage is
low, the transistor does not conduct, there is no current and the collector voltage (output) is
pulled up to VCC. When the input voltage is increased, the transistor begins to conduct, the
voltage drop across RC starts increasing, and the output voltage falls. Finally, when the input
voltage is high enough to drive the transistor into saturation, there is a fixed small drop (V CE=0.1
to 0.2 V) across the transistor and the output voltage saturates to this low value.
Voltage Transfer Characteristic graph of transistor gives the relation between input voltage i.e.
base voltage and the output voltage i.e. collector voltage. In this it is seen that the transistor
operates in three regions i.e. cut off region, forward active region and saturation region.

Transient analysis gives time domain waveforms which are plots of voltage or current versus
time.

CIRCUIT DIAGRAM:

R2

1k
V

V3
5V dc
Q1
R1

1k
V Q 2N 2222
V4
5V dc

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Transient Analysis Procedure:

1. Draw the circuit as shown in figure
2. Insert the Vdc source from the library.
3. Double click on the components and place the value.
4. Set up the Transient Analysis: go to the PSPICE/NEW SIMULATION PROFILE.
5. Give it a name (e.g. Transient). When the Simulation Settings window opens, select "Time
Domain (Transient)" Analysis.
6. Enter the Run Time. Lets make it 10000us. For the Max Step size, you can leave it blank or
enter 10us.
7. Run PSpice.

RESULT:

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EXPERIMENT: - 1 (B)‫ـ‬

 AIM:  (b) DC Analysis (VTC) of BJT inverter with parameters.

THEORY:-Transistor functions as an inverter, when operated in only the cutoff and the
saturation regions of the transistor amplifier, not in the linear region. When the input voltage is
low, the transistor does not conduct, there is no current and the collector voltage (output) is
pulled up to VCC. When the input voltage is increased, the transistor begins to conduct, the
voltage drop across RC. starts increasing, and the output voltage falls. Finally, when the input
voltage is high enough to drive the transistor into saturation, there is a fixed small drop (V CE=0.1
to 0.2 V) across the transistor and the output voltage saturates to this low value.Voltage Transfer
Characteristic graph of transistor gives the relation between input voltage i.e. base voltage and
the output voltage i.e. collector voltage. In this it is seen that the transistor operates in three
regions i.e. cut off region, forward active region and saturation region.
DC analysis gives DC voltage or current, usually versus a stepped voltage or current.

CIRCUIT DIAGRAM:

R2

1k
V

V3
5Vdc
Q1
R1

1k
V Q 2N 2222

V4
5Vdc

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DC Sweep Analysis Procedure:

The DC sweep is used to draw the voltage transfer characteristic (VTC) between output and
input.
1. we connect the circuit as shown in figure
2. Set up the DC Sweep: go to the PSPICE/NEW SIMULATION PROFILE
3. From dc sweep analysis we choose primary sweep and we put the name of the source V4
and start value (0),end value (5V) and increment (0.1).
4. Place the Voltage marker above R1 and R2 as shown.
5. The result will be as shown below.
6. RESULT

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EXPERIMENT: - 2 (a)

AIM: - Transient Analysis of NMOS inverter uses step input.

THEORY: - NMOS inverter circuit with an enhancement load with the substrate connected to
ground. Although, the source-to-body voltage (VSB) of M1 is zero, that of M2 is equal to VO. As a
result, the threshold voltage of M2 is no longer equal to the threshold voltage of M1. For straight
forward hand analysis, it is common to neglect the transistor body effect and assume that each
transistor has the same threshold voltage

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Transient analysis gives time domain waveforms which are plots of voltage or current versus
time

CIRCUIT DIAGRAM:-

M1

BSS129

V
V2
M2 5Vdc

L2082
V
V1
5Vdc

0
5.000V

Transient Analysis Procedure:

1. Draw the circuit as shown in figure
2. Insert the Vdc source from the library.
3. Double click on the components and place the value.
4. Set up the Transient Analysis: go to the PSPICE/NEW SIMULATION PROFILE.
5. Place the Voltage marker
6. Give it a name. When the Simulation Settings window opens, select "Time Domain
(Transient)" Analysis.

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7. Enter the Run Time. Let’s make it 10000us. For the Max Step size, you can leave it blank or
enter 10us. and Run PSpice.

RESULT

EXPERIMENT NO.02b

 AIM: - Transient Analysis of NMOS inverter uses pulse input.

THEORY: For the same NMOS inverter circuit diagram when pulse input is used, the output
waveform is just inverted as followed with input waveform as shown in diagram.

CIRCUIT DIAGRAM:-

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M3

B SS 129

V
V2
O F F TI M E = . 5 u S D S TM 1 M2 5V dc
O N T I M E = . 5 u S CLK
D ELAY = L2082
S TA R TV A L = 0 V
OPPVAL = 1

Transient Analysis Procedure:

1. Draw the circuit as shown in figure
2. Insert the digital clock and VDC from the library and give the value.
3. Set up the Transient Analysis: go to the PSPICE/NEW SIMULATION PROFILE.
4. Give it a name. When the Simulation Settings window opens, select "Time Domain
(Transient)" Analysis.
5. Enter the Run Time. Lets make it 10000us. For the Max Step size, you can leave it blank or
enter 10us. Place the Voltage marker.
6. Run PSpice.

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Result

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EXPERIMENT NO:-2(c)

AIM:-DC Analysis (VTC) of NMOS inverter with PARAMETERS

THEORY: - DC analysis gives DC voltage or current, usually versus a stepped voltage or

current.

M3

B SS 129

V
V2
M2 5Vdc
V3 L2082
5Vdc V

0
CIRCUIT DIAGRAM:-

DC Sweep Analysis Procedure:

The DC sweep is used to draw the voltage transfer characteristic (VTC) between output and
input.
1. Connect the circuit as shown in figure
2. Set up the DC Sweep: go to the PSPICE/NEW SIMULATION PROFILE
3. From dc sweep analysis we choose primary sweep and we put the name of the source V3
and start value (0),end value (5V) and increment (0.1).
4. Place the Voltage marker above R1 and R2 as shown.
5. Run the circuit
6. The result will be as shown below.

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RESULTS

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EXPERIMENT NO :-3(a)

AIM: - Analysis of CMOS inverter uses step input.

THEORY:-CMOS Inverter
The inverter circuit as shown in the figure below. It consists of PMOS and NMOS FET. The
input A serves as the gate voltage for both transistors. The NMOS transistor has input from Vss
(ground) and the PMOS transistor has input from Vdd the terminal Y is output. When a high
voltage (~ Vdd) is given at input terminal (A) of the inverter, the PMOS becomes an open
circuit, and NMOS switched OFF so the output will be pulled down to Vss. When a low-level
voltage (<Vdd, ~0v) applied to the inverter, the NMOS switched OFF and PMOS switched ON.
So the output becomes Vdd or the circuit is pulled up to Vdd.

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INPUT LOGIC INPUT OUTPUT LOGIC OUTPUT

0v 0 Vdd 1

Vdd 1 0v 0

CIRCUIT DIAGRAM:-

V1
5V dc

0
M1

M2SJ 598/N E C

V V
V2
5Vdc M2

M2SK3295/N EC
0

Transient Analysis
0
Procedure:
1. Draw the circuit as shown in figure
2. Insert the VDC from the library and give the value.
3. Set up the Transient Analysis: go to the PSPICE/NEW SIMULATION PROFILE.
4. Give it a name. When the Simulation Settings window opens, select "Time Domain
(Transient)" Analysis.
5. Enter the Run Time. Let’s make it 10000us. For the Max Step size, you can leave it blank or
enter 10us. Place the Voltage marker. Run PSpice.

RESULTS

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EXPERIMENT NO.:-3(b)

 AIM: - Transient Analysis of CMOS inverter using step input with parameters.

THEORY:
The term CMOS stands for “Complementary Metal Oxide Semiconductor,” this means that we
use both NMOS and PMOS devices in order to achieve the desired digital logic.
In this post and the ones that follow, we will go through the transistor level implementation of
CMOS technology. We will try to understand how each of the gates are formed using simple
transistor devices. As we are concerned with CMOS technology, we will only be dealing with
logic gate implementations using MOSFETs. 

CIRCUIT DIAGRAM:-

RESULT

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EXPERIMENT NO: 3(c)

AIM:- Transient Analysis of CMOS inverter using pulse input.

CIRCUIT DIAGRAM:-

V1
5Vdc

0
M1

M2S J 598/N E C

V V
V1 = 0 V2
V2 = 5 M2
TD =
TR = 1 n s
TF = 1 n s M2SK3295/N EC
PW = 1m s
PER = 2m s

0
0

Transient Analysis Procedure:

1. Draw the circuit as shown in figure
2. Insert the Vpulse input and VDC supply from the library and put the given value.
3. Set up the Transient Analysis: go to the PSPICE/NEW SIMULATION PROFILE.
4. Give it a name. When the Simulation Settings window opens, select "Time Domain
(Transient)" Analysis.
5. Enter the Run Time. Lets make it 10000us. For the Max Step size, you can leave it blank or
enter 10us. Place the Voltage marker.
6. Run PSpice.

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RESULT

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EXPERIMENT NO :-(3d)‫ـ‬

 AIM: - Transient Analysis of CMOS inverter using pulse input with parameters.

CIRCUIT DIAGRAM:-

V1
5Vdc

0
M1

M2S J 598/N E C

V1 = 0 V2
V2 = 5 M2
TD =
TR = 0
TF = 0 M2S K 3295/N E C
PW = 10ns
PE R = 30ns

0
0

Transient Analysis with parameter Procedure:

1. Draw the circuit as shown in figure
2. Insert the Vpulse input and VDC supply from the library and put the given value.
3. Set up the Transient Analysis: go to the PSPICE/NEW SIMULATION PROFILE.
4. Give it a name. When the Simulation Settings window opens, select "Time Domain
(Transient)"Analysis.
5. Enter the Run Time. Lets make it 10000us. For the Max Step size, you can leave it blank or
enter 10us. Place the Voltage marker on output.
6. Run PSpice.

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RESULT

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EXPERIMENT NO:-3(e)

 AIM:-DC Analysis (VTC) of CMOS inverter with and without parameters.

CIRCUIT DIAGRAM:-

V1
5V dc

0
M1

M2S J 598/N E C

V V
V2
5Vdc M2

M2S K3295/N EC

0
0

DC Sweep Analysis Procedure:

The DC sweep is used to draw the voltage transfer characteristic (VTC) between output and
input.
1. Connect the circuit as shown in figure
2. Set up the DC Sweep: go to the PSPICE/NEW SIMULATION PROFILE
3. From dc sweep analysis we choose primary sweep and we put the name of the source V2
and start value (0),end value (5V) and increment (0.1).
4. Place the Voltage marker as shown in the figure .

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5. Run the circuit

6. The result will be as shown below.

RESULT

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EXERIMENT:-4

 AIM: . Transient & DC Analysis of NAND Gate using CMOS inverter.

CMOS NAND Gate

THEORY:-The below figure shows a 2-input Complementary MOS NAND gate. It consists of
two series NMOS transistors between Y and Ground and two parallel PMOS transistors between
Y and VDD.If either input A or B is logic 0, at least one of the NMOS transistors will be OFF,
breaking the path from Y to Ground. But at least one of the p MOS transistors will be ON,
creating a path from Y to VDD.

Two Input NAND Gate

Hence, the output Y will be high. If both inputs are high, both of the nMOS transistors will be
ON and both of the pMOS transistors will be OFF. Hence, the output will be logic low. The truth
table of the NAND logic gate given in the below table.

Pull-up
A B Pull-Down Network Network OUTPUT Y
0 0 OFF ON 1
0 1 OFF ON 1
1 0 OFF ON 1
1 1 ON OFF 0

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CIRCUIT DIAGRAM:-

5V dc
V2

M2N 6851 M2N 6851

M8 M9

2.499m V

O F F TI M E = . 5 u S D S TM 3 M6 V
O N T I M E = . 5 u S CLK
D ELAY =
S TA R TV A L = 0 V M2N 6660
OPPVAL = 1

O F F TI M E = 1 u S D S TM 4 M7
O N TIM E = 1u S CLK
D ELAY =
S TA R TV A L = 0 V M2N 6660
OPPVAL = 1
0

RESULT

Transient Analysis of NAND Gate.

5.0V

2.5V

0V
V(DSTM3:1)
5.0V

2.5V

SEL>>
0V
V(DSTM4:1)
10V

0V

-10V
0s 1us 2us 3us 4us 5us 6us 7us 8us 9us 10us
V(M9:d)
Time

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EXPERIMENT:-5

 AIM:-Transient & DC Analysis of NOR Gate inverter.

THEORY:

Logic NOR Gate The logic or Boolean expression given for a logic NOR gate is that for Logical
Multiplication which it performs on the complements of the inputs. The Boolean expression for a
logic NOR gate is denoted by a plus sign, ( + ) with a line or Overlie, ( ‾‾ ) over the expression to
signify the NOT OR logical negation of the NOR gate giving us the Boolean expression of

CIRCUIT DIAGRAM:-

V1
5V dc

0
M4

M TD 2 9 5 5 V / O N

M5

M TD 2 9 5 5 V / O N

V1 = 0 V2 V M6 M7
V2 = 5
TD = M TD 2 N 5 0 / O N M TD 2 N 5 0 / O N
TR =
TF =
P W = 20ns
P ER = 40ns

DC Sweep Analysis Procedure:

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The DC sweep is used to draw the voltage transfer characteristic (VTC) between output and
input.
1. Connect the circuit as shown in figure
2. Set up the DC Sweep: go to the PSPICE/NEW SIMULATION PROFILE
3. From dc sweep analysis we choose primary sweep and we put the name of the source V2
and start value (0),end value (5V) and increment (0.1).
4. Place the Voltage marker as shown in the figure .
5. Run the circuit
6. The result will be as shown below.

RESULTS
(A) DC Analysis of NOR gate Inverter.

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Transient Analysis of NOR gate.

5Vdc
V3
M 2N 6851

M12

M 2N 6851

M13

O F F TIM E = . 5 u S D S TM 5 M10 M11

O N TI M E = . 5 u S CLK
D ELAY =
S TA R TV A L = 0 V M 2N 6660
O PPVAL = 1

0
O F F TIM E = 1 u S D S TM 6
O N TI M E = 1 u S CLK
D ELAY =
S TA R TV A L = 0 V
OPPVAL = 1

Transient Analysis with parameter Procedure:

1. Draw the circuit as shown in figure
2. Insert the Vpulse input and VDC supply from the library and put the given value.
3. Set up the Transient Analysis: go to the PSPICE/NEW SIMULATION PROFILE.
4. Give it a name. When the Simulation Settings window opens, select "Time Domain
(Transient)" Analysis.
5. Enter the Run Time. Lets make it 20ms. For the Max Step size, you can leave it blank or enter
10us. Place the Voltage marker on output.
6. Run PSpice.

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RESULTS

(A) Transient Analysis of NOR Gate

5.0V

2.5V

0V
V(DSTM5:1)
10V

0V

SEL>>
-10V
V(DSTM6:1)
10V

0V

-10V
0s 1us 2us 3us 4us 5us 6us 7us 8us 9us 10us
V(M13:d)
Time

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EXPERIMENT:-6

AIM:- To design and perform the transient analysis of CMOS transmission gate.

DESCRIPTION:

MOS Diagram

SPICE simulation of a circuit used in CMOS design to pass or not pass a signal. It’s made up of
the parallel connection of a NMOS and a PMOS device.
Note that I have removed the arrow that usually identifies the source. This is because the source
terminal actually changes according to whether V1 is higher than V2 or V2 is higher than V1.

As you probably expected, this circuit is far from a perfect switch. One problem is the source
voltage: The current through the MOSFET is influenced by the source voltage, and the source
voltage depends on whatever signal is passing through the switch. Indeed, if the gate is
controlled by a driver that cannot exceed VDD, the transistor can pass signals only as high as
VDD minus the threshold voltage.

When you analyze and ponder this switch, you recognize a certain asymmetry. For example, if
we are using this switch for pass-transistor logic, the NMOS can effectively pass a logic-low
signal but not a full logic-high signal. Is it possible to modify the circuit in a way that will
redress this asymmetry? If you are maintaining a good CMOS mentality, your intuition might tell
you that we could achieve better overall performance by incorporating a PMOS transistor to
compensate for the deficiencies of the NMOS. In this case, your intuition is correct.

Here we have a PMOS in parallel with the NMOS; I used an “invert” circle to identify the PMOS
transistor. Note that the control signal applied to the PMOS is the complement of the control
signal applied to the NMOS; this is reminiscent of the CMOS inverter, where a logic-high
voltage turns on the NMOS and a logic-low voltage turns on the PMOS.

This CMOS transmission gate is a synergistic system—the NMOS provides good switch
performance under conditions that are favorable for itself but not for the PMOS, and the PMOS
provides good switch performance under conditions that are favorable for itself but not for the

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NMOS. The result is a simple yet effective bidirectional voltage-controlled switch that is suitable
for both analog and digital applications.

Pass Transistor Diagram

CIRCUIT DIAGRAM:-

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OUTPUT WAVEFORM:

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HDL
(USING VHDL PROGRAMS)

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EXPERIMENTS- 7

AIM: Design and Simulation of Full Adder using VHDL program module.

SOFTWARE REQUIRED: VHDL

Description: Full Adder is the adder which adds three inputs and produces two outputs. The
first two inputs are A and B and the third input is an input carry as C-IN. The output carry is
designated as C-OUT and the normal output is designated as S which is SUM.

A full adder logic is designed in such a manner that can take eight inputs together to create a
byte-wide adder and cascade the carry bit from one adder to the another.

Truth Table:

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CIRCUIT DIAGRAM:

VHDL Code for a Full Adder:

Library ieee;
use ieee.std_logic_1164.all;

entity full_adder is port(a,b,c:in bit; sum,carry:out bit);

end full_adder;

architecture data of full_adder is

begin
sum<= a xor b xor c;
carry <= ((a and b) or (b and c) or (a and c));
end data;

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Waveforms:

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EXPERIMENTS- 8

AIM: Design and Simulation of 4x1 MUX using VHDL program module

SOFTWARE REQUIRED: VHDL

DESCRIPTION:

It is a combinational circuit which have many data inputs and single output depending on
control or select inputs. For N input lines, log n (base2) selection lines, or we can say that for
2n input lines, n selection lines are required. Multiplexers are also known as  “Data n selector,
parallel to serial convertor, many to one circuit, universal logic circuit”. Multiplexers are
mainly used to increase amount of the data that can be sent over the network within certain
amount of time and bandwidth. 

Block Diagram of 4X1 Multiplier

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Logic Diagram:

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VHDL CODE FOR A MULTIPLEXER:

Library ieee;
use ieee.std_logic_1164.all;

entity mux is
port(S1,S0,D0,D1,D2,D3:in bit; Y:out bit);
end mux;

architecture data of mux is

begin
Y<= (not S0 and not S1 and D0) or
(S0 and not S1 and D1) or
(not S0 and S1 and D2) or
(S0 and S1 and D3);
end data;

OUTPUT WAVEFORMS:

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EXPERIMENTS- 8

AIM: Design and Simulation of BCD to Excess-3 code using VHDL program module

SOFTWARE REQUIRED: VHDL

DESCRIPTION: Excess-3 binary code is a unweighted self-complementary BCD code.

BCD digit can be converted to it’s corresponding Excess-3 code by simply adding 3 to it.
Let be the bits representing the binary numbers, where   is the LSB and   is the
MSB, and Let be the bits representing the gray code of the binary numbers, where   is the
LSB and  is the MSB. The truth table for the conversion is given below. The X’s mark don’t
care conditions.

TRUTH TABLE

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LOGIC DIAGRAM:

Corresponding minimized Boolean expressions for Excess-3 code bits –

VHDL CODE FOR BCD to Excess-3 code

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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY bin2ex3 IS
PORT (bin : IN std_logic_vector(3 DOWNTO 0);
ex3 : OUT std_logic_vector(3 DOWNTO 0));
END bin2ex3;
ARCHITECTURE exam OF bin2ex3 IS
BEGIN
WITH bin SELECT
ex3 <= "0011" WHEN "0000",
"0100" WHEN "0001",
"0101" WHEN "0010",
"0110" WHEN "0011",
"0111" WHEN "0100",
"1000" WHEN "0101",
"1001" WHEN "0110",
"1010" WHEN "0111",
"1011" WHEN "1000",
"1100" WHEN "1001",
"1101" WHEN "1010",
"1110" WHEN "1011",
"1111" WHEN "1100",
"0000" WHEN "1101",
"0001" WHEN "1110",
"0010" WHEN OTHERS;
END exam;
OR- 2nd approach
Library IEEE;
use IEEE.std_logic_1164.all;
entity excess is
port(b0,b1,b2,b3:in bit;
e0,e1,e2,e3:out bit);
end excess;
architecture excess_D of excess is
begin
e0 <= (not b0);
e1 <= b1 xor b0;
e2 <= (b1 and (not b2)) or (b0 and (not b2)) or ((not b0) and (not b1) and b2);
e3 <= b1 or (b0 and b2) or (b1 and b2);
end excess_D;

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OUTPUT WAVEFORM:

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BEYOND
SYLLABUS

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EXPERIMENT: - 1

AIM:- Design differentiator and integrator using PSPICE CIRCUIT.

CIRCUIT DIAGRAM:-

INTEGRATOR:

RESULT:

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DIFFERENTIATOR:

RESULT:

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EXPERIMENT: -2

AIM:- Design wein bridge oscillator using PSPICE CIRCUIT:

Part1:  To investigate the magnitude and phase response of the frequency determining
network

Wien bridge network

1. Plot magnitude and phase response of the network circuit against frequency (from
10Hz to 1M Hz)

Here is the simulation setting

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In this laboratory experiment, we need to design the frequency determining network for a
1k Hz sinusoidal oscillator. Therefore, we should set: 
Capacitance = 100nF
Resistance = 1520 ohm

Oscillating frequency: at 1000 Hz

Remark: You may verify the magnitude and phase response at different oscillating
frequencies.

Oscillating frequency:  at 10 Hz

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Oscillating frequency:  at 100Hz

Oscillating frequency:  at 10k Hz

Oscillating frequency:  at 100k Hz

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Oscillating frequency:  at 1M Hz

Part2:     To investigate the performance of oscillator circuit design

Circuit Diagram of Wien bridge oscillator

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Plot output voltage waveform of oscillator:

Here is the simulation setting Output voltage waveform of oscillator with varying the value of
R1:

Set R1 = 2033 ohm  (The loop gain is about to 1, sustained oscillation is resulted.)

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Ser R1=2.1k ohm (The loop gain is greater than 1, overdamping oscillation is resulted.)

Set R1= 1.9k ohm (The loop gain is smaller than 1, underdamping oscillation is resulted.)

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EXPERIMENT: - 3

OBJECT:- Design and simulate of Low-Pass Filter

DESCRIPTION: A Low Pass Filter is a circuit that can be designed to modify, reshape or reject
all unwanted high frequencies of an electrical signal and accept or pass only those signals wanted
by the circuit’s designer. Passive element LPF circuit diagram (basic) is

The Low Pass Filter – the low pass filter only allows low frequency signals from 0Hz to its
cut-off frequency, ƒc point to pass while blocking those any higher.

CIRCUIT DIAGRAM

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OUTPUT WAVEFORM OF LOW PASS FILTER

8.0K

6.0K

4.0K

2.0K

0
100Hz 300Hz 1.0KHz 3.0KHz 10KHz 30KHz 100KHz 300KHz 1.0MHz
V(1) V(1) / V(5)
Frequency

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