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LAB 3 Report

The document provides behavioral descriptions and testbenches for 3 Verilog modules: 1) A 4-to-1 multiplexer with a behavioral description and testbench. 2) A 3-to-8 decoder with a behavioral description and testbench. 3) An 8-to-3 priority encoder with a behavioral description and testbench.

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Suyash Mishra
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168 views10 pages

LAB 3 Report

The document provides behavioral descriptions and testbenches for 3 Verilog modules: 1) A 4-to-1 multiplexer with a behavioral description and testbench. 2) A 3-to-8 decoder with a behavioral description and testbench. 3) An 8-to-3 priority encoder with a behavioral description and testbench.

Uploaded by

Suyash Mishra
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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1.write behavioural description and testbench for 4:1 mux.

module mux_4x1_behav ( a, b, c, d, s0, s1, out);

input a, b, c, d;

input s0, s1;

output reg out;

always @ (a or b or c or d or s0, s1)

begin

case (s0 | s1)

2'b00 : out = a;

2'b01 : out = b;

2'b10 : out = c;

2'b11 : out = d;

endcase

end

endmodule

TESTBENCH:

module mux_4x1_behav_tb();

reg a, b, c, d;

reg s0, s1;

wire out;

integer i;

mux_4x1_behav DUT(a,b,c,d,s0,s1);

initial

begin

for (i=0;i<4;i=i+1)

begin

{s0,s1}=i;
#10;

end

end

initial $monitor("Input a=%b,b=%b,c=%b,d=%b,s0+%b,s1=%b output out=%b", a,b,c,d,s0,s1,out);

initial #100 $finish;

endmodule
2.write behavioural description for 3:8 decoder and verify using test bench.

module decoder3to8(

Data_in,

Data_out

);

input [2:0] Data_in;

output [7:0] Data_out;

reg [7:0] Data_out;

always @(Data_in)

case (Data_in)

3'b000 : Data_out = 8'b00000001;

3'b001 : Data_out = 8'b00000010;

3'b010 : Data_out = 8'b00000100;

3'b011 : Data_out = 8'b00001000;

3'b100 : Data_out = 8'b00010000;

3'b101 : Data_out = 8'b00100000;

3'b110 : Data_out = 8'b01000000;

3'b111 : Data_out = 8'b10000000;

default : Data_out = 8'b00000000;

endcase

endmodule
TESTBENCH:

module tb_decoder;

reg [2:0] Data_in;

wire [7:0] Data_out;

decoder3to8 uut (

.Data_in(Data_in),

.Data_out(Data_out)

);

initial begin

Data_in = 3'b000; #100;

Data_in = 3'b001; #100;

Data_in = 3'b010; #100;

Data_in = 3'b011; #100;

Data_in = 3'b100; #100;

Data_in = 3'b101; #100;

Data_in = 3'b110; #100;

Data_in = 3'b111; #100;

end

endmodule
3. Write an behavioural description and testbench 8:3 priority encoder.

module prienc8x3_behav(I,y,valid);

input [7:0]I;

output [2:0]y;

output valid;

always @(I)

begin

if(I[7]==1'b1) begin

y=3'b111;

valid=1'b1;

end

elseif (I[6]==1'b1) begin

y=3'b110;

valid=1'b1;

end

elseif (I[5]==1'b1) begin

y=3'b101;

valid=1'b1;

end

elseif (I[4]==1'b1) begin

y=3'b100;

valid=1'b1;

end

elseif (I[3]==1'b1) begin

y=3'b011;

valid=1'b1;

end

elseif (I[2]==1'b1) begin

y=3'b010;

valid=1'b1;

end
elseif (I[1]==1'b1) begin

y=3'b001;

valid=1'b1;

end

elseif (I[0]==1'b1) begin

y=3'b000;

valid=1'b1;

end

else

begin

y=3'bz;

valid=1'b0;

end

endmodule

TESTBENCH:

module prienc8x3_behav_tb();

reg [7:0]I;

wire [2:0]y;

wire valid;

prienc8x3_behav DUT(I,y,valid);

task init;

begin

I=0;

end

endtask

task prienc_inp(input [7:0]i);

begin

I=i;

end

endtask
task delay;

begin

#10;

end

endtask

initial

begin

initialize;

prienc_inp(8'b10000100);

delay;

prienc_inp(8'b11100010);

delay;

end

initial

$monitor("input I=%b, output y=%b",I,y);

Endmodule

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