NB671

24V, High Current

Synchronous Step-down Converter
The Future of Analog IC Technology

DESCRIPTION FEATURES
The NB671 is a fully integrated high frequency • Wide 5V to 24V Operating Input Range
synchronous rectified step-down switch mode • 6A Continuous Output Current
converter. It offers very compact solutions to • 9A Peak Output Current
achieve 6A continuous output current and 9A • Low RDS(ON) Internal Power MOSFETs
peak current over a wide input supply range • Proprietary Switching Loss Reduction
with excellent load and line regulation. The Technique
NB671 operates at high efficiency over a wide • 1% Reference Voltage
output current load range. • 1.7ms Internal Soft Start
Constant-On-Time (COT) control mode • Output Discharge
provides fast transient response and eases loop • 500kHZ Switching Frequency
stabilization. • OCP, OVP, UVP Protection and Thermal
Under voltage lockout is internally set as 4.6V, Shutdown
An open drain power good signal indicates the • Output Adjustable from 0.604V to 5.5V
output is within its nominal voltage range. APPLICATIONS
Full protection features include OCP, OVP, and • Laptop Computer
thermal shut down. • Tablet PC
The converter requires minimum number of • Networking Systems
external components and is available in QFN16 • Personal Video Recorders
(3mmx3mm) package. • Flat Panel Television and Monitors
• Distributed Power Systems
All MPS parts are lead-free and adhere to the RoHS directive. For MPS green
status, please visit MPS website under Products, Quality Assurance page.
“MPS” and “The Future of Analog IC Technology” are registered trademarks of
Monolithic Power Systems, Inc.

TYPICAL APPLICATION

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 NB671, 24V, HIGH CURRENT SYNCHRONOUS STEP-DOWN CONVERTER

ORDERING INFORMATION
Part Number* Package Top Marking
NB671GQ QFN16 (3x3mm) AEA

* For Tape & Reel, add suffix –Z (e.g. NB671GQ–Z)

PACKAGE REFERENCE
TOP VIEW

(5)
ABSOLUTE MAXIMUM RATINGS (1) Thermal Resistance θJA θJC
Supply Voltage VIN ....................................... 24V QFN16 (3mmx3mm) ...............70 ...... 15 ... °C/W
VSW ...............................................-0.3V to 24.3V Notes:
VSW (30ns)..........................................-3V to 28V 1) Exceeding these ratings may damage the device.
VSW (5ns)............................................-6V to 28V 2) Refer to “Configuring the EN Control”.
3) The maximum allowable power dissipation is a function of the
VBST ................................................... VSW + 5.5V maximum junction temperature TJ(MAX), the junction-to-
VEN ............................................................... 12V ambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
Enable Current IEN(2)................................ 2.5mA any ambient temperature is calculated by PD(MAX)=(TJ(MAX)-
All Other Pins ..............................–0.3V to +5.5V TA)/θJA. Exceeding the maximum allowable power dissipation
(3) will cause excessive die temperature, and the regulator will go
Continuous Power Dissipation (TA=+25°) into thermal shutdown. Internal thermal shutdown circuitry
QFN16...……………………….…..…………1.8W protects the device from permanent damage.
4) The device is not guaranteed to function outside of its
Junction Temperature ...............................150°C operating conditions.
Lead Temperature ....................................260°C 5) Measured on JESD51-7, 4-layer PCB.
Storage Temperature............... -65°C to +150°C
(4)
Recommended Operating Conditions
Supply Voltage VIN ..............................5V to 22V
Output Voltage VOUT ....................0.604V to 5.5V
Enable Current IEN...................................... 1mA
Operating Junction Temp. (TJ). -40°C to +125°C

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ELECTRICAL CHARACTERISTICS
VIN = 12V, TJ = 25°C, unless otherwise noted.
Parameters Symbol Condition Min Typ Max Units
Supply Current
Supply Current (Shutdown) IIN VEN = 0V 0 1 μA
Supply Current (Quiescent) IIN VEN = 2V, VFB = 0.65V 100 160 200 μA
MOSFET
High-side Switch On Resistance HSRDS-ON 30 mΩ
Low-side Switch On Resistance LSRDS-ON 15 mΩ
Switch Leakage SWLKG VEN = 0V, VSW = 0V 0 1 μA

Current Limit

Low-side Valley Current Limit ILIMIT 8 8.5 9.5 A

Switching frequency and minimum off timer
Switching frequency FS 400 500 600 kHz
Minimum Off Time(6) TOFF 250 300 350 ns
Over-voltage and Under-voltage Protection
OVP Threshold VOVP 125% 130% 135% VREF
OVP Delay TOVPDEL 2.5 μs
UVP Threshold VUVP 55% 60% 65% VREF
UVP Delay TUVPDEL 12 μs
Reference And Soft Start
Reference Voltage VREF 598 604 610 mV
Feedback Current IFB VFB = 0.604V 10 50 nA
Soft Start Time TSS 1.5 1.7 1.95 ms
Enable And UVLO
Enable Input Low Voltage VILEN 1.15 1.25 1.35 V
Enable Hysteresis VEN-HYS 100 mV
VEN = 2V 5
Enable Input Current IEN μA
VEN = 0V 0
VCC Under Voltage Lockout
VCCVth 4.6 4.85 V
Threshold Rising
VCC Under Voltage Lockout
VCCHYS 480 mV
Threshold Hysteresis

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ELECTRICAL CHARACTERISTICS (continued)

VIN = 12V, TJ = 25°C, unless otherwise noted.
Parameters Symbol Condition Min Typ Max Units
VCC Regulator
VCC Regulator VCC 4.8 5.1 5.3 V
VCC Load Regulation Icc=5mA 5 %

Power Good

FB Rising (Good) PGVth-Hi 95

FB Falling (Fault) PGVth-Lo 85
%VREF
FB Rising (Fault) PGVth-Hi 115
FB Falling (Good) PGVth-Lo 105
Power Good Lower to High Delay PGTd 0.5 ms
Power Good Sink Current
VPG Sink 4mA 0.4 V
Capability
Power Good Leakage Current IPG_LEAK VPG = 3.3V 12 μA
Thermal Protection
Thermal Shutdown(6) TSD 135 150 °C
Thermal Shutdown Hysteresis(6) 25 °C
Note:
6) Guaranteed by design.

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PIN FUNCTIONS
PIN # Name Description
Supply Voltage. The IN pin supplies power for internal MOSFET and regulator. The
NB671 operate from a +5V to +22V input rail. An input capacitor is needed to
1 VIN
decouple the input rail. Use wide PCB traces and multiple vias to make the
connection.
2 PGND Power Ground. Use wide PCB traces and multiple vias to make the connection
Power good output, the output of this pin is an open drain signal and is high if the
4 PG output voltage is higher than 95% of the nominal voltage. There is a delay from FB ≥
95% to PGOOD goes high.
3, 5, 6 NC
VOUT pin is used to sense the output voltage of the Buck regulator, connect this pin
7 VOUT
to the output capacitor of the regulator directly.
Switch Output. Connect this pin to the inductor and bootstrap capacitor. This pin is
driven up to the VIN voltage by the high-side switch during the on-time of the PWM
8,9
duty cycle. The inductor current drives the SW pin negative during the off-time. The
Exposed SW
on-resistance of the low-side switch and the internal diode fixes the negative
Pad 15, 16
voltage. Use wide and short PCB traces to make the connection. Try to minimize the
area of the SW pattern.
Bootstrap. A capacitor connected between SW and BS pins is required to form a
10 BST
floating supply across the high-side switch driver.
Internal 5V LDO output. The driver and control circuits are powered from this
voltage. Decouple with a minimum 1µF ceramic capacitor as close to the pin as
11 VCC
possible. X7R or X5R grade dielectric ceramic capacitors are recommended for their
stable temperature characteristics.
Feedback. An external resistor divider from the output to GND, tapped to the FB pin,
sets the output voltage. It is recommended to place the resistor divider as close to
12 FB
FB pin as possible. Vias should be avoided on the FB traces. It is recommended to
set the current through FB resistors around 10uA.
Enable pin. EN is a digital input that turns the regulator on or off. Drive EN high to
13 EN turn on the regulator, drive it low to turn it off. Connect EN with VIN through a pull-up
resistor or a resistive voltage divider for automatic startup. Do not float this pin.
Analog ground. The internal reference is referred to AGND. Connect the GND of the
14 AGND
FB divider resistor to AGND for better load regulation.

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TYPICAL PERFORMANCE CHARACTERISTICS

Performance waveforms are tested on the evaluation board of the Design Example section.
VIN=19V, VOUT =1.05V, L=1.2µH, TJ=+25°C, unless otherwise noted.

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)

Performance waveforms are tested on the evaluation board of the Design Example section.
VIN=19V, VOUT =1.05V, L=1.2µH, TJ=+25°C, unless otherwise noted.

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 NB671, 24V, HIGH CURRENT SYNCHRONOUS STEP-DOWN CONVERTER

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

Performance waveforms are tested on the evaluation board of the Design Example section.
VIN=19V, VOUT =1.05V, L=1.2µH, TJ=+25°C, unless otherwise noted.

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BLOCK DIAGRAM

Figure 1—Functional Block Diagram

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OPERATION
PWM Operation When the output current is high and the inductor
current is always above zero amps, it is called
The NB671 is fully integrated synchronous
continuous-conduction-mode (CCM). The CCM
rectified step-down switch mode converter.
mode operation is shown in Figure 2 shown.
Constant-on-time (COT) control is employed to
When VFB is below VREF, HS-MOSFET is turned
provide fast transient response and easy loop
on for a fixed interval which is determined by
stabilization. At the beginning of each cycle, the
one- shot on-timer as equation 1 shown. When
high-side MOSFET (HS-FET) is turned ON when
the HS-MOSFET is turned off, the LS-MOSFET
the feedback voltage (VFB) is below the
is turned on until next period.
reference voltage (VREF), which indicates
insufficient output voltage. The ON period is In CCM mode operation, the switching frequency
determined by both the output voltage and input is fairly constant and it is called PWM mode.
voltage to make the switching frequency fairy
Light-Load Operation
constant over input voltage range.
With the load decrease, the inductor current
After the ON period elapses, the HS-FET is decrease too. Once the inductor current touch
turned off, or becomes OFF state. It is turned ON zero, the operation is transition from continuous-
again when VFB drops below VREF. By conduction-mode (CCM) to discontinuous-
repeating operation this way, the converter conduction-mode (DCM).
regulates the output voltage. The integrated low-
side MOSFET (LS-FET) is turned on when the The light load operation is shown in Figure 3.
HS-FET is in its OFF state to minimize the When VFB is below VREF, HS-MOSFET is turned
conduction loss. There will be a dead short on for a fixed interval which is determined by
between input and GND if both HS-FET and LS- one- shot on-timer as equation 1 shown. When
FET are turned on at the same time. It’s called the HS-MOSFET is turned off, the LS-MOSFET
shoot-through. In order to avoid shoot-through, a is turned on until the inductor current reaches
dead-time (DT) is internally generated between zero. In DCM operation, the VFB does not reach
HS-FET off and LS-FET on, or LS-FET off and VREF when the inductor current is approaching
HS-FET on. zero. The LS-FET driver turns into tri-state (high
Z) whenever the inductor current reaches zero. A
An internal compensation is applied for COT current modulator takes over the control of LS-
control to make a more stable operation even FET and limits the inductor current to less than -
when ceramic capacitors are used as output 1mA. Hence, the output capacitors discharge
capacitors, this internal compensation will then slowly to GND through LS-FET. As a result, the
improve the jitter performance without affect the efficiency at light load condition is greatly
line or load regulation. improved. At light load condition, the HS-FET is
Heavy-Load Operation not turned ON as frequently as at heavy load
condition. This is called skip mode.
At light load or no load condition, the output
drops very slowly and the NB671 reduces the
switching frequency naturally and then high
efficiency is achieved at light load.

Figure 2—Heavy Load Operation

Figure 3—Light Load Operation

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 NB671, 24V, HIGH CURRENT SYNCHRONOUS STEP-DOWN CONVERTER

As the output current increases from the light

resistor. Ceramic capacitors usually can not be
load condition, the time period within which the
used as output capacitor.
current modulator regulates becomes shorter.
The HS-FET is turned ON more frequently. To realize the stability, the ESR value should be
Hence, the switching frequency increases chosen as follow:
correspondingly. The output current reaches the
TSW T
critical level when the current modulator time is + ON
zero. The critical level of the output current is RESR ≥ 0.7 × π 2 (2)
determined as follows: COUT
TSW is the switching period.
(VIN − VOUT ) × VOUT
IOUT = (1)
2 × L × FSW × VIN The NB671 has built in internal ramp
compensation to make sure the system is stable
It turns into PWM mode once the output current even without the help of output capacitor’s ESR;
exceeds the critical level. After that, the switching and thus the pure ceramic capacitor solution can
frequency stays fairly constant over the output be applicant. The pure ceramic capacitor solution
current range. can significantly reduce the output ripple, total
Jitter and FB Ramp Slope BOM cost and the board area.
Jitter occurs in both PWM and skip modes when Figure 6 shows a typical output circuit in PWM
noise in the VFB ripple propagates a delay to the mode without an external ramp circuit. Turn to
HS-FET driver, as shown in Figures 4 and 5. application information section for design steps
Jitter can affect system stability, with noise without external compensation.
immunity proportional to the steepness of VFB’s
downward slope. However, VFB ripple does not
directly affect noise immunity.
VNOISE V SLO PE1

V FB

V R EF

H S D river

Jitter Figure 6—Simplified Circuit in PWM Mode

without External Ramp Compensation
Figure 4—Jitter in PWM Mode
When using a large-ESR capacitor on the output,
VNOISE
V SLO PE2 add a ceramic capacitor with a value of 10uF or
V FB
less to in parallel to minimize the effect of ESL.
V REF Operating with external ramp compensation
The NB671 is usually able to support ceramic
output capacitors without external ramp, however,
H S D river
in some of the cases, the internal ramp may not
Jitter be enough to stabilize the system, and external
ramp compensation is needed. Skip to
Figure 5—Jitter in Skip Mode application information section for design steps
Operating without external ramp with external ramp compensation.

The traditional constant-on-time control scheme

is intrinsically unstable if output capacitor’s ESR
is not large enough as an effective current-sense

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 NB671, 24V, HIGH CURRENT SYNCHRONOUS STEP-DOWN CONVERTER

Vo

R1 ESR
FB
Ro
Cout
R2

Figure 7—Simplified Circuit in PWM Mode

with External Ramp Compensation Figure 8—Simplified Circuit in skip Mode
Figure 7 shows a simplified external ramp The downward slope of the VFB ripple in skip
compensation (R4 and C4) for PWM mode, with mode can be determined as follow:
HS-FET off. Chose R1, R2, R9 and C4 of the − VREF
external ramp to meet the following condition: VSLOPE2 = (8)
((R1 + R2 ) // Ro) × COUT
1 1 ⎛ R1 × R 2 ⎞ Where Ro is the equivalent load resistor.
< ×⎜ + R9 ⎟ (3)
2π × FSW × C4 5 ⎝ R1 + R 2 ⎠ As described in Figure 5, VSLOPE2 in the skip
Where: mode is lower than that is in the PWM mode, so
it is reasonable that the jitter in the skip mode is
IR4 = IC4 + IFB ≈ IC4 (4) larger. If one wants a system with less jitter
during light load condition, the values of the VFB
And the Vramp on the VFB can then be estimated resistors should not be too big, however, that will
as: decrease the light load efficiency.
VIN − VOUT R1 // R2 (5) Configuring the EN Control
VRAMP = × TON ×
R 4 × C4 R1 // R2 + R9 EN is used to enable or disable the whole chip.
Pull En high to turn on the regulator and pull EN
The downward slope of the VFB ripple then
low to turn it off. Do not float the pin.
follows
For automatic start-up the EN pin can be pulled
− VRAMP − VOUT (6)
VSLOPE1 = = up to input voltage through a resistive voltage
Toff R 4 × C4 divider. Choose the values of the pull-up resistor
As can be seen from equation 6, if there is (Rup from Vin pin to EN pin) and the pull-down
instability in PWM mode, we can reduce either resistor (Rdown from EN pin to GND) to
R4 or C4. If C4 can not be reduced further due to determine the automatic start-up voltage:
limitation from equation 3, then we can only (Rup + Rdown )
reduce R4. For a stable PWM operation, the VIN−START = 1.35 × (V) (9)
Vslope1 should be design follow equation 7.
Rdown

TSW T For example, for Rup=150kΩ and

+ ON -RESRCOUT Rdown=51kΩ,the VIN−START is set at 5.32V.
Io × 10-3
-Vslope1 ≥ 0.7 × π 2 VOUT + (7)
2 × L × COUT TSW -Ton To avoid noise, a 10nF ceramic capacitor from
EN to GND is recommended.
Io is the load current.
There is an internal Zener diode on the EN pin,
In skip mode, the downward slope of the VFB which clamps the EN pin voltage to prevent it
ripple is the same whether the external ramp is from running away. The maximum pull up current
used or not. Figure 8 shows the simplified circuit assuming a worst case 12V internal Zener clamp
of the skip mode when both the HS-FET and LS- should be less than 1mA.
FET are off.

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 NB671, 24V, HIGH CURRENT SYNCHRONOUS STEP-DOWN CONVERTER

Therefore, when EN is driven by an external logic Over Current Protection

signal, the EN voltage should be lower than 12V;
when EN is connected with VIN through a pull-up NB671 has cycle-by-cycle over current limiting
resistor or a resistive voltage divider, the control. The current-limit circuit employs a
resistance selection should ensure the maximum "valley" current-sensing algorithm. The part uses
pull up current less than 1mA. the Rds(on) of the low side MOSFET as a
current-sensing element. If the magnitude of the
If using a resistive voltage divider and VIN higher current-sense signal is above the current-limit
than 12V, the allowed minimum pull-up resistor threshold, the PWM is not allowed to initiate a
Rup should meet the following equation: new cycle.
VIN -12V 12V The trip level is fixed internally. The inductor
- =1mA (10)
Rup Rdown current is monitored by the voltage between GND
Especially, just using the pull-up resistor Rup(the pin and SW pin. GND is used as the positive
pull-down resistor is not connected), the current sensing node so that GND should be
connected to the source terminal of the bottom
VIN-START is determined by input UVLO, and the
MOSFET.
minimum resistor value is:
Since the comparison is done during the high
V -12V
Rup = IN (W) (11) side MOSFET OFF and low side MOSFET ON
1mA state, the OC trip level sets the valley level of the
A typical pull-up resistor is 499kΩ. inductor current. Thus, the load current at over-
Soft Start current threshold, IOC, can be calculated as
The NB671 employs soft start (SS) mechanism follows:
to ensure smooth output during power-up. When ΔIinductor
the EN pin becomes high, the internal reference IOC = I _ limit + (12)
2
voltage ramps up gradually; hence, the output
voltage ramps up smoothly, as well. Once the In an over-current condition, the current to the
reference voltage reaches the target value, the load exceeds the current to the output capacitor;
soft start finishes and it enters into steady state thus the output voltage tends to fall off.
operation. Eventually, it will end up with crossing the under
voltage protection threshold and shutdown.
If the output is pre-biased to a certain voltage
during startup, the IC will disable the switching of Over/Under-Voltage Protection (OVP/UVP)
both high-side and low-side switches until the NB671 monitors a resistor divided feedback
voltage on the internal reference exceeds the voltage to detect over and under voltage. When
sensed output voltage at the FB node. the feedback voltage becomes higher than 115%
Power Good (PGOOD) of the target voltage, the controller will enter
Dynamic Regulation Period. During this period,
The NB671 has power-good (PGOOD) output the LS will off when the LS current goes to -1A,
used to indicate whether the output voltage of the this will then discharge the output and try to keep
Buck regulator is ready or not. The PGOOD pin it within the normal range. If the dynamic
is the open drain of a MOSFET. It should be regulation can not limit the increasing of the Vo,
connected to VCC or other voltage source through once the feedback voltage becomes higher than
a resistor (e.g. 100k). After the input voltage is 130% of the feedback voltage, the OVP
applied, the MOSFET is turned on so that the comparator output goes high and the circuit
PGOOD pin is pulled to GND before SS is ready. latches as the high-side MOSFET driver OFF
After FB voltage reaches 95% of REF voltage, and the low-side MOSFET turns on acting as an -
the PGOOD pin is pulled high after a delay. The 1A current source.
PGOOD delay time is 0.5ms.
When the feedback voltage becomes lower than
When the FB voltage drops to 85% of REF 60% of the target voltage, the UVP comparator
voltage, the PGOOD pin will be pulled low. output goes high if the UV still occurs after typical

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 NB671, 24V, HIGH CURRENT SYNCHRONOUS STEP-DOWN CONVERTER

12μs delay; then the fault latch will be triggered--- Thermal Shutdown
latches HS off and LS on; the LS FET keeps on Thermal shutdown is employed in the NB671.
until the inductor current goes zero. The junction temperature of the IC is internally
UVLO Protection monitored. If the junction temperature exceeds
The NB671 has under-voltage lock-out protection the threshold value (typical 150ºC), the converter
(UVLO). When the VCC voltage is higher than shuts off. This is a non-latch protection. There is
the UVLO rising threshold voltage, the part will about 25ºC hysteresis. Once the junction
be powered up. It shuts off when the VIN voltage temperature drops to about 125ºC, it initiates a
is lower than the UVLO falling threshold voltage. SS.
This is non-latch protection. The part is disabled Output Discharge
when the VCC voltage falls below 4.6V. If an NB671 discharges the output when EN is low, or
application requires a higher under-voltage the controller is turned off by the protection
lockout (UVLO), use the EN pin as shown in functions (UVP & OCP, OCP, OVP, UVLO, and
Figure 9 to adjust the input voltage UVLO by thermal shutdown). The part discharges outputs
using two external resistors. It is recommended using an internal 6Ω MOSFET which is
to use the enable resistors to set the UVLO connected to VOUT and GND. The external low-
falling threshold (VSTOP) above 4.6V. The rising side MOSFET is not turned on for the output
threshold (VSTART) should be set to provide discharge operation to avoid the possibility of
enough hysteresis to allow for any input supply causing negative voltage at the output.
variations.

Figure 9—Adjustable UVLO

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APPLICATION INFORMATION
Setting the Output Voltage---without external through resistor R4 and capacitor C4.The output
compensation voltage is influenced by ramp voltage VRAMP
For applications that electrolytic capacitor or POS besides R divider as shown in Figure 11. The
capacitor with a controlled output of ESR is set VRAMP can be calculated as shown in equation 7.
as output capacitors, or the internal R2 should be chosen reasonably, a small R2 will
compensation is enough for a stable operation lead to considerable quiescent current loss while
when ceramic capacitors is used, then the too large R2 makes the FB noise sensitive. It is
external compensation is not need.. The output recommended to choose a value within 5kΩ-
voltage is set by feedback resistors R1 and R2. 100kΩ for R2.Typically, set the current through
As Figure 10 shows. R2 between 5-30uA will make a good balance
between system stability and also the no load
loss. And the value of R1 then is determined as
follow:
R2 (14)
R= 1
VFB(AVG) R2
-
(VOUT -VFB(AVG) ) R4 +R9
The VFB(AVG) is the average value on the FB,
VFB(AVG) varies with the Vin, Vo, and load
Figure10—Simplified Circuit of POS Capacitor condition, etc., its value on the skip mode would
First, choose a value for R2. R2 should be be lower than that of the PWM mode, which
chosen reasonably, a small R2 will lead to means the load regulation is strictly related to the
considerable quiescent current loss while too VFB(AVG). Also the line regulation is related to the
large R2 makes the FB noise sensitive. It is VFB(AVG). If one wants to gets a better load or line
recommended to choose a value within 5kΩ- regulation, a lower Vramp is suggested, as long
100kΩ for R2,.Typically, set the current through as the criterion shown in equation 8 can be met.
R2 between 5-30uA will make a good balance For PWM operation, VFB(AVG) value can be
between system stability and also the no load deduced from the equation below.
loss. Then R1 is determined as follow with the
1 R1 //R2
output ripple considered: VFB(AVG) = VREF + VRAMP × (15)
1 2 R1 //R2 + R9
VOUT − ΔVOUT − VREF Usually, R9 is set to 0Ω, and it can also be set
R1 = 2 ⋅ R2 (13)
VREF following equation 14 for a better noise immunity.
It should also set to be 5 times smaller than
ΔVOUT is the output ripple.
R1//R2 to minimize its influence on Vramp.
Setting the Output Voltage---with external
1
compensation R9 = (16)
2π× C4 × 2FSW
Using equation 13 to calculate the R1 can be
complicated. To simplify the calculation, a DC-
blocking capacitor Cdc can be added to filter the
DC influence from R4 and R9. Figure 12 shows
a simplified circuit with external ramp
compensation and a DC-blocking capacitor. With
this capacitor, R1 can easily be obtained by
Figure11—Simplified Circuit of Ceramic
Capacitor
If the system is not stable enough when low ESR
ceramic capacitor is used in the output, an
external voltage ramp should be added to FB

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using the simplified equation for PWM mode IOUT

operation: ICIN = (19)
2
1
(VOUT − VREF − VRAMP )
2 (17) For simplification, choose the input capacitor with
R1 = R2
1 an RMS current rating greater than half of the
VREF + VRAMP maximum load current.
2
Cdc is suggested to be at least 10 times larger The input capacitance value determines the input
than C4 for better DC blocking performance, and voltage ripple of the converter. If there is an input
should also not larger than 0.47uF considering voltage ripple requirement in the system, choose
start up performance. In case one wants to use the input capacitor that meets the specification.
larger Cdc for a better FB noise immunity,
combined with reduced R1 and R2 to limit the The input voltage ripple can be estimated as
Cdc in a reasonable value without affecting the follows:
system start up. Be noted that even when the IOUT V V
Cdc is applied, the load and line regulation are ΔVIN = × OUT × (1 − OUT ) (20)
still Vramp related. FSW × CIN VIN VIN
Under worst-case conditions where VIN = 2VOUT:
1 IOUT
ΔVIN = × (21)
4 FSW × CIN
Output Capacitor
The output capacitor is required to maintain the
DC output voltage. Ceramic or POSCAP
capacitors are recommended. The output voltage
Figure12—Simplified Circuit of Ceramic ripple can be estimated as:
Capacitor with DC blocking capacitor
VOUT V 1
Input Capacitor ΔVOUT = × (1 − OUT ) × (RESR + ) (22)
FSW × L VIN 8 × FSW × COUT
The input current to the step-down converter is
In the case of ceramic capacitors, the impedance
discontinuous and therefore requires a capacitor
at the switching frequency is dominated by the
to supply the AC current to the step-down
capacitance. The output voltage ripple is mainly
converter while maintaining the DC input voltage.
caused by the capacitance. For simplification, the
Ceramic capacitors are recommended for best
output voltage ripple can be estimated as:
performance and should be placed as close to
the VIN pin as possible. Capacitors with X5R and VOUT V (23)
ΔVOUT = × (1 − OUT )
X7R ceramic dielectrics are recommended 8 × FSW × L × COUT
2
VIN
because they are fairly stable with temperature
fluctuations. The output voltage ripple caused by ESR is very
small. Therefore, an external ramp is needed to
The capacitors must also have a ripple current stabilize the system. The external ramp can be
rating greater than the maximum input ripple generated through resistor R4 and capacitor C4.
current of the converter. The input ripple current
can be estimated as follows: In the case of POSCAP capacitors, the ESR
dominates the impedance at the switching
VOUT V frequency. The ramp voltage generated from the
ICIN = IOUT × × (1 − OUT ) (18)
VIN VIN ESR is high enough to stabilize the system.
Therefore, an external ramp is not needed. A
The worst-case condition occurs at VIN = 2VOUT, minimum ESR value around 12mΩ is required to
where: ensure stable operation of the converter. For

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simplification, the output ripple can be PCB Layout Guide

approximated as:
1. The high current paths (GND, IN, and SW)
VOUT V should be placed very close to the device
ΔVOUT = × (1 − OUT ) × RESR (24) with short, direct and wide traces.
FSW × L VIN
2. Put the input capacitors as close to the IN
Maximum output capacitor limitation should be and GND pins as possible.
also considered in design application. NB671 has 3. Put the decoupling capacitor as close to the
an around 1.7ms soft-start time period. If the VCC and GND pins as possible. Place the
output capacitor value is too high, the output Cap close to AGND if the distance is long.
voltage can’t reach the design value during the And place >3 Vias if via is required to reduce
soft-start time, and then it will fail to regulate. The the leakage inductance.
maximum output capacitor value Co_max can be
4. Keep the switching node SW short and away
limited approximately by:
from the feedback network.
CO _ MAX = (ILIM _ AVG − IOUT ) × Tss / VOUT (25) 5. The external feedback resistors should be
placed next to the FB pin. Make sure that
Where, ILIM_AVG is the average start-up current there is no via on the FB trace.
during soft-start period. Tss is the soft-start time.
6. Keep the BST voltage path (BST, C3, and
Inductor SW) as short as possible.
The inductor is necessary to supply constant 7. Keep the IN and GND pads connected with
current to the output load while being driven by large copper and use at least two layers for
the switched input voltage. A larger-value IN and GND trace to achieve better thermal
inductor will result in less ripple current that will performance. Also, add several Vias with
result in lower output ripple voltage. However, a 10mil_drill/18mil_copper_width close to the
larger-value inductor will have a larger physical IN and GND pads to help on thermal
footprint, higher series resistance, and/or lower dissipation.
saturation current. A good rule for determining 8. Four-layer layout is strongly recommended to
the inductance value is to design the peak-to- achieve better thermal performance.
peak ripple current in the inductor to be in the Note:
range of 30% to 40% of the maximum output
current, and that the peak inductor current is Please refer to the PCB Layout Application Note
below the maximum switch current limit. The for more details.
inductance value can be calculated by:
VOUT V (26)
L= × (1 − OUT )
FSW × ΔIL VIN

Where ΔIL is the peak-to-peak inductor ripple

current.
The inductor should not saturate under the
maximum inductor peak current, where the peak
inductor current can be calculated by:
VOUT V
ILP = IOUT + × (1 − OUT ) (27)
2FSW × L VIN

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Figure 13—Recommend Layout

Recommend Design Example The detailed application schematic is shown in
Figure 14 when low ESR caps are used. The
Two design examples are provided below when
typical performance and circuit waveforms have
the ceramic capacitors are applied:
been shown in the Typical Performance
Table 1—Design Example Characteristics section. For more possible
VOUT Cout L R4 C4 R9 R1 R2 applications of this device, please refer to related
(V) (F) (μH) (Ω) (F) (kΩ) (kΩ) (kΩ) Evaluation Board Data Sheets.
1.05 22μx2+47μ 1.2 1M 220p 499 63.4 82
5.0 22μx3 2 1M 220p 499 150 18

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 NB671, 24V, HIGH CURRENT SYNCHRONOUS STEP-DOWN CONVERTER

TYPICAL APPLICATION

Figure 14 — Typical Application Circuit with Low ESR Ceramic Output Capacitor
VIN=6.5-22V, VOUT=1.05V, IOUT=6A

Figure 15 — Typical Application Circuit with Low ESR Ceramic Output Capacitor
VIN=7-22V, VOUT=5V, IOUT=6A

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 NB671, 24V, HIGH CURRENT SYNCHRONOUS STEP-DOWN CONVERTER

PACKAGE INFORMATION
QFN16 (3X3mm)

PIN 1 ID
MARKING PIN 1 ID
0.10x45癟 YP.

PIN 1 ID
INDEX AREA

TOP VIEW BOTTOM VIEW

SIDE VIEW

NOTE:

1) ALL DIMENSIONS ARE IN MILLIMETERS.

0.10x45° 2) EXPOSED PADDLE SIZE DOES NOT INCLUDE
MOLD FLASH.
3) LEAD COPLANARITY SHALL BE 0.10
MILLIMETERS MAX.
4) JEDEC REFERENCE IS MO-220.
5) DRAWING IS NOT TO SCALE.

RECOMMENDED LAND PATTERN

NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.

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