ENUGU STATE UNIVERSITY OF SCIENCE & TECHNOLOGY

(ESUT)

FACULTY OF APPLIED NATURAL SCIENCES (FANS)

DEPARTMENT OF COMPUTER SCIENCE (CSC)

ASSIGNMENT
BY

GROUP A
ON

ASSEMBLY LANGUAGE

CSC 353

LECTURER: Mr. Olofin B.

DATE: 20TH MARCH, 2017

 GROUP A PARTICIPANTS

S/N NAME REG NUMBER

01 UGWUAMOKE NNENNA ESUT/2014/147420
02 NEBO LOVETH UKAMAKA ESUT/2014/147424
03 IHEJIETO EMELDA ESUT/2015030173969
04 NNAMANI VIVIAN ESUT/2014/147430
05 OGBODO CHUKWUMA A. ESUT/2014/147445
06 OKAFOR TOCHUKWU ESUT/2014/147448
07 ONYEGWU CHRISTIAN ESUT/2014/147438
08 NWIYI CHIDUBEM ESUT/2014/147441
09 OBI BLESSING ESUT/2014/147418
10 MMUO OGECHUKWU ESUT/2014/147416
11 OKECHUKWU GODSWILL ESUT/2014/147423
12 ONU BENJAMIN UCHE ESUT/2014/147427
13 ONUGHA CHINONSO ESUT/2014/147456
14 EMERIKE ADAEZE ESUT/2014/147455
15 NWATU SABASTINE O. ESUT/2014/147436
16 NWAFOR CHUKWUEBUKA ESUT/2014/147433
17 EZE KENNETH KENECHUKWU ESUT/2014/147454
18 NNADI HENRY ESUT/2014/147440
19 AGBO IKECHUKWU ESUT/2014/147450
20 CHIBULU CHUKWUEBUKA ESUT/2014/147422
21 ANIKWE BENJAMIN ESUT/2014/147453
22 CHUKWUMAIFE PRAISE ESUT/2014/147437
23 NWOBODO MICHAEL EMMANUEL ESUT/2014/147447
24 EZE KINGSLEY CHIBUEZE ESUT/2014/147442
25 ASOGWA KELECHI ESUT/2014/147425
26 ANI DANIEL CHUKWUEMEKA ESUT/2014/147451
27 AKERU ZIKORA IVAN A. ESUT/2014/147446
28 NWOBODO CHUKWUNONSO KINGSLEY ESUT/2014/155190
29 NWATU FIDELIS IFENNA ESUT/2014/155191
30 OKEANONIFE NEBOLISA ESUT/2014/147421
31 IGBANI POSSIBLE C. ESUT/2014/147432
32 NDU CHINWEOKWU C. ESUT/2014/147419
33 ITUMO JENNIFER OLUCHUKWU ESUT/2014/147417
34 ABAGHA EMMANUEL CHIMDI ESUT/2014/147449
35 IKE ELVIS VICTOR ESUT/2014/147457
36 OZOR UGONNA KENNETH ESUT/2014/147439
37 ODUNZE EBUKA HENRY ESUT/2014/147429
38 AMADI CHISOM ESUT/2014/155202
39
40
41
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43
44

GROUP LEADER: AKERU ZIKORA IVAN A.

ASSIGNMENTS:
1. PAGE 142
2. PAGE 190 QUESTIONS 1 - 8
1. What 3 components make up a Von Neumann Machine?
 CPU
 MEMORY
 INPUT/OUTPUT
2. What is the purpose of the (a)system bus (b) address bus (c) data bus (d) control bus
 System bus: It is the electronic pathway that connects the various components of a
Von Neumann Machine.
 Address bus: This is the bus that is used to send the address of a memory location
the CPU wishes to write/store to or read/retrieve data from.
 Data bus: Is used to shuffle data between various components of a Von Neumann
Machine.
 Control bus: This bus is used to transfer signals which control how the processor
communicates with the rest of the system.

3. Which bus defines the “size” of the processor?

The data bus defines the “size” of the processor.

4. Which bus controls how much memory you can have?

The address bus controls how much memory you can have.

5. Does the size of the data bus control the maximum value the CPU can process? Explain.
No. The size of the data bus only determines how much data can be transferred over the
bus at any instant but that won’t stop for example, a 32 bit CPU from using 4 memory reads
on an 8 bit data bus to get its full 32 bits required for an operation.

6. What are the data bus sizes of: (a) 8088 (b) 8086 (c) 80286 (d) 80386sx (e) 80386 (f) 80486
(g) 80586/Pentium
Processor Data bus size
 8088 8
 8086 16
 80286 16
 80386sx 16
 80386 32
 80486 32
 80586/Pentium 64
7. What are the address bus sizes of the above processors?
Processor Address bus size
 8088 20
 8086 20
 80286 24
  80386sx 24
 80386 32
 80486 32
 80586/Pentium 32

8. How many “banks” of memory do each of the above processors have?

Processor Address bus size Banks of memory
 8088 20 1MB
 8086 20 1MB
 80286 24 16MB
 80386sx 24 16MB
 80386 32 4GB
 80486 32 4GB
 80586/Pentium 32 4GB

9. Explain how to store a word in a byte addressable memory (that is, at what address)?
Explain how to store a double word
 Word: Place the low order byte in an even address & the corresponding address
 Double word: Place the low order byte in an address if its value MOD 4 is a
factor of 4.

10. How many memory operations will it take to read a word from the following addresses on
the following processors?

100 10 102 10 104 105

1 3
8088 2 2 2 2 2 2
8028 1 2 1 2 1 2
6
8038 1 1 1 2 1 1
6
11. Repeat the above for double words

100 10 102 10 104 105

1 3
8088 4 4 4 4 4 4
8028 2 3 2 3 2 3
6
8038 1 2 2 2 1 2
6

12. Explain which addresses are best for byte, word and double word variables on an 8088, 80286
and 80386 processor.

CPU BYTE WORD DOUBLE WORD

8088 Any Any address Any address
 address
80286 Any Even address Even address
address
80386 Any Address values that are not equal to 3 in Addresses that are evenly
address (Address MOD 4) operation divisible by 4

13. How many different I/O locations can you address on the 80x86 chip? How many are typically
available on a PC?

There are 65,536 different I/O locations on an 80x86 chip. Only about a maximum of
1024 are available on a typical PC.

14. What is the purpose of the system clock?

The purpose of the system clock is to synchronize the operations of a computer system.

ASIGNMENT 2 – PAGE 190

1. Although the 80x86 processors always use segmented addresses, the instruction encodings for
instructions like “mov AX, I” only have a 16 bit offset encoded into the opcode. Explain.

This is because the AX register is the default destination register in this addressing mode
& is therefore implicit and can be omitted from the opcode.

2. Segmented addressing is best described as a two dimensional addressing scheme. Explain.

It is described as such because it requires two parameters to access a memory location (like
two – dimensional arrays) which are the Segment and the Offset respectively.
3. Convert the following logical addresses to physical addresses. Assume all values are hexadecimal
and real mode operation on the 80x86:

a) 1000:1000 b) 1234:5678 c) 0:1000 d) 100:9000 e) FF00:1000

f) 800:8000 g) 8000:800 h) 234:9843 i) 1111:FFFF j) FFFF:10

Answer: (multiply segment by 10H, add to offset).

a) 11000 b) 179B8 c) 01000 d) 0A000 e) 100000

f) 10000 g) 80800 h) 0BB83 i) 2110F j) 100000

4. Provide normalized forms of the logical addresses above.

Answer: (multiply segment by 10H, add to offset, place last digit of the result as the new offset).

a) 1100:0 b) 179B:8 c) 0100:0 d) 0A00:0 e) 10000:0

f) 1000:0 g) 8080:0 h) 0BB8:3 i) 2110:F j) 10000:0

5. List all the 8086 memory addressing modes.

 Displacement Only/Direct Addressing mode

 Register Indirect Addressing mode
 Indexed Addressing mode
 Based Indexed addressing mode
 Based Indexed Plus Displacement Addressing mode

6. List all 80386 (and later) addressing modes that are not available on the 8086 (use generic forms

like disp[reg], do not enumerate all possible combinations).

 Scaled Indexed Addressing mode – disp[index * n] & [base] [index * n] are its syntax.

7. Besides memory addressing modes, what are the other two major addressing modes?

 Register Addressing modes.

 Register Indirect Addressing mode
8. Describe a common use for each of the following addressing modes:

a) Register b) Displacement only c) Immediate d) Register Indirect e) Indexed

f) Based Indexed g) Based Indexed plus displacement h) Scaled Indexed.

Answer:

 Register: To access frequently used variables.

 Displacement Only: To access simple variables.
 Immediate: Used if the memory location/address is known beforehand.
 Register Indirect: Used to return from subroutines since the return address is stored in a
register.
 Indexed: To manipulate data structures such as arrays.
 Based Indexed: Used to access the stack segment without having to pop it.
 Based Indexed Plus Displacement: Used to manipulate data structures within a segment
 Scaled Indexed: Used to access contiguous variables of fixed length larger than a byte.