Gamecard - Nintendo Switch Brew https://switchbrew.org/w/index.php?title=Game...

Gamecard
is page documents the Nintendo Switch Gamecard.

A Switch game cartridge, A Switch game cartridge,

frontside backside

Close-up of frontside PCB

Close-up of stripped Close-up of backside PCB

frontside PCB

For the Gamecard image format, see here.

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Gamecard - Nintendo Switch Brew https://switchbrew.org/w/index.php?title=Game...

For the Gamecard ASIC, see here.

Contents
Pinout
Slot Pinout
Protocol
Manufacturers

Pinout

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Gamecard - Nintendo Switch Brew https://switchbrew.org/w/index.php?title=Game...

Pin Name Direction Description

Card Detect; Single pin on cartridge side (hardwired to GND).

1,
CD# Output Bridges pin 1 (GND) and 2 (CD#) on slot side as cartridge is
2
inserted

3 CLK Input Clock, 25MHz

Return clock; Game cartridge sends back CLK signal delayed

4 RCLK Output
by a few ns

5 CS# Input Chip Select

6 DAT1 Inout Data bus pin 1

7 DAT0 Inout Data bus pin 0

VCC
8 Input
3.3v

9 DAT3 Inout Data bus pin 3

10 DAT2 Inout Data bus pin 2

VCC
11 Input
1.8v

12 DAT5 Inout Data bus pin 5

13 DAT4 Inout Data bus pin 4

14 DAT6 Inout Data bus pin 6

15 DAT7 Inout Data bus pin 7

16 GND

17 RST# Input Reset

All IO use 1.8V for logic HIGH and 0V for logic LOW.

Slot Pinout
is just maps the cartridge pinout onto the slot on the console.

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Gamecard - Nintendo Switch Brew https://switchbrew.org/w/index.php?title=Game...

Pin Name

1 GND

2 CD#

3 CLK

4 RCLK

5 CS#

6 DAT1

7 DAT0

VCC
8
3.3v

9 DAT3

10 DAT2

VCC
11
1.8v

12 DAT5

13 DAT4

14 DAT6

15 DAT7

16 GND

17 RST# Annotated slot pinout

Protocol
Switch game cartridges use a simple (but Nintendo proprietery) SPI-like bus with 8-bit width (DAT7..0). It is very
similar to the bus interface of 3DS game cartridges, except with very different commands.

e Switch host starts a transfer by first pulling CS low, followed by clocking a byte each clock cycle. e bus data
will always be ready before the rising edge of the CLK signal, so that it can be captured on the rising edge. Aer
command bytes are wrien to the bus, the direction of the bus implicitly changes and the game cartridge responds.
e Switch host keeps clocking while the game cartridge responds. Aer the transfer is ended, the CS line is pulled
high again.

Commands are 16 bytes long, and followed immediately by a 4-byte CRC-32 over the command bytes. Aer this,
the Switch stops driving the data bus, and the bus will be 'floating'. Due to the pull-ups on the bus, it will slowly
converge to logic HIGH state. e Switch will clock 2 cycles to allow the bus to sele a direction change. e
Switch host will then clock another cycle and if the game cartridge didn't receive the CRC OK, it will respond with
"01". Otherwise it will respond with "00" and pull DAT0 low on the next cycle to signal it is busy. e Switch host
will then keep clocking until the cartridge is ready.

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Gamecard - Nintendo Switch Brew https://switchbrew.org/w/index.php?title=Game...

When the game cartridge is ready to send the actual data response, it will pull the DAT0 pin high for 2 cycles to let
the Switch host know. Aer this, the game cartridge will send the actual data response bytes.

e actual response bytes are also followed immediately by a 4-byte CRC-32 over the actual data response bytes.

Manufacturers
MegaChips
Uses package: LGA, TSOP-48
Uses card id: 0xC2
Lapis
Uses package: LGA, TSOP-48
Uses card id: 0xAE
Renesas
Uses package: LGA, TSOP-48
Uses card id: 0x23
SanDisk?
Uses package: ??
Uses card id: 0x45 ?

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This page was last edited on 30 March 2021, at 18:25.

5z5 23. 07. 21 17:44