Design of Controllers

Finite State Machines and

Algorithmic State Machine (ASM) Charts
Structure of a Typical Digital System

Data Inputs Control Inputs

Control
Signals
Datapath Controller
(Execution (Control
Unit) Unit)
Status
Signals
Data Outputs Control Outputs

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Datapath (Execution Unit)
• Manipulates and processes data
• Performs arithmetic and logic operations,
shifting, and other data-processing tasks
• Is composed of registers, gates, multiplexers,
decoders, adders, comparators, ALUs, etc.
• Provides all necessary resources and
interconnects among them to perform specified
task
• Interprets control signals from the Controller
and generates status signals for the Controller

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Controller (Control Unit)

• Controls data movements in the Datapath by

switching multiplexers and enabling or disabling
resources
Example: enable signals for registers
Example: control signals for muxes
• Provides signals to activate various processing
tasks in the Datapath
• Determines the sequence the operations
performed by Datapath
• Follows Some ‘Program’ or Schedule

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Controller
• Controller can be programmable or non-programmable
• Programmable
• Has a program counter which points to next instruction
• Instructions are held in a RAM or ROM externally
• Microprocessor is an example of programmable
controller
• Non-Programmable
• Once designed, implements the same functionality
• Another term is a “hardwired state machine” or
“hardwired instructions”
• In the following several lectures we will be
focusing on non-programmable controllers.

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Finite State Machines
• Digital Systems and especially their Controllers
can be described as Finite State Machines
(FSMs)
• Finite State Machines can be represented using
• State Diagrams and State Tables - suitable
for simple digital systems with a relatively few
inputs and outputs
• Algorithmic State Machine (ASM) Charts -
suitable for complex digital systems with a
large number of inputs and outputs
• All these descriptions can be easily translated to
the corresponding synthesizable VHDL code
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State Diagrams

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Moore Machine

transition
condition 1

state 1 / state 2 /
output 1 output 2
transition
condition 2

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Mealy Machine

transition condition 1 /
output 1

state 1 state 2
transition condition 2 /
output 2

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Moore vs. Mealy FSM (1)

• Moore and Mealy FSMs Can Be

Functionally Equivalent
• Equivalent Mealy FSM can be derived from
Moore FSM and vice versa
• Mealy FSM Has Richer Description and
Usually Requires Smaller Number of States
• Smaller circuit area

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Moore vs. Mealy FSM (2)

• Mealy FSM Computes Outputs as soon as

Inputs Change
• Mealy FSM responds one clock cycle sooner
than equivalent Moore FSM
• Moore FSM Has No Combinational Path
Between Inputs and Outputs
• Moore FSM is more likely to have a shorter
critical path

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Algorithmic State Machine (ASM)
Charts

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Algorithmic State Machine

Algorithmic State Machine –

representation of a Finite State Machine
suitable for FSMs with a larger number of
inputs and outputs compared to FSMs
expressed using state diagrams and state
tables.

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Elements used in ASM charts (1)
State name

Output signals 0 (False) 1 (True)

Condition
or actions
expression
(Moore type)

(a) State box (b) Decision box

Conditional outputs
or actions (Mealy type)

(c) Conditional output box

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State Box
• State box – represents a state. State name
• Equivalent to a node in a state diagram or
a row in a state table. Output signals
or actions
• Contains register transfer actions or (Moore type)
output signals
• Moore-type outputs are listed inside of
the box.
• It is customary to write only the name of
the signal that has to be asserted in the
given state, e.g., z instead of z<=1.
• Also, it might be useful to write an action
to be taken, e.g., count <= count + 1, and
only later translate it to asserting a control
signal that causes a given action to take
place (e.g., enable signal of a counter).
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Decision Box
• Decision box –
indicates that a 0 (False) 1 (True)
Condition
given condition is to expression

be tested and the

exit path is to be
chosen accordingly
The condition
expression may
include one or more
inputs to the FSM.

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Conditional Output Box
• Conditional
output box
Conditional outputs
• Denotes output or actions (Mealy type)
signals that are of
the Mealy type.
• The condition that
determines
whether such
outputs are
generated is
specified in the
decision box.
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ASMs representing simple FSMs

• Algorithmic state machines can model both

Mealy and Moore Finite State Machines
• They can also model machines that are of
the mixed type

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Moore FSM – Example 2: State diagram

Reset

w = 1
w = 0 A z = 0 B z = 0

w = 0

w = 0 w = 1

C z = 1

w = 1

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Moore FSM – Example 2: State table

Present Next state Output

state w = 0 w = 1 z

A A B 0
B A C 0
C A C 1

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ASM Chart for Moore FSM – Example 2
Reset

0
w
1

0
w
1

0 1
w

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• ASM (algorithmic state machine) chart
– Flowchart-like diagram
– Provide the same info as an FSM
– More descriptive, better for complex
description
– ASM block
• One state box
• One ore more optional decision boxes: with T or F
exit path
• One or more conditional output boxes: for Mealy
output

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• E.g. 1.

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• E.g. 2.

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• E.g. 3.

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• E.g. 4.

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• Difference between a regular flowchart
and ASM chart:
– Transition governed by clock
– Transition done between ASM blocks
• Basic rules:
– For a given input combination, there is one
unique exit path from the current ASM block
– The exit path of an ASM block must always
lead to a state box. The state box can be the
state box of the current ASM block or a state
box of another ASM block.

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• Incorrect ASM charts:

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 Some More
Examples from your Course Book
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 Verilog Code of all the above
examples is given in your Book.
Read 5.14,5.15 and 5.16.

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