Coffee Lake H/S Platform System

Memory Interface
Technical White Paper

January 2019

Revision 0.9

Intel Confidential

Document Number: 573583

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Copyright © 2017-2019, Intel Corporation. All rights reserved.

2 Intel Confidential 573583



Contents
1 Introduction ..............................................................................................................6
1.1 Introduction ....................................................................................................... 6
1.2 Reference Documents .......................................................................................... 6
1.3 Terminology and Descriptions ............................................................................... 7
2 CFL-H Memory Interface White Paper ........................................................................ 9
2.1 CFL-H DDR4 SoDIMM 2DPC Daisy Chain NIL Guidelines ............................................ 9
2.2 CFL-H DDR4 SoDIMM 1DPC NIL Guidelines ........................................................... 15
2.3 CFL-H Mixed SoDIMM and Memory Down 2Rx8...................................................... 20
2.4 CFL-H DDR4 1R x16, T4 10L, Dual sided Memory Down Guidelines........................... 28
3 CFL-S Memory Interface White Paper ...................................................................... 34
3.1 CFL-S DDR4 SoDIMM 1DPC NIL Guidelines............................................................ 34
3.2 CFL-S DDR4 Mixed SODIMM and Memory Down x16 .............................................. 39
4 CFL-S/H VREF/DM/ODT Guidelines ......................................................................... 48
4.1 CFL-S and CFL-H System Memory ODT Signal Connectivity Details........................... 48
4.2 Memory Data Mask (DM) Signals Connectivity Details............................................. 48
4.3 CFL H and CFL S System Memory Reference Voltage (VREF) Guidelines .................... 49
5 Memory Interface Schematic Checklist .................................................................... 51

Figures
2-1 CFL-H DDR4 SoDIMM 2DPC Block Diagram .................................................................. 10
2-2 CFL-H DDR4 SoDIMM 2DPC Daisy Chain Placement ...................................................... 10
2-3 CFL-H DDR4 SoDIMM 2DPC Daisy Chain CTRL/Reset/Rcomp Signals Topology .................. 11
2-4 CFL-H DDR4 SoDIMM 2DPC Daisy Chain CMD/Alert/Strobe/Data Signals Topology ............ 11
2-5 CFL-H DDR4 SoDIMM 1DPC Block Diagram .................................................................. 16
2-6 CFL-H DDR4 SoDIMM 1DPC Block Placement ............................................................... 16
2-7 CFL-H DDR4 2Rx8 Memory Down Placement and Block Diagram..................................... 21
2-8 CFL-H DDR4 SODIMM Signals Topology....................................................................... 22
2-9 CFL-H DDR4 2Rx8 DDP Memory Down CLK/CKE/CMD/CTRL/Reset Signals Topologies........ 23
2-10CFL-H DDR4 2Rx8 DDP Memory Down DQ/DQS/RCOMP Signals ..................................... 23
2-11CFL-H DDR4 x16 T4 10L Dual sided Memory Down Placement and Block Diagram............. 29
2-12CFL-H DDR4 x16 T4 10L Dual sided Memory Down Strobe/Data/RCOMP Signal Topologies . 29
2-13CFL-H DDR4 x16 T4 10L Dual sided Memory Down CLK/CTRL/CKE/CMD/Reset Signal Topology
30
3-1 CFL-S DDR4 1DPC SoDIMM T3/4L Inline NIL Placement and Block Diagram...................... 35
3-2 CFL-S DDR4 SoDIMM 1DPC Signals Topology ............................................................... 35
3-3 CFL-S DDR4 SoDIMM 1DPC DDR Reset Topology .......................................................... 35
3-4 CFL-S DDR4 Mixed SODIMM and Memory Down x16 Placement and Block Diagram ........... 40
3-5 CFL-S DDR4 SODIMM Signals Topology ....................................................................... 40
3-6 CFL-S DDR4 1Rx16 Memory Down Strobe/Data/RCOMP Signal Topologies ....................... 40
3-7 CFL-S DDR4 1Rx16 Memory Down CLK/CTRL/CKE/CMD/Reset Signal Topology................. 41
4-1 CFL H/S DDR4 SO-DIMM VREF-CA Overview ................................................................ 49
4-2 CFL-H/S DDR4 x16 Memory Down VREF-CA Overview ................................................... 50
4-3 CFL-H DDR4 x8 Memory Down VREF-CA Overview........................................................ 50

573583 Intel Confidential 3

Tables
1-1 Non-POR System Memory Configurations Supported in this White Paper ........................... 6
1-2 CFL-H/S Reference Documents .................................................................................... 6
1-3 CFL-H System Memory Interface Guideline Terminology and Descriptions.......................... 7
2-1 System Memory Configuration Details Covered in this Section ......................................... 9
2-2 CFL-H DDR4 SoDIMM 2DPC Daisy Chain Signal Routing Guidelines ..................................12
2-3 CFL H DDR4 SoDIMM Lengths Matching Guidelines........................................................14
2-4 System Memory Configuration Details Covered in this Section ........................................15
2-5 CFL-H DDR4 SoDIMM 1DPC Signal Routing Guidelines ...................................................17
2-6 CFL-H DDR4 SO-DIMM 1DPC Length and Matching Guidelines.........................................19
2-7 System Memory Configuration Details Covered in this Section ........................................20
2-8 CFL-H DDR4 Mixed SoDIMM and Memory Down 2Rx8 - Memory Down Routing Guideline....24
2-9 CFL-H DDR4 2Rx8 DDP Memory Down Length Matching Guidelines..................................26
2-10System Memory Configuration Details Covered in this Section ........................................28
2-11CFL-H DDR4 x16 T4 10L Dual sided Memory Down Routing Guideline ..............................31
2-12CFL-H DDR4 x16 T4 10L, Dual sided Memory Down Length Matching Guidelines ...............32
3-1 System Memory Configuration Details Covered in this Section ........................................34
3-2 CFL-S DDR4 SoDIMM 1DPC 4L Routing Guidelines.........................................................36
3-3 CFL-S DDR4 SoDIMM 1DPC 4L Lengths Matching Guidelines ...........................................38
3-4 System Memory Configuration Details Covered in this Section ........................................39
3-5 CFL-S DDR4 Mixed SODIMM and Memory down x16 - SODIMM Routing Guidelines ............41
3-6 CFL-S DDR4 Mixed SODIMM and Memory down x16 - Memory Down Routing Guideline......44
3-7 CFL-S DDR4 Mixed SODIMM and Memory down x16 - SODIMM Lengths Matching Guidelines .
46
3-8 CFL-S DDR4 Mixed SODIMM and Memory down x16 - Memory Down Lengths Matching
Guidelines ...............................................................................................................47
4-1 ODT Signals Connectivity Table ..................................................................................48
4-2 DIMMs/DRAMs DM Signals Connectivity Table...............................................................48

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Revision History

Document Revision
Description Revision Date
Number Number

0.5 • Initial release June 2017

• Added C2 cap in value 0.01 uF to CLK signal for MDx16 Figure 2-13 and
Figure 3-7.
• Changed termination from VTT to VDDQ for CKL signal MDx8 and MDx16
0.7 August 2017
Figure 2-13, Figure 3-7 and Figure 2-9.
• Changed C2 value capacitor from 0.1 uF to 0.01 uF for CLK signal MDx8
Table 2-8.
• Updated CFL H 1DPC SoDIMM Frequency from 2400 MT/s to 2666 MT/s
0.71 October 2017
(Section 2.2).
573583
• Republish.
• Updated maximum frequency of CFL-H DDR4 SoDIMM 2DPC Daisy Chain
topology to 2400 MT/s (Section 2.1).
0.8 • Updated maximum frequency of CFL-H DDR4 Mixed So-DIMM and MD 2Rx8 November 2018
topology to 2400 MT/s (Section 2.3).
• Updated maximum frequency of CFL-H DDR4 Dual sided MD 1Rx16 topology
to 2400 MT/s (Section 2.4).
• Fixed maximum frequency of CFL-H DDR4 SoDIMM 2DPC Daisy Chain
0.9 January 2019
topology to 2133 MT/s (Section 2.1).

§§

573583 Intel Confidential 5

 Introduction

1 Introduction

1.1 Introduction
This Technical White Paper covers the Coffee Lake S and H the system memory
interface motherboard design recommendations for the following Non Plan of Record
(Non-POR), but support system memory interface configurations.

These recommendations have been developed to enable flexibility for board designers,
while reducing the risk of motherboard system memory interface related issues.

These recommendations are not fully simulated and they are not validated. As
a result, it is up to those that implement them to fully validate their own
design. The validation and risk are the sole responsibility of the customer.

Table 1-1. Non-POR System Memory Configurations Supported in this White Paper
DRAMs/
Memory Memory Channel PCB CPU Ball
Section CPU Connector
Type Speed Configuration Type/Layers Map
Placement

ECC/Non ECC
SoDIMM 2DPC ECC - T3/10L
Daisy Chain- Non
2.1 CFL-H DDR4 2133 Single Side Non ECC - 8L/
Topology Interleaved
T3
Both Channels

ECC/Non-ECC ECC - T3/10L

SoDIMM 1DPC Non
2.2 CFL-H DDR4 2666 Single Side Non ECC - 8L/ Interleaved
Both Channels T3

Mixed SODIMM
Interleaved/
and MD 2Rx8
2.3 CFL-H DDR4 2400 Single Side T3/10L Non
(8 DRAMS per Interleaved
channel)

Dual sided
2.4 CFL-H DDR4 2400 memory down Dual sided T4/10L Interleaved
1Rx16

SoDIMM 1DPC Single Side Non

3.1 CFL-S DDR4 2133 T3/4L
Both Channels Side-By-Side Interleaved

Mixed SODIMM
Single Side/
2133/ and MD x16
3.2 CFL-S DDR4 Back-To- T3/8L Interleaved
2400 (4 DRAMS per Back
channel)

1.2 Reference Documents

Table 1-2. CFL-H/S Reference Documents (Sheet 1 of 2)
Document Name CCL
th ®
8 Generation Intel Core™ Processor Families
CFL EDS 570805
External Design Specification Volume 1 of 2

CFL H PDG Coffee Lake H Platform Design Guide 571391

CFL S + CNL PCH PDG Coffee Lake S CNP Platform Design Guide 571264

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Introduction

Table 1-2. CFL-H/S Reference Documents (Sheet 2 of 2)

Document Name CCL

Coffee Lake S CNP Platform Design Guide PRE PUB

CFL S + KBL PCH PDG 570576
Review

System Memory Automated Trace Length

ATLC 568458
Calculator

1.3 Terminology and Descriptions

Table 1-3. CFL-H System Memory Interface Guideline Terminology and Descriptions
(Sheet 1 of 2)
CFL-H CFL-S

CFL Processor and

Memory Type DDR4 DDR4 DDR4
DDR4 DDR4
SO-DIMM no SO-DIMM Memory Down
SO-DIMM+ECC Memory Down
ECC 1DPC

Signal Group Details

CKN[3:0], CKN[3:0], CKN[1:0], CKP[1:0], CKP[1:0],

Clock (CLK)
CKP[3:0] CKP[3:0] CKP[1:0] CKN[1:0] CKN[1:0]

CS#[3:0], CS#[3:0], CS#[1:0], CS#[1:0], CS#[1:0],

Control (CTRL)
ODT[3:0] ODT[3:0] ODT[1:0] ODT[1:0] ODT[1:0]

Clock Enable (CKE) CKE[3:0] CKE[3:0] CKE[1:0] CKE[1:0] CKE[1:0]

MA[16:0], MA[16:0], MA[16:0], MA[16:0], MA[16:0],

BG[1:0], BG[1:0], BG[1:0], BG[1:0], BG[1:0],
Command (CMD)
BA[1:0], ACT#, BA[1:0],ACT#, BA[1:0], ACT#, BA[1:0], ACT#, BA[1:0], ACT#,
PAR PAR PAR PAR PAR

DQSP[7:0], DQSP[7:0], DQSP[7:0], DQSN[7:0], DQSN[7:0],

Strobe
DQSN[7:0] DQSN[7:0] DQSN[7:0] DQSP[7:0] DQSP[7:0]

DQSP[8],
ECC strobe N/A N/A N/A N/A
DQSN[8]

Data DQ[63:0] DQ[63:0] DQ[63:0] DQ[63:0] DQ[63:0]

ECC Data DQ[71:64] N/A N/A N/A N/A

Alert ALERT# ALERT# ALERT# ALERT# ALERT#

Reset DRAM_RESET# DRAM_RESET# DRAM_RESET# DRAM_RESET# DRAM_RESET#

on package on package
RCOMP DDR_RCOMP[2:0] DDR_RCOMP[2:0] DDR_RCOMP[2:0]

Guideline Terminology Descriptions

Motherboard Layer Signal Transition Via Placement Locations. For SO-DIMM designs, this identifies
Via Count the PTH Via Placement Locations. For DRAM Down designs, this does not identify the total count of
micro-vias or buried vias on a signal.

Trace Width The trace widths are for reference. The controlling specification is the target trace impedance.

Diff Spacing Differential spacing between CK and CK# and between DQS and DQS#.

Group Spacing Minimum self spacing and spacing between signals within the same signal group.

Minimum spacing between signals from the following different signal groups:
1. CLK-CTRL, CLK-CKE, CLK-CMD, CLK-Reset CTRL-CKE, CTRL-CMD, CTRL-Reset, CKE-CMD,
Group to Group CKE-Reset.
Spacing 2. CLK-Strobe, CLK-Data, CTRL-Strobe, CTRL-Data, CKE-Strobe, CKE-Data, CMD-Strobe, CMD-
Data, Reset-Strobe, Reset-Data.
3. Minimum spacing between bytes with different channels.

1. Minimum spacing between strobe and data group signals within the same byte.
Byte Spacing
2. Minimum spacing between bytes within the same channel.

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 Introduction

Table 1-3. CFL-H System Memory Interface Guideline Terminology and Descriptions
(Sheet 2 of 2)
CFL-H CFL-S

CFL Processor and

Memory Type DDR4 DDR4 DDR4
DDR4 DDR4
SO-DIMM no SO-DIMM Memory Down
SO-DIMM+ECC Memory Down
ECC 1DPC

DDR to Other
The minimum spacing requirement for DDR to other signal/interfaces is 25 mils.
Interfaces/Signals

Impedance numbers are calculated according to the stack-up layers thickness, the material
DDR Trace conductivity, traces spacing, width, dielectric constant and thickness.
impedance The controlling specification is the target trace impedance. It is allowed to change
and trace the signal trace width within design tolerance.
geometries It is strictly not recommended to reduce spacing between signals. Any spacing reduction can cause
to performance degradation.

Total length refers to the signal trace length calculated from Processor die pad to each DRAM ball or
Total maximum
each DIMM connector pin, which include Processor inner PKG trace length, Break-out, Main and
length
Break-in trace segments of each DRAM.

§§

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CFL-H Memory Interface White Paper

2 CFL-H Memory Interface White

Paper

2.1 CFL-H DDR4 SoDIMM 2DPC Daisy Chain NIL

Guidelines
Table 2-1. System Memory Configuration Details Covered in this Section
Parameter Details

Processor CFL-H

Memory Type DDR4

Channel A = Two SO-DIMMs

Configuration
Channel B = Two SO-DIMMs

Speed (MT/s) 2133

Channels 1 and 2

System Memory Voltage 1.2 V

Max Ranks Per Channel 4

DRAM Die Density (Gb) 4 and 8

Max Capacity (GB) 64

ECC DIMMs:
RC-D(1Rx8),RC-G(2Rx8),RC-F(2Rx8),RC-H(2Rx8)
SO-DIMM Raw-Card Types
Non-ECC DIMMs:
RC-A(1Rx8), RC-B (2Rx8),RC-E (2Rx8),RC-C(1Rx16)

ECC - 10L/T3
PCB Layers/Type(1)
Non ECC - 8L/T3

Single side Top layer placement

SODIMM module placement 2DPC are Daisy Chain Topology.
For each channel the SODIMMs are back to back.

Processor Memory Ball Map(2) Non-Interleaved (NIL)

DRAM Device ODT Capability(3) Enable

Strobe/Data/CTRL/CLK/CKE/CMD = PKG+BO1+BO2+M+BI
Total Maximum Length
RCOMP = M

Notes:
1. Type 3 (T3)= PCB with zero build-up layers using Plated Through-hole (PTH) Vias with no Micro-vias.
Refer “Stack-Up and PCB Considerations” chapter for more details in this document.
2. Non-Interleave = The processor is optimized for a side-by-side ball map and placement of the DRAM
memory down devices or DIMM Side-by-Side (inline) placement. Each memory channel’s signals are
grouped together on one side of the processor packages.
Interleave = The processor is optimized for a back-to-back ball map and placement of the DIMMs. Each
memory channel’s signals are grouped together on front or back side of the processor packages.
3. The DRAM Device ODT Capability can be enabled or disabled for reads and writes depending on the system
memory interface margins. Enabling the DRAM device ODT increases the memory interface power and
improves signal integrity/margins, while disabling the DRAM device ODT decreases the memory interface
power but degrades signal integrity/margins. For ODT implementation recommendation for this topology,
refer to Table 4-1.

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 CFL-H Memory Interface White Paper

Figure 2-1. CFL-H DDR4 SoDIMM 2DPC Block Diagram

CFL H

DDR1_CMD DDR0_CMD
DDR0_CKP[1:0] DDR0_CKP[3:2] DDR1_CKP[3:2] DDR1_CKP[1:0] DDR_RESET
DDR1_DQ DDR0_DQ
DDR0_CKN[1:0] DDR0_CKN[3:2] DDR1_CKN[3:2] DDR1_CKN[1:0]
DDR1_ECC DDR0_ECC
DDR0_CKE[1:0] DDR0_CKE[3:2] DDR1_CKE[3:2] DDR1_CKE[1:0]
DDR1_DQS DDR0_DQS
DDR0_CS[1:0] DDR0_CS[3:2] DDR1_CS[3:2] DDR1_CS[1:0]
DDR0_ODT[1:0] DDR0_ODT[3:2] DDR1_ODT[3:2] DDR1_ODT[1:0]

Channel 0, SO‐DIMM 1, Rank 2:3
BOTTOM
Channel 0, SO‐DIMM 0, Rank 0:1
TOP

Channel 1, SO‐DIMM 1, Rank 2:3
BOTTOM
Channel 1, SO‐DIMM 0, Rank 0:1
TOPTOP

Figure 2-2. CFL-H DDR4 SoDIMM 2DPC Daisy Chain Placement

CFL Non‐Interleave

Ch A Ch B

Ch A SoDIMM0 Ch B  SoDIMM0
Ch A SoDIMM1 Ch B  SoDIMM1

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CFL-H Memory Interface White Paper

Figure 2-3. CFL-H DDR4 SoDIMM 2DPC Daisy Chain CTRL/Reset/Rcomp Signals Topology

CFL‐H =VIA DIMMs

CLK, BO1 BO2 M BI
CTRL,
BO2 BO2
CKE BO1
a b
M BI

R
RCOMP M

VDDQ

R1
R2
Reset BO1 BO2 M BI

C1

Note: DRAM_RST CAP should have no stuff.

Figure 2-4. CFL-H DDR4 SoDIMM 2DPC Daisy Chain CMD/Alert/Strobe/Data Signals
Topology

DIMM0 DIMM1
CFL‐H

BI BI

BO1 BO2 M S2S

CMD,
DIMM0 DIMM1
 Strobe, 
Data, 
ECC
Alert
BI BI

BO2 BO2
BO1 M S2S
a b

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 CFL-H Memory Interface White Paper

Table 2-2. CFL-H DDR4 SoDIMM 2DPC Daisy Chain Signal Routing Guidelines
(Sheet 1 of 2)
Target
Minimum Trace Spacing Maximum Length
Impedance
(mils) (mils)
(Ω)

Trace Width
Layer Route

R (Ω±1%)
Reference

Via Count
Region

(mils)

Group to Group

Notes
Breakout [1,2]

C(uF)
Signal

Byte [1]/[2]
Single Ended
Group

Tolerance

[1]/[2]

Region
Group

Total
(%)
Diff

Diff
BO1 MS VSS/VCC 1 3 3.5 8 8/ 400
[1] 600
CLK BO2 SL VSS 0 3 3 8 8/ 450 1,2,
5000 3,6
Channel 0 M SL VSS 0 3.5 88 ±10 3.5 12 12/

BI MS VSS/VCC 1 4 4 12 12/ 300

BO1 MS VSS/VCC 1 3 3.5 5 5/ 25

BO2a SL VSS 0 3 3 5 5/ 150

CLK [2] 700
1,2,
BO2b SL VSS 0 3 3 8 8/ 600 5000 3,6
Channel 1
M SL VSS 0 3.5 88 ±10 3.5 12 12/

BI MS VSS/VCC 1 4 4 12 12/ 300

BO1 MS VSS/VCC 1 3 3.5 5/10 500

CTRL [1] 600
CKE BO2 SL VSS 0 3 5 5/10 500 1,2,
5000 3
M SL VSS 0 6 40 ±10 12 12/25
Channel 0
BI MS VSS/VCC 1 4 4 12/25 300

BO1 MS VSS/VCC 1 3 3.5 5/10 25

CTRL BO2a SL VSS 0 3 3 5/10 150 [2] 700

CKE 1,2,
BO2b SL VSS 0 3 4 5/10 600 5000 3

Channel 1 M SL VSS 0 6 40 ±10 12 12/25

BI MS VSS/VCC 1 4 4 12/25 300

BO1 MS VSS/VCC 1 3 3.5 5/ 500

[1] 600
BO2 SL VSS 0 3 5 5/ 500
Alert/CMD 1,2,
M SL VSS 0 7.5 35 ±10 13.5 12/ 5000 3
Channel 0
BI MS VSS/VCC 1 4 4 12/ 200

S2S SL VSS 0 7.5 8 12/ 550

BO1 MS VSS/VCC 1 3 3.5 5/ 25

BO2a SL VSS 0 3 3 5/ 150 [2] 700

Alert/CMD BO2b SL VSS 0 3 4 5/ 650 1,2,
5000 3
Channel 1 M SL VSS 0 7.5 35 ±10 13.5 12/

BI MS VSS/VCC 1 4 4 12/ 200

S2S SL VSS 0 7.5 8 12/ 550

BO1 MS VSS 1 3 3.5 /10 4/25 300

[1] 300
Strobe BO2 SL VSS 0 3 3 /10 5/25 650
1,2,
M SL VSS 0 5.5 75 42 ±10 3.5 /25 12/25 5000 3,4,
Ch0 5,6
[8:0] BI MS VSS 1 4 4 /25 5/25 85

S2S SL VSS 0 3 3 /12 12/12 550

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Table 2-2. CFL-H DDR4 SoDIMM 2DPC Daisy Chain Signal Routing Guidelines
(Sheet 2 of 2)
Target
Minimum Trace Spacing Maximum Length
Impedance
(mils) (mils)
(Ω)

Trace Width
Layer Route

R (Ω±1%)
Reference

Via Count
Region

(mils)

Group to Group

Notes
C(uF)
Breakout [1,2]
Signal

Byte [1]/[2]
Single Ended
Group

Tolerance

[1]/[2]

Region
Group

Total
(%)
Diff

Diff
BO1 MS VSS 1 3 3.5 /10 4/25 200
[1] 450
Strobe BO2 SL VSS 0 3 3 /10 5/25 350
1,2,
M SL VSS 0 5.5 75 ±10 3.5 /25 12/25 5000 3,4,
Ch1 5,6
[0] BI MS VSS 1 4 4 /25 5/25 85

S2S SL VSS 0 3 3 /12 12/12 550

BO1 MS VSS 1 3 3.5 /10 4/25 25

BO2a SL VSS 0 3 3 /10 5/25 600 [2] 750

Strobe
BO2b SL VSS 0 3 3 /10 5/25 300 1,2,
5000 3,4,
Ch1 M SL VSS 0 5.5 75 ±10 3.5 /25 12/25 5,6
[8:1]
BI MS VSS 1 4 4 /25 5/25 85

S2S SL VSS 0 3 3 /12 12/12 550

Data BO1 MS VSS 1 3 3.5 /10 4/25 300

[1] 700
BO2 SL VSS 0 3 3 /10 5/25 650
Ch0 Byte 1,2,
M SL VSS 0 5.5 3,4,
[7:0] 42 ±10 9 /25 12/25 5000
5
BI MS VSS 1 4 4 /25 5/25 85
Ch0
ECC[7:0] S2S SL VSS 0 3 9 /12 12/12 550

BO1 MS VSS 1 3 3.5 /10 4/25 200

[1] 450
Data BO2 SL VSS 0 3 4.5 /10 5/25 350
1,2,
Ch1 Byte M SL VSS 0 5.5 42 ±10 9 /25 12/25 3,4,
5000
5
[0]
BI MS VSS 1 4 4 /25 5/25 85

S2S SL VSS 0 3 9 /12 12/12 550

BO1 MS VSS 1 3 3.5 /10 4/25 25

Data
BO2a SL VSS 0 3 3 /10 5/25 600 [2] 750
Ch1 Byte 5.5/
BO2b SL VSS 0 3 5.5 /10 300 1,2,
[7:1] 25 3,4,
5000
5
M SL VSS 0 5.5 42 ±10 9 /25 12/25
Ch1
ECC[7:0] BI MS VSS 1 4 4 /25 5/25 85

S2S SL VSS 0 3 9 /12 12/12 550

BO1 MS VSS/VCC 1 4 50 ±10 4/4 30 (R1)

MS VSS/VCC 0 4 50 ±10 8/8 470
100
BO2 0
SL VSS 0 3.5 50 ±10 8/8 (R2)
Reset 8000 3,7
0
MS VSS/VCC 0 4 50 ±10 20/20
M
SL VSS 0 3.5 50 ±10 20/20 (C1)
0.1
BI MS VSS/VCC 1 4 50 ±10 20/20

RCOMP[0] M MS VSS 2 12-15 20 25/25 500 121

RCOMP[1] M MS VSS 2 12-15 20 25/25 500 75

RCOMP[2] M MS VSS 2 12-15 20 25/25 500 100

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 CFL-H Memory Interface White Paper

Notes:
1. The Channel A CLK/CTRL/CKE/CMD/Alert signals all must route on the same inner layer together. The Channel B CLK/CTRL/CKE/
CMD/Alert signals all must route on the same inner layer together. The Channel A and Channel B Strobe/Data signals of the same
byte must route on the same inner layer together.
2. The Maximum Breakout Length = BO1+BO2 [1] or BO1+(BO2a + BO2b) [2], where specified
3. Signals, while routed on inner PCB layers must be ground referenced with solid ground floods on both sides.
4. The Strobe and Data Group Signals within the same byte must route together for their entire route from CPU Ball to DIMM Pin.
5. DQ Bit Swapping is allowed within the same byte, and Byte Swapping is allowed within the same channel. Utilizing this capability
enables a modified SO-DIMM pin map and places common SO-DIMM pins in overlapping positions on the top and bottom layers
of the motherboard. It also reduces the Data and Strobe signal T-Topology Break-In (BI) segment lengths, it helps eliminate
serpentine routing, and creates more room for ground vias next to every Data and Strobe signal transition via in the SO-DIMM
pin field area.
6. Clock (CLK and CLK#) and Strobe (DQS and DQS#) differential signal swapping within a pair is not allowed. Also, differential
clock pair to clock pair swapping within a channel is not allowed.
7. Capacitor C1 is a defensive design and should have NO STUFF by default.
8. Impedance numbers are for reference only, it is calculating according to the stackup layers thickness, the material conductivity,
traces spacing and width. The recommendation is to follow stackup and traces geometries.

Table 2-3. CFL H DDR4 SoDIMM Lengths Matching Guidelines

Length Matching (mils)
Signal
Rule Details Notes
Group
Minimum Maximum
1,2
CK[X] - CK#[X], where X = 0 or 1 -5 5
CLK
1,2
CK/CK#[1:0] (max - min) 0 40

CTRL/CKE (max - min) 0 200 1,2

CTRL/CKE
1,2
CK/CK#[1:0] - CTRL/CKE 0 100
1,2
CMD (max - min) 0 200
CMD
CK/CK#[1:0] - CMD -500 500 1,2

1,2
DQS[X] - DQS#[X], where X = 0 to 7 -5 5
Strobe
1,2
CK/CK#[1:0] - DQS/DQS#[X], where X = 0 to 7 -1500 2500

Data DQ(Byte[X]) - DQS/DQS#[X], where X = 0 to 7 -20 20 1,2,3

Notes:
1. Length Matching = CPU Die to SO-DIMM Pin (PKG + BO1 + BO2 + M + BI, PKG + BO1 +BO2a + BO2b + M
+ BI); where a conversion factor of 0.9 must be used on Micro-Strip Segments to convert Micro-Strip lengths
to Strip-Line equivalent lengths.
2. To help facilitate and check the Length and Matching relationships on a design, refer to the Memory Automated
Trace Length Calculator (# 568458). Refer Table 1-2.
3. Byte[0] = DQ[7:0], DQS/DQS#[0], Byte[1] = DQ[15:8], DQS/DQS#[1], Byte[2] = DQ[23:16], DQS/
DQS#[2], Byte[3] = DQ[31:24], DQS/DQS#[3], Byte[4] = DQ[39:32], DQS/DQS#[4], Byte[5] = DQ[47:40],
DQS/DQS#[5], Byte[6] = DQ[55:48], DQS/DQS#[6], Byte[7] = DQ[63:56], DQS/DQS#[7].

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2.2 CFL-H DDR4 SoDIMM 1DPC NIL Guidelines

Table 2-4. System Memory Configuration Details
Parameter Details

Processor CFL-H

Memory Type DDR4

Channel A = One SO-DIMMs

Configuration
Channel B = One SO-DIMMs

Maximum Speed (MT/s) 2666

Channels 1 and 2

System Memory Voltage 1.2 V

Maximum Ranks Per Channel 2

DRAM Die Density (Gb) 4 and 8

Maximum Capacity (GB) 32

ECC DIMMs:
RC-D(1Rx8),RC-G(2Rx8)
SO-DIMM Raw-Card Types
Non-ECC DIMMs:
RC-A(1Rx8), RC-E (2Rx8),RC-C(1Rx16)

ECC - 10L/T3
PCB Layers/Type(1)
Non ECC - 8L/T3

Single side Top layer placement

SODIMM module placement For 1DPC implementation, drop the farther SoDIMM connector at
each channel.

Processor Memory Ball Map(2) Non-Interleaved (NIL)

DRAM Device ODT Capability(3) Enable

Strobe/Data/CTRL/CLK/CKE/CMD = PKG+BO1+BO2+M+BI
Total Maximum Length
RCOMP = M

Notes:
1. Type 3 (T3)= PCB with zero build-up layers using Plated Through-hole (PTH) Vias with no Micro-vias.
Refer “Stack-Up and PCB Considerations” chapter for more details in this document.
2. Non-Interleave = The processor is optimized for a side-by-side ball map and placement of the DRAM
memory down devices or DIMM Side-by-Side (inline) placement. Each memory channel’s signals are
grouped together on one side of the processor packages.
Interleave = The processor is optimized for a back-to-back ball map and placement of the DIMMs. Each
memory channel’s signals are grouped together on front or back side of the processor packages.
3. The DRAM Device ODT Capability can be enabled or disabled for reads and writes depending on the system
memory interface margins. Enabling the DRAM device ODT increases the memory interface power and
improves signal integrity/margins, while disabling the DRAM device ODT decreases the memory interface
power but degrades signal integrity/margins. For ODT implementation recommendation for this topology,
refer to Table 4-1.

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Figure 2-5. CFL-H DDR4 SoDIMM 1DPC Block Diagram

CFL‐H

DDR0_CKP[1:0] DDR1_CKP[1:0]
DDR0_CKN[1:0] DDR1_CKN[1:0]
DDR0_CKE[1:0] DDR1_CKE[1:0] DDR_RESET
DDR0_CS[1:0] DDR1_CS[1:0]
DDR0_ODT[1:0] DDR1_ODT[1:0]
DDR0_CMD DDR1_CMD
DDR0_DQ DDR1_DQ
DDR0_DQS DDR1_DQS
DDR0_ALERT DDR1_ALERT

Channel 0, SO‐DIMM, Rank 0:1

Channel 1, SO‐DIMM, Rank 0:1

Figure 2-6. CFL-H DDR4 SoDIMM 1DPC Block Placement

For CFL H DDR4 SoDIMM 1DPC Signal Topology, refer to Figure 4-7, “CFL-H DDR4
SoDIMM 2DPC Signals Topology” in CFL-H PDG.

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Table 2-5. CFL-H DDR4 SoDIMM 1DPC Signal Routing Guidelines (Sheet 1 of 2)
Target
Minimum Trace Spacing Maximum Length
Impedance
(mils) (mils)
(Ω)

Trace Width
Layer Route

R (Ω±1%)
Reference

Via Count
Region

(mils)

Group to Group

Notes
Breakout [1,2]

C(uF)
Signal

Byte [1]/[2]
Single Ended
Group

Tolerance

[1]/[2]

Region
Group

Total
(%)
Diff

Diff
BO1 MS VSS/VCC 1 3 3.5 8 8/10 400
[1] 500
CLK BO2 SL VSS 0 3 3 8 8/10 200 1,2,
4600 3,6
Channel 0 M SL VSS 0 3.5 88 ±10 3.5 16 16/25

BI MS VSS/VCC 1 4 4 16 16/25 300

BO1 MS VSS/VCC 1 3 3.5 8 8/10 25

[1] 620
CLK BO2 SL VSS 0 3 3 8 8/10 610 1,2,
4600 3,6
Channel 1 M SL VSS 0 3.5 88 ±10 3.5 16 16/25

BI MS VSS/VCC 1 4 4 16 16/25 300

BO1 MS VSS/VCC 1 3 3.5 5/10 350

CTRL [1] 600
CKE BO2 SL VSS 0 3 5 5/10 500 1,2,
4600 3
CMD M SL VSS 0 6 40 ±10 12 16/25
Channel 0
BI MS VSS/VCC 1 4 4 16/25 300

BO1 MS VSS/VCC 1 3 3.5 5/10 25

CTRL BO2a SL VSS 0 3 3 5/10 150 [2] 700

CKE 1,2,
BO2b SL VSS 0 3 5.5 5/10 600 4600 3
CMD
Channel 1 M SL VSS 0 6 40 ±10 12 16/25

BI MS VSS/VCC 1 4 4 16/25 300

BO1 MS VSS 1 3 3.5 /10 4/25 300

[1] 700 1,2,
Strobe BO2 SL VSS 0 3 3 /10 5/25 650 3,4,
4600 5,,8
Ch0 [7:0] M SL VSS 0 3.5 88 ±10 3.5 /25 16/25 6

BI MS VSS 1 4 4 /25 5/25 300

BO1 MS VSS 1 3 3.5 /10 4/25 300

[1] 450 1,2,
Strobe BO2 SL VSS 0 3 3 /10 5/25 350 3,4,
4600 5,6,
Ch1 [0] M SL VSS 0 3.5 88 ±10 3.5 /25 16/25 8

BI MS VSS 1 4 4 /25 5/25 300

BO1 MS VSS 1 3 3.5 /10 4/25 25

BO2a SL VSS 0 3 3 /10 5/25 600 [2] 750 1,2,

Strobe 3,4,
BO2b SL VSS 0 3 3 /10 5/25 300 4600 5,6,
Ch1 [7:1] 8
M SL VSS 0 3.5 88 ±10 3.5 /25 16/25

BI MS VSS 1 4 4 /25 5/25 300

BO1 MS VSS 1 3 3.5 /10 4/25 300

[1] 700
Data BO2 SL VSS 0 3 3 /10 5/25 650 1,2,
3,4,
Ch0 Byte 4600
5,8
[7:0] M SL VSS 0 3.5 50 ±10 8 /25 16/25

BI MS VSS 1 4 4 /25 5/25 300

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Table 2-5. CFL-H DDR4 SoDIMM 1DPC Signal Routing Guidelines (Sheet 2 of 2)
Target
Minimum Trace Spacing Maximum Length
Impedance
(mils) (mils)
(Ω)

Trace Width
Layer Route

R (Ω±1%)
Reference

Via Count
Region

(mils)

Group to Group

Notes
Breakout [1,2]

C(uF)
Signal

Byte [1]/[2]
Single Ended
Group

Tolerance

[1]/[2]

Region
Group

Total
(%)
Diff

Diff
BO1 MS VSS 1 3 3.5 /10 4/25 300
[1] 450
Data BO2 SL VSS 0 3 4.5 /10 5/25 350 1,2,
Ch1 Byte 4600 3,4,
5,8
[0] M SL VSS 0 3.5 50 ±10 8 /25 16/25

BI MS VSS 1 4 4 /25 5/25 300

BO1 MS VSS 1 3 3.5 /10 4/25 25

BO2a SL VSS 0 3 3 /10 5/25 600 [2] 750

Data 1,2,
BO2b SL VSS 0 3 5.5 /10 5.5/25 300 4600 3,4,
Ch1 Byte
5,8
[7:1]
M SL VSS 0 3.5 50 ±10 8 /25 16/25

BI MS VSS 1 4 4 /25 5/25 300

BO1 MS VSS/VCC 1 3 3.5 5/10 30

BO2a SL VSS 0 3 3 5/10 500 [2] 750

1,2,
Alert BO2b SL VSS 0 3.5 5 5/10 200 4600 3,

M SL VSS 0 6 40 ±10 12 16/25

BI MS VSS/VCC 1 4 4 16/25 300

BO1 MS VSS/VCC 1 4 50 ±10 4/4 30

(R1)
MS VSS/VCC 0 4 50 ±10 4/4 470
BO2 1000 (R2)
SL VSS 0 3.5 50 ±10 4/4
Reset 8000 0 3,7
MS VSS/VCC 0 4 50 ±10 4/4 (C1)
M 0.1
SL VSS 0 3.5 50 ±10 4/4

BI MS VSS/VCC 1 4 50 ±10 4/4

RCOMP
M MS VSS 2 12-15 20 25/25 500 121
[0]

RCOMP
M MS VSS 2 12-15 20 25/25 500 75
[1]

RCOMP
M MS VSS 2 12-15 20 25/25 500 100
[2]

Notes:
1. The Channel A CLK/CTRL/CKE/CMD/Strobe/Data signals all must route on the same inner layer together and they must not route
on the same inner layer or an adjacent layer, as any of the Channel B CLK/CTRL/CKE/CMD/Strobe/Data signals. The Channel B
CLK/CTRL/CKE/CMD/Strobe/Data signals all must route on the same inner layer together and they must not route on the same
inner layer or an adjacent layer as any of the Channel A CLK/CTRL/CKE/CMD/Strobe/Data signals.
2. The Maximum Breakout Length = BO1+BO2 [1] or BO1+(BO2a + BO2b) [2], where specified.
3. Signals, while routed on inner PCB layers must be ground referenced with solid ground floods on both sides.
4. The Strobe and Data Group Signals within the same byte must route together for their entire route from CPU Ball to DIMM Pin.
5. DQ Bit Swapping is allowed within the same byte, and Byte Swapping is allowed within the same channel. Utilizing this capability
enables a modified SO-DIMM pin map and places common SO-DIMM pins in overlapping positions on the top and bottom layers
of the motherboard. It also reduces the Data and Strobe signal T-Topology Break-In (BI) segment lengths, it helps eliminate
serpentine routing, and creates more room for ground vias next to every Data and Strobe signal transition via in the SO-DIMM
pin field area.
6. Clock (CLK and CLK#) and Strobe (DQS and DQS#) differential signal swapping within a pair is not allowed. Also differential
clock pair to clock pair swapping within a channel is not allowed.
7. Capacitor C1 is a defensive design and should be NO STUFF by default.
8. DQ and DQS signals must route at the same layer and have same width.

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Table 2-6. CFL-H DDR4 SO-DIMM 1DPC Length and Matching Guidelines
Length Matching (mils)
Signal
Rule Details Notes
Group
Minimum Maximum

CK[X] - CK#[X], where X = 0 or 1 -5 5 1,2

CLK
1,2
CK/CK#[1:0] (max - min) 0 40
1,2
CTRL/CKE (max - min) 0 200
CTRL/CKE
CK/CK#[1:0] - CTRL/CKE 0 100 1,2

1,2
CMD (max - min) 0 200
CMD
1,2
CK/CK#[1:0] - CMD -500 500

DQS[X] - DQS#[X], where X = 0 to 8 -5 5 1,2

Strobe
1,2
CK/CK#[1:0] - DQS/DQS#[X], where X = 0 to 8 -1500 2500
1,2,3
Data DQ(Byte[X]) - DQS/DQS#[X], where X 0 to 7 -20 20

Notes:
1. Length Matching = CPU Die to SO-DIMM Pin (PKG + BO1 + BO2 + M + BI, PKG + BO1 +BO2a + BO2b + M
+ BI); where a conversion factor of 0.9 must be used on Micro-Strip Segments to convert Micro-Strip lengths
to Strip-Line equivalent lengths.
2. To help facilitate and check the Length and Matching relationships on a design, refer the Automated Trace
Length Calculator Tools #568458.
3. Byte[0] = DQ[7:0], DQS/DQS#[0], Byte[1] = DQ[15:8], DQS/DQS#[1], Byte[2] = DQ[23:16], DQS/
DQS#[2], Byte[3] = DQ[31:24], DQS/DQS#[3], Byte[4] = DQ[39:32], DQS/DQS#[4], Byte[5] = DQ[47:40],
DQS/DQS#[5], Byte[6] = DQ[55:48], DQS/DQS#[6], Byte[7] = DQ[63:56], DQS/DQS#[7].

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2.3 CFL-H Mixed SoDIMM and Memory Down 2Rx8

Table 2-7. System Memory Configuration Details Covered in this Section
Parameter Details

Processor CFL-H

Memory Type DDR4

SoDIMM Channel = One SO-DIMMs

Configuration
MD Channel = x8 Memory Down (8 DRAM Devices for 2 Ranks)

Maximum Speed (MT/s) 2400

Channels 1 and 2

System Memory Voltage 1.2 V

Maximum Ranks Per Channel 2

DRAM Die Density (Gb) 4 and 8

Maximum Capacity (GB) 32

SO-DIMM Raw-Card Types RC-A(1Rx8),RC-E(2Rx8),RC-C(1Rx16)

Memory Down Types(1,2) 78-Ball BGA

(Pkg Ranks - Die Bits - Pkg bits) DDP 2-8-8

PCB Layers/Type(3) 10L/T3

SODIMM and DRAMs module placement Single side Top layer placement

Processor Memory Ball Map(4) Interleaved/Non-Interleaved (IL/NIL)

(5)
DRAM Device ODT Capability Enable

SoDIMM Channel:
Strobe/Data/CTRL/CLK/CKE/CMD = PKG+A+B+C+D
RCOMP = M
Memory Down Channel:
Total Maximum Length Strobe/Data = PKG+BO1+BO2+M+BI1
Reset = PKG+BO1+BO2+M+BI1+BI2
CLK = PKG+BO1+BO2+M1+M2+BI1+BI2
CTRL/CKE/CMD= PKG+BO1+BO2+M+BI1+BI2
RCOMP = M

Notes:
1. SDP: Single Die Package, DDP: Dual Die Package.
2. No mixed vendor support within a channel or channel to channel and No mixed memory DRAM down type
support (SDP, DDP) within a channel or channel to channel.
3. Type 3 (T3)= PCB with zero build-up layers using Plated Through-hole (PTH) Vias with no Micro-vias.
Refer “Stack-Up and PCB Considerations” chapter for more details in this document.
4. Non-Interleave = The processor is optimized for a side-by-side ball map and placement of the DRAM
memory down devices or DIMM Side-by-Side (inline) placement. Each memory channel’s signals are
grouped together on one side of the processor packages.
Interleave = The processor is optimized for a back-to-back ball map and placement of the DIMMs. Each
memory channel’s signals are grouped together on front or back side of the processor packages.
5. The DRAM Device ODT Capability can be enabled or disabled to read and write depending on the system
memory interface margins. Enabling the DRAM device ODT increases the memory interface power and
improves signal integrity/margins, while disabling the DRAM device ODT decreases the memory interface
power but degrades signal integrity/margins. For ODT implementation recommendation for this topology,
refer to Table 4-1.

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Figure 2-7. CFL-H DDR4 2Rx8 Memory Down Placement and Block Diagram

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Figure 2-8. CFL-H DDR4 SODIMM Signals Topology

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Figure 2-9. CFL-H DDR4 2Rx8 DDP Memory Down CLK/CKE/CMD/CTRL/Reset Signals
Topologies

Notes:
1. The alert signal must be routed in the opposite direction to the address/command bus. Example: The alert
signal must first connect to the last device that the address/command bus is connected to.
2. DRAM_RST CAP should have no stuffed.

Figure 2-10. CFL-H DDR4 2Rx8 DDP Memory Down DQ/DQS/RCOMP Signals

CFL‐H
DRAM
Strobe,  BO1 BO2 M BI1
Data

R
RCOMP M

For CFL H DDR4 Mixed SoDIMM and Memory Down 2Rx8 -SoDIMM Routing Guidelines,
refer to Table 2-5.

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For CFL H DDR4 Mixed SoDIMM and Memory Down 2Rx8 -SoDIMM Length and Matching
Guidelines, refer to Table 2-6.

Table 2-8. CFL-H DDR4 Mixed SoDIMM and Memory Down 2Rx8 - Memory Down Routing
Guideline (Sheet 1 of 3)

Target Impedance Minimum Trace Spacing Maximum (mils)

(Ω) (mils) Length

Trace Width
Layer Route

R (Ω±1%)
Reference

Via Count
Region

(mils)

Notes
C(uF)
Signal

Byte [1 and
Tolerance

Breakout
Group to
Group[1

Region
and 2]
Group

Single
Ended

Group

Total
(%)
Diff

Diff

2]
BO1 MS VSS 1 3 3.5 3.5 3.5 450
800
BO2 SL VSS 0 3.5 4 16 16 700

M1 SL VSS 0 6/6.5 72 ±10 4.5 16 16

4.5/
M2 SL VSS 0 5/5.5 16 16 1000
4 (R1) 36
[1st] (C1)
0.0033
6000 1,2,3,
CLK BI1 SL VSS 8 3 3.5 16 16 150 (C1-No
[Last] stuff) 7,8
10300
(C2) 0.01
BI2 SL VSS 0 4.5 85 ±10 4.5 16 16 700

T1 MS VSS 1 3 3.5 16 16 200

T2 SL VSS 0 4.5 85 ±10 4.5 16 16 300

T3 MS VSS 1 3 3.5 16 16 50

BO1 MS VSS 1 3 3.5 3.5 450

800
BO2 SL VSS 0 3.5 4 16 700

M SL VSS 0 5.5/7 40 ±10 5/6 16

[1st]
CTRL/ 6000
BI1 MS VSS 8 3 3.5 16 150 36 1,2,3
CKE [Last]
10300
BI2 SL VSS 0 4.5 50 ±10 6.5 16 700

T2 SL VSS 0 4.5 50 ±10 6.5 16 300

T3 MS VSS 1 3 3.5 16 50

BO1 MS VSS 1 3 3.5 3.5 450

800
BO2 SL VSS 0 3.5 4 16 700

4.5
M SL VSS 0 5.5/7 40 ±10 / 16
5.5 [1st]
6000
CMD 36 1,2,3
BI1 MS VSS 8 3 3.5 16 150 [Last]
10300

BI2 SL VSS 0 4.5 50 ±10 6.5 16 700

T2 SL VSS 0 4.5 50 ±10 6.5 16 300

T3 MS VSS 1 3 3.5 16 50

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Table 2-8. CFL-H DDR4 Mixed SoDIMM and Memory Down 2Rx8 - Memory Down Routing
Guideline (Sheet 2 of 3)

Target Impedance Minimum Trace Spacing Maximum (mils)

(Ω) (mils) Length

Trace Width
Layer Route

R (Ω±1%)
Reference

Via Count
Region

(mils)

Notes
C(uF)
Signal

Byte [1 and
Tolerance

Breakout
Group to
Group[1

Region
and 2]
Group

Single
Ended

Group

Total
(%)
Diff

Diff

2]
BO1 MS VSS 1 3 3.5 3.5 450
800
BO2 SL VSS 0 3.5 4 16 700

4.5
M SL VSS 0 5.5/7 40 ±10 / 16
5.5 [1st] (R1
connecte
6000
Alert d to 1,2,3
BI1 MS VSS 8 3 3.5 16 150 [Last] VDDQ)
10300 50

BI2 SL VSS 0 4.5 50 ±10 6.5 16 700

T2 SL VSS 0 4.5 50 ±10 6.5 16 300

T3 MS VSS 1 3 3.5 16 50

BO1 MS VSS 1 3 3.5 3.5 3.5 450

800
BO2 SL VSS 0 3.5 4 16 25 700
1,2,4,5
Strobe 4500 ,6,7,9
M SL VSS 0 4/4.5 85 50 ±10 4.5 16 25

BI1 SL VSS 1 3 3.5 16 25 150

BO1 MS VSS 1 3 3.5 3.5 3.5 450

800
BO2 SL VSS 0 3.5 4 16 25 700

1,2,4,5
Data 4.5 4500 ,6,9
M SL VSS 0 4/4.5 50 ±10 / 16 25
5.5

BI1 SL VSS 1 3 3.5 16 25 150

BO1 MS VSS 1 3 3.5 30

1000
BO2 SL VSS 0 3.5 20 1000
(R1) 470
Reset M SL VSS 1 4/4.5 50 ±10 20 8000
(R2)
3,8
0
(C1) 0.1
BI1 MS VSS 8 3 20

BI2 SL VSS 0 4.5 50 ±10 20

RCOMP MS/
M VSS 4 12-15 13 13 500 500 121
[0] SL

RCOMP MS/
M VSS 4 12-15 13 13 500 500 121
[1] SL

RCOMP MS/
M VSS 4 12-15 13 13 500 500 100
[2] SL

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Table 2-8. CFL-H DDR4 Mixed SoDIMM and Memory Down 2Rx8 - Memory Down Routing
Guideline (Sheet 3 of 3)

Target Impedance Minimum Trace Spacing Maximum (mils)

(Ω) (mils) Length

Trace Width
Layer Route

R (Ω±1%)
Reference

Via Count
Region

(mils)

Notes
C(uF)
Signal

Byte [1 and
Tolerance

Breakout
Group to
Group[1

Region
and 2]
Group

Single
Ended

Group

Total
(%)
Diff

Diff

2]
Notes:
1. Avoid any parallel routing between two adjacent layers.
2. Signals, while routed on inner PCB layers must be ground referenced with solid ground floods on both sides.
3. Use individual termination resistors (R1) for each signal. Do not use Rpacks.
4. For Option #1 (Single Rank) configuration there are only 8 DRAM Devices connected to each CMD Group Signal and only 1
DRAM Device connected to each Strobe/Data Group Signal. For these designs DRAM Devices [15:8] and their corresponding
BI1 routing segments need to be removed for each CMD Group Signal and the second DRAM Device and corresponding BI
routing segment needs to be removed for each Strobe/Data Group Signal.
5. The Strobe and Data Group Signals within the same byte must always route together on the same layers for their entire
route.
6. DQ Bit Swapping is allowed within the same byte, and Byte Swapping is allowed within the same channel.
7. Clock (CLK and CLK#) and Strobe (DQS and DQS#) differential signal swapping within a pair is not allowed.
8. Capacitor C1 is a defensive design and should be NO STUFF by default.
9. DQ and DQS signals must route at the same layer and have same width.

Table 2-9. CFL-H DDR4 2Rx8 DDP Memory Down Length Matching Guidelines 
(Sheet 1 of 2)
Length Matching (mils)
Signal
Rule Details Notes
Group
Minimum Maximum

BI1 (max - min) 0 50 2

CLK CK[0] - CK#[0]; 0 -5 5 1,2

CK/CK#[0] (max - min) 0 10 1,2

BI1 (max - min) 0 0 2,5

CTRL/CKE CTRL/CKE (max - min) 0 100 1,2

CK/CK#[0] - CTRL/CKE; 0 100 1,2,4

BI1 (max - min) 0 0 2,5

CMD CMD (max - min) 0 100 1,2

CK/CK#[0] - CMD; -500 500 1,2,4

BI1 (max – min) 0 0 2,6

Strobe DQS[X] - DQS#[X], where X = 0 to 7 -5 5 1,2

CK/CK#[0] - DQS/DQS#[Y], where Y = 0 to 7 -500 5500 1,2

BI (max-min) 0 0 2,6
Data
DQ (Byte[X]) - DQS/DQS#[X], where X = 0 to 7 -20 20 1,2,3

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Table 2-9. CFL-H DDR4 2Rx8 DDP Memory Down Length Matching Guidelines 
(Sheet 2 of 2)
Notes:
1. Length Matching = CPU Die to DRAM Ball of every DRAM Device (CLK =
PKG+BO1+BO2+M1+M2+BI1+BI2, CTRL/CKE/CMD = PKG+BO1+BO2+M+BI1+BI2, Strobe/Data =
PKG+BO1+BO2+M+BI1); where a conversion factor of 0.9 must be used on Micro-Strip Segments to
convert Micro-Strip lengths to Strip-Line equivalent lengths.
2. To facilitate and check the Length and Matching relationships on a design, refer to the Automated Trace
Lengths Calculator (ATLC #568458). Refer Table 1-2
3. Byte[0] = DQ[7:0], DQS/DQS#[0], Byte[1] = DQ[15:8], DQS/DQS#[1], Byte[2] = DQ[23:16], DQS/
DQS#[2], Byte[3] = DQ[31:24], DQS/DQS#[3], Byte[4] = DQ[39:32], DQS/DQS#[4], Byte[5] =
DQ[47:40], DQS/DQS#[5], Byte[6] = DQ[55:48], DQS/DQS#[6], Byte[7] = DQ[63:56], DQS/DQS#[7]
4. The delta between CLK signals to CMD/CTRL/CKE, between DRAMs should be kept < 20 mils. Example:
|DRAM[x] (CK[i]-Addr[j]) - DRAM[y](CK[i]-Addr[j])| < 20 mils.
5. This matching rule refer to all BI (Break-ins) sections that routed within each signal. Example: ADDR[0]
BI1 should be equal in all DRAMs. ADDR[1] BI1 should be equal in all DRAMs. ADDR[0] BI1 may not be
equal to ADDR[1] BI1.
6. DQ - BI should be matched within all bytes and not only within byte (max-min=0). DQ[63..0] BI section
should be equal. DQS - BI should be matched within all bytes and not only within bytes (max-
min=0).DQS[7..0][P/N] BI section should be equal. DQ and DQS BI does not need to be matched. Can
allow 50 mils difference. DQS-DQ<=50 mils.

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2.4 CFL-H DDR4 1R x16, T4 10L, Dual sided Memory

Down Guidelines
Table 2-10. System Memory Configuration Details Covered in this Section
Parameter Details

Processor CFL-H

Memory Type DDR4

Configuration Channel A = x16 Memory Down (4 DRAM Devices per channel)

Channel B = x16 Memory Down (4 DRAM Devices per channel)

Speed (MT/s) 2400

Channels 1 and 2

System Memory Voltage 1.2 V

Maximum Ranks Per Channel 1

DRAM Die Density (Gb) 8 and 4

Maximum Capacity (GB) SDP: 1R x16, 8 Gb - 8 GB

DDP: 1R x16, 8 Gb - 16 GB

Memory Down Types(1,2) 96-Ball BGA

(Pkg Ranks - Die Bits - Pkg bits) SDP 1-16-16, DDP 1-8-16

PCB Layers/Type(3) 10L/T4

SODIMM and DRAMS module placement Dual sided board. Each Channel is placed on a different side. Each
channel is Daisy Chain single sided

CPU System Memory Ball Map(4) Interleaved

DRAM Device ODT Capability(5) Enabled

Total Maximum Length Strobe/Data/Reset = PKG+BO1+M+BI

CLK/CTRL/CKE/CMD= PKG+BO1+M+BI1+BI2
RCOMP = M

Notes:
1. SDP: Single Die Package, DDP: Dual Die Package.
2. No mixed vendor support within a channel or channel to channel and No mixed memory DRAM down type
support (SDP, DDP) within a channel or channel to channel.
3. Type 4 (T4) (1-x-1+) = PCB with one build-up layer and two layers of Micro-vias.
Type 4 (T4) (2-x-2+) = PCB with two build-up layer and three layers of Micro-vias.
Refer “Stack-Up and PCB Considerations” chapter for more details.
4. Non-Interleave = The processor is optimized for a side-by-side ball map and placement of the DRAM memory
down devices or DIMM Side-By-Side (inline) placement. Each memory channel’s signals are grouped together
on one side of the processor packages.
Interleave = The processor is optimized for a back-to-back ball map and placement of the DIMMs. Each
memory channel’s signals are grouped together on front or back side of the processor packages.
5. The DRAM Device ODT Capability can be enabled or disabled to read and write depending on the system
memory interface margins. Enabling the DRAM device ODT increases the memory interface power and
improves signal integrity/margins, while disabling the DRAM device ODT decreases the memory interface
power but degrades signal integrity/margins. For ODT implementation recommendation for this topology.
Refer to Table 4-1.

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Figure 2-11. CFL-H DDR4 x16 T4 10L Dual sided Memory Down Placement and Block
Diagram

Figure 2-12. CFL-H DDR4 x16 T4 10L Dual sided Memory Down Strobe/Data/RCOMP Signal
Topologies

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 CFL-H Memory Interface White Paper

Figure 2-13. CFL-H DDR4 x16 T4 10L Dual sided Memory Down CLK/CTRL/CKE/CMD/Reset
Signal Topology

Notes:
1. The alert signal must be routed in the opposite direction to the address/command bus. Example: The alert
signal must first connect to the last device that the address/command bus is connected to.
2. DRAM_RST C1 capacitor should not be installed.
3. For SDP, BG1 should be left open.
4. For DDP, BG1 should be connected to the DRAM.

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Table 2-11. CFL-H DDR4 x16 T4 10L Dual sided Memory Down Routing Guideline 
(Sheet 1 of 2)

Target Impedance Minimum Trace Spacing Maximum

(Ω) (mils) (mils) Length

Trace Width
Layer Route

R (Ω±1%)
Reference

Via Count
Region

(mils)

Notes
C(uF)
Signal

Byte [1 and
Tolerance

Group[1
Group to

Region
Group

and 2]
Ended

Group
Single

Total
(%)
Diff

Diff

2]
BO1 SL VSS 0 3 3 6 6 450

M1 SL VSS 0 4 72 ±10 4 16 16
(R1) 36
(C1)
M2 SL VSS 0 4 4 16 16 1000 [1st] 0.0033
6000 1,2,3,
CLK (C1-no
[Last] 7,8
stuff)
BI1 SL VSS 8 3 3 16 16 120 8000 (C2)
0.01
BI2 SL VSS 0 3 86 ±10 5 16 16 700

T1 MS VSS 1 3 3.5 16 16 150

T2 SL VSS 0 3 86 ±10 5 16 16 300

BO1 SL VSS 0 3 6 16 450

M SL VSS 0 3.5 40 ±10 6 16

[1st]
6000 36 1,2,3
CTRL/CKE BI1 MS VSS 8 3 3.5 16 120
[Last]
8000
BI2 SL VSS 0 2.5 50 ±10 8 16 700

T2 SL VSS 0 2.5 50 ±10 8 16 300

BO1 SL VSS 0 3 6 16 450

M SL VSS 0 3.5 40 ±10 6 16

[1st]
6000 1,2,3,
CMD BI1 MS VSS 8 3 3.5 16 120 36
[Last] 13
8000
BI2 SL VSS 0 2.5 50 ±10 8 16 700

T2 SL VSS 0 2.5 50 ±10 8 16 300

BO1 SL VSS 0 2.5 3 16 25 450

1,2,4,5
Strobe
M SL VSS 0 2.5 86 ±10 3 16 25 4500 ,6,7,9,
10
BI1 SL VSS 1 2.5 3 16 25 120

BO1 SL VSS 0 2.5 6 16 25 450

1,2,4,5
Data M SL VSS 0 2.5 48 ±10 6 16 25 4500 ,6,9,10

BI1 SL VSS 1 2.5 4 16 25 120

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Table 2-11. CFL-H DDR4 x16 T4 10L Dual sided Memory Down Routing Guideline 
(Sheet 2 of 2)

Target Impedance Minimum Trace Spacing Maximum

(Ω) (mils) (mils) Length

Trace Width
Layer Route

R (Ω±1%)
Reference

Via Count
Region

(mils)

Notes
C(uF)
Signal

Byte [1 and
Tolerance

Group[1
Group to

Region
and 2]
Group

Ended

Group
Single

Total
(%)
Diff

Diff

2]
BO1 SL VSS 0 2.5 6 16 25 600

M SL VSS 0 2.5 48 ±10 8 16 25 [1st]

6000 (R1
connected
[Last] to 1,2,3
Alert BI1 SL VSS 1 2.5 4 16 25 150
8000 VDDQ)50

BI2 SL VSS 0 2.5 48 ±10 8 16 700

T2 SL VSS 0 2.5 48 ±10 6.5 16 300

BO1 SL VSS 0 2.5 20 1000

(R1)
470
M SL VSS 1 2.5 48 ±10 20
(R2)
Reset 8000 3,8
0
BI1 SL VSS 8 2.5 20 (C1)
0.1
BI2 SL VSS 0 2.5 48 ±10 20

RCOMP[0] MS/ 121

M VSS 4 12-15 13 13 500 500
SL

RCOMP[1] MS/ 121 1,2

M VSS 4 12-15 13 13 500 500
SL

RCOMP[2] MS/ 100

M VSS 4 12-15 13 13 500 500
SL

Notes:
1. Avoid any parallel routing between two adjacent layers.
2. Signals, while routed on inner PCB layers must be ground referenced with solid ground floods on both sides.
3. Use individual termination resistors (R1) for each signal. Do not use Rpacks.
4. For Option #1 (Single Rank) configuration, there are only 8 DRAM Devices connected to each CMD Group Signal and only
1 DRAM Device connected to each Strobe/Data Group Signal. For these designs DRAM Devices [15:8] and their
corresponding BI1 routing segments need to be removed for each CMD Group Signal and the second DRAM Device and
corresponding BI routing segment needs to be removed for each Strobe/Data Group Signal.
5. The Strobe and Data Group Signals within the same byte must always route together on the same layers for their entire
route.
6. DQ Bit Swapping is allowed within the same byte, and Byte Swapping is allowed within the same channel.
7. Clock (CLK and CLK#) and Strobe (DQS and DQS#) differential signal swapping within a pair is not allowed.
8. Capacitor C1 is a defensive design and should be NO STUFF by default.
9. DQ and DQS signals must route at the same layer and have same width.
10. Route 2 adjacent bytes to same DRAM device - like DRAM0 (BYTE0,1) DRAM1 (BYTE 2,3), for better VREF training per
DRAM device.
11. Impedance numbers are for reference only, it is calculating according to the stackup layers thickness, the material
conductivity, traces spacing and width. The recommendation is to follow stackup and traces geometries.
12. For DDP BG[1] should be connected.

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Table 2-12. CFL-H DDR4 x16 T4 10L, Dual sided Memory Down Length Matching Guidelines

Length Matching (mils) Notes

Signal
Rule Details
Group
Minimum Maximum

BI1 (max - min) 0 50 2

CLK CK[X] - CK#[X]; where X = 0 or 1 -5 5 1,2

CK/CK#[1:0] (max - min) 0 10 1,2

BI1 (max - min) 0 0 2,5

CTRL/CKE CTRL/CKE (max - min) 0 100 1,2

CK/CK#[X] - CTRL/CKE; where X = 0 or 1 0 100 1,2,4

BI1 (max - min) 0 0 2,5

CMD CMD (max - min) 0 100 1,2

CK/CK#[0] - CMD; where X = 0 or 1 -500 500 1,2,4

BI1 (max – min) 0 0 2,6

DQS[X] - DQS#[X], where X = 0 to 7 -5 5 1,2

Strobe
CK/CK#[X] - DQS/DQS#[Y], where X = 0 or 1 and Y = -500 3500 1,2
0 to 7

BI (max-min) 0 0 2,6
Data
DQ (Byte[X]) - DQS/DQS#[X], where X = 0 to 7 -20 20 1,2,3

Notes:
1. Length Matching = CPU Die to DRAM Ball of every DRAM Device (CLK =
PKG+BO1+BO2+M1+M2+BI1+BI2, CTRL/CKE/CMD = PKG+BO1+BO2+M+BI1+BI2, Strobe/Data =
PKG+BO1+BO2+M+BI1); where a conversion factor of 0.9 must be used on Micro-Strip Segments to
convert Micro-Strip lengths to Strip-Line equivalent lengths.
2. To facilitate and check the Length and Matching relationships on a design, refer to Automated Trace
Length Calculator (# 568458).
3. Byte[0] = DQ[7:0], DQS/DQS#[0], Byte[1] = DQ[15:8], DQS/DQS#[1], Byte[2] = DQ[23:16], DQS/
DQS#[2], Byte[3] = DQ[31:24], DQS/DQS#[3], Byte[4] = DQ[39:32], DQS/DQS#[4], Byte[5] =
DQ[47:40], DQS/DQS#[5], Byte[6] = DQ[55:48], DQS/DQS#[6], Byte[7] = DQ[63:56], DQS/DQS#[7]
4. The delta between CLK signals to CMD/CTRL/CKE, between DRAMs should be kept < 20 mils. Example:
|DRAM[x] (CK[i]-Addr[j]) - DRAM[y](CK[i]-Addr[j])| < 20 mils.
5. This matching rule refer to all Break-ins (BI) sections that routed within each signal. Example:ADDR[0]
BI1 should be equal in all DRAMs. ADDR[1] BI1 should be equal in all DRAMs. ADDR[0] BI1 may not be
equal to ADDR[1] BI1.
6. DQ - BI should be matched within all bytes and not only within byte (max-min=0). DQ[63..0] BI section
should be equal. DQS - BI should be matched within all bytes and not only within bytes (max-min=0).
DQS[7..0][P/N] BI section should be equal. DQ and DQS BI does not need to be matched. Can allow 50
mils difference. DQS-DQ<=50 mils.

§§

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3 CFL-S Memory Interface White

Paper

3.1 CFL-S DDR4 SoDIMM 1DPC NIL Guidelines

Table 3-1. System Memory Configuration Details Covered in this Section
Parameter Details

Processor CFL-S

Memory Type DDR4

Channel A = One SoDIMM

Configuration
Channel B = One SoDIMM

Speed (MT/s) 2133

Channels 1 and 2

System Memory Voltage 1.2 V

Maximum Ranks Per Channel 2

DRAM Die Density (Gb) 4 and 8

Maximum Capacity (GB) 32

SO-DIMM Raw-Card Types RC-A (1Rx8),RC-B (2Rx8),RC-E (2Rx8),RC-C (1Rx16)

PCB Layers/Type(1) 4L/T3

Single side Top layer placement

SODIMM module placement
DIMMs placed side by side (inline)

Processor Memory Ball Map(2) Non-Interleaved

DRAM Device ODT Capability(3) Enable

Strobe/Data/CTRL/CLK/CKE/CMD = PKG+A+B+C+D+E
Total Maximum Length
Reset = PKG+A+B+C+D+E+F

Notes:
1. Type 3 (T3)= PCB with zero build-up layers using Plated Through-hole (PTH) Vias with no Micro-vias.
Refer “Stack-Up and PCB Considerations” chapter for more details in this document.
2. Non-Interleave = The processor is optimized for a side-by-side ball map and placement of the DRAM
memory down devices or DIMM Side-by-Side (inline) placement. Each memory channel’s signals are
grouped together on one side of the processor packages.
Interleave = The processor is optimized for a back-to-back ball map and placement of the DIMMs. Each
memory channel’s signals are grouped together on front or back side of the processor packages.
3. The DRAM Device ODT Capability can be enabled or disabled for reads and writes depending on the system
memory interface margins. Enabling the DRAM device ODT increases the memory interface power and
improves signal integrity/margins while disabling the DRAM device ODT decreases the memory interface
power but degrades signal integrity/margins. For ODT implementation recommendation for this topology,
refer to Table 4-1.

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Figure 3-1. CFL-S DDR4 1DPC SoDIMM T3/4L Inline NIL Placement and Block Diagram

CFL S

DDR0_CLK[1:0] DDR1_CLK[1:0]
DDR0_CS[1:0] DDR1_CS[1:0]
DDR0_CKE[1:0] DDR1_CKE[1:0]
DDR0_ODT[1:0] DDR1_ODT[1:0]
DDR0_CMD DDR1_CMD
DDR0_Alert DDR1_Alert
DDR0_DQ DDR1_DQ
DDR0_DQS DDR1_DQS

Ch A SO‐DIMM Ch B SO‐DIMM

Figure 3-2. CFL-S DDR4 SoDIMM 1DPC Signals Topology

CHx 
CFL‐S DIMM0
CLK, CTRL, A B C D E
CMD, Alert,
Data, Strobe

Figure 3-3. CFL-S DDR4 SoDIMM 1DPC DDR Reset Topology

CH0 CH1
 DIMM0  DIMM0

VDDQ
CFL‐S R1 E E

R2
DDR Reset A B C D F
C1

Note: DRAM_RST CAP should have no stuff.

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Table 3-2. CFL-S DDR4 SoDIMM 1DPC 4L Routing Guidelines (Sheet 1 of 2)

Target Minimum Trace Spacing Maximum (mils)

MB Layer Route
Impedance (Ω) (mils)
Length

Trace Width

R (Ω±1%)
Reference

Via Count
Region

(mils)

Notes
Signal

Byte [1 and
Tolerance

Group to
Group[1

Region
and 2]
Group

Ended

Group
Single

Total
[%]
Diff

Diff

2]
VSS/
A 1 0 3.5 4 4.5 4.5 25
VCC

VSS/
B 1,4 0/1 3.5 4 6.5 6.5 75
VCC

VSS/ 1,2,3,
CLK C 1,4 1/0 3.5 4 15.5 15.5 400 5000
VCC 4

VSS/
D 1,4 0/1 8 62 ±15 5 20 20
VCC

VSS/
E 1 0/1 8 62 ±15 5 20 20 1000
VCC

VSS/
A 1 0 3.5 4.5 4.5 100
VCC

VSS/
B 1,4 0/1 3.5 6.5 6.5 150
VCC

VSS/ 2,5,6,
CTRL/CKE C 1,4 1/0 3.5 8.5 8.5 150 5000
VCC 7,8,9

VSS/
D 1,4 0/1 6.5 40 ±15 9.5 9.5
VCC

VSS/
E 1 0/1 6.5 40 ±15 8.5 8.5 1000
VCC

VSS/
A 1 0 3.5 4.5 4.5 100
VCC

VSS/
B 1,4 0/1 3.5 6.5 6.5 150
VCC

VSS/ 2,6,7,
CMD/Alert C 1,4 1/0 3.5 8.5 8.5 150 5000
VCC 9,10

VSS/
D 1,4 0/1 8.5 35 ±15 6.5 5.5
VCC

VSS/
E 1 0/1 6.5 40 ±15 8.5 8.5 750
VCC

4.5/
A 1 VSS 0 3.5 4 15 75
15

6.5/
B 1,4 VSS 0/1 3.5 4 15 150
15

10.5 2,6,7,
C 1,4 VSS 1/0 3.5 4 18.5 / 375 11,12
Strobe 5000 ,13,
18.5
14

15.5
D 1,4 VSS 0/1 6.5 62 ±15 5 18.5 /
18.5

E 1 VSS 0/1 6.5 62 ±15 5 18.5 15.5 750

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Table 3-2. CFL-S DDR4 SoDIMM 1DPC 4L Routing Guidelines (Sheet 2 of 2)

Target Minimum Trace Spacing Maximum (mils)

MB Layer Route
Impedance (Ω) (mils)
Length

Trace Width

R (Ω±1%)
Reference

Via Count
Region

(mils)

Notes
Signal

Byte [1 and
Tolerance

Group to
Group[1

Region
Group

and 2]
Ended

Group
Single

Total
[%]
Diff

Diff

2]
4.5/
A 1 VSS 0 3.5 4.5 15 75
15

6.5/
B 1,4 VSS 0/1 3.5 6.5 15 150
15

10.5 2,6,7,
C 1,4 VSS 1/0 3.5 10.5 18.5 / 375 11,12
Data 5000 ,13,
18.5
14

15.5
D 1,4 VSS 0/1 6.5 40 ±15 18.5 18.5 /
18.5

E 1 VSS 0/1 6.5 40 ±15 15.5 18.5 15.5 750

VSS/
A 1,4 0/1 3.5 4.5 75
VCC

VSS/
B 1,4 0/1 3.5 6.5 200
VCC
(R1)
VSS/ 470
C 1,4 0/1 3.5 8.5
VCC
(R2)
Reset 8000 15,16
VSS/ 0
D 1,4 0/1 4 8.5
VCC
(C1)
VSS/ 0.1
E 1,4 0/1 4 8.5
VCC

VSS/
F 1,4 0/1 4 8.5
VCC

Notes:
1. In a One DIMM per Channel memory layout implementation, designers must either route the DIMM0 specific Clock (CK/
CK#[1:0]) signals or the DIMM1 specific Clock(CK/CK#[3:2]) signals to the single DIMM within a channel. Make sure the
DIMM Clock specific signals not routed to the single DIMM are test pointed on the motherboard and left as no connects.
2. For every transition, signal via the processor break-out regions, a ground via must be placed a maximum of one grid
distance away. If needed, it is acceptable to share a ground via between two transition signal vias.
3. The trace widths in these segments are for reference ONLY. The controlling specification is the trace impedance.
4. Strongly recommend that designs increase the Isolation Spacing in the Break Out Regions A, B, and C as much as possible
and get to the Main Segment Region D as quickly as possible.
5. In a One DIMM per Channel memory layout implementation, designers must route the Control signals associated with the
specific DIMM Clocks routed to the single DIMM within a channel (CS#/CKE/ODT[1:0] to CK/CK#[1:0], CS#/CKE/ODT[3:2]
to CK/CK#[3:2]). Make sure the DIMM specific Control signals not routed to the single DIMM are test pointed on the
motherboard and left as no connects.
6. The trace widths in these segments are for reference ONLY. The controlling specification is the trace impedance.
7. Strongly recommend that designs increase the Spacing in the Break Out Regions A, B, and C as much as possible and get
to the Main Segment Region D as quickly as possible.
8. If needed a minimum Control to Control trace spacing of 10 mils and a minimum Control to Command/address isolation
spacing of 10.25 mils are allowed for Region D but for no more than 300 mils maximum.
9. Region E must utilize three track routing with only two near aggressors. If needed, a minimum trace spacing of 4.5 mils is
allowed in Region E but the total combined length of reduced trace spacing must be less than 100 mils maximum.
10. Region E must utilize three track routing with only two near aggressors. If needed a minimum trace spacing of 4.5 mils is
allowed in Region E but the total combined length of reduced trace spacing must be less than 100 mils maximum.
11. For platforms that donot support ECC the DQS[8], DQS#8 and DQ[71:64] pins must be left as no connect at the processor
side.
12. Data bit swapping within a byte lane in the same channel is allowed.
13. Regions E must utilize 2 track routing with only 1 near aggressor.
14. The Signal/Trace Reference can be power or ground but they must maintain the same reference and not cross any plane
splits.
15. Capacitor C1 is a defensive design and should have NO STUFF by default.
16. Impedance numbers are for reference only, it is calculated according to the stackup layers thickness. The material
conductivity, traces spacing and width. The recommendation is to follow stackup and traces geometries.

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Table 3-3. CFL-S DDR4 SoDIMM 1DPC 4L Lengths Matching Guidelines

\

Length Matching (mils)

Signal
Rule Details Notes
Group
Min Max
1,2
CK[X] - CK#[X], where X = 0 or 1 -5 5
CLK
1,2
CK/CK#[1:0] (max - min) 0 10

CTRL/CKE (max - min) 0 50 1,2

CTRL/CKE
1,2
CK/CK#[1:0] - CTRL/CKE -150 0
1,2
CMD (max - min) 0 100
CMD
CK/CK#[1:0] - CMD -250 250 1,2

1,2
DQS[X] - DQS#[X], where X = 0 to 7 -5 5
Strobe
1,2
CK/CK#[1:0] - DQS/DQS#[X], where X = 0 to 7 -1000 500

Data DQ (Byte[X]) - DQS/DQS#[X], where X = 0 to 7 -20 20 1,2,3

Notes:
1. Length Matching = CPU Die to SO-DIMM Pin (PKG+A+B+C+D+E); where a conversion factor of 0.9 must
be used on Micro-Strip Segments to convert Micro-Strip lengths to Strip-Line equivalent lengths. Keep the
signal Die to SODIMM Total Lengths for each signal, as short as possible.
2. To help facilitate and check the Length and Matching relationships on a design, refer to the Automated
Trace Length Calculator (# 568458). Refer Table 1-2.
3. Byte[0] = DQ[7:0], DQS/DQS#[0], Byte[1] = DQ[15:8], DQS/DQS#[1], Byte[2] = DQ[23:16], DQS/
DQS#[2], Byte[3] = DQ[31:24], DQS/DQS#[3], Byte[4] = DQ[39:32], DQS/DQS#[4], Byte[5] =
DQ[47:40], DQS/DQS#[5], Byte[6] = DQ[55:48], DQS/DQS#[6], Byte[7] = DQ[63:56], DQS/DQS#[7]

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3.2 CFL-S DDR4 Mixed SODIMM and Memory Down

x16
Table 3-4. System Memory Configuration Details
Parameter Details

Processor CFL-H

Memory Type DDR4

One Channel = One SO-DIMM

Configuration
One Channel = Four DRAM devices of x16 Memory Down

Speed (MT/s) 2133

Channels 2

System Memory Voltage 1.2 V

SoDIMM Channel - 2 Ranks

Maximum Ranks Per Channel
Memory down channel - 1 Rank

DRAM Die Density (Gb) 4 and 8

Maximum Capacity (GB) 20 GB, SODIMM 16 GB + Memory Down 4 Devices of 1 GB

SO-DIMM Raw-Card Types RC-A (1Rx8), RC-C (1Rx16), RC-E (2Rx8)

Memory Down Types(4, 5)

96-Ball BGA SDP 1-16-16
(Pkg Ranks - Die Bits - Pkg bits)

PCB Layers/Type(1) 8L/T3

Top Motherboard Layer, Single Sided, Channels are Back-to-Back

SODIMM module Placement
Placement, Memory Down x16 Daisy-Chain Topology

Processor Memory Ball Map(2) Interleaved

(3)
DRAM Device ODT Capability Enable

SoDIMM Channel:
Strobe/Data/CTRL/CLK/CKE/CMD = PKG+A+B+C+D
RCOMP = M
Total Maximum Length Memory Down Channel:
Strobe/Data = PKG+BO1+BO2+M+BI1+BI2
CTRL/CLK/CKE/CMD = PKG+BO1+BO2+M+BI1+BI2+BI3
RCOMP = M

Notes:
1. Type 3 (T3)= PCB with zero build-up layers using Plated Through-hole (PTH) Vias with no Micro-vias.
Refer “Stack-Up and PCB Considerations” chapter for more details in this document.
2. Non-Interleave = The processor is optimized for a side-by-side ball map and placement of the DRAM
memory down devices or DIMM Side-by-Side (inline) placement. Each memory channel’s signals are
grouped together on one side of the processor packages.
Interleave = The processor is optimized for a back-to-back ball map and placement of the DIMMs. Each
memory channel’s signals are grouped together on front or back side of the processor packages.
3. The DRAM Device ODT Capability can be enabled or disabled for reads and writes depending on the system
memory interface margins. Enabling the DRAM device ODT increases the memory interface power and
improves signal integrity/margins, while disabling the DRAM device ODT decreases the memory interface
power but degrades signal integrity/margins. For ODT implementation recommendation for this topology.
Refer to Table 4-1.
4. SDP: Single Die Package, DDP: Dual Die Package.
5. No mixed vendor support within a channel or channel to channel and No mixed memory DRAM down type
support (SDP, DDP) within a channel or channel to channel.

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 CFL-S Memory Interface White Paper

Figure 3-4. CFL-S DDR4 Mixed SODIMM and Memory Down x16 Placement and Block
Diagram

CFL S
Ch B 
Ch B  CLK/CTRL/
Data Bytes CKE/CMD/
Alert
Channel B SO‐DIMM

Ch A Data Bytes

ChA  ChA  ChA  ChA 

DRAM 3 DRAM 2 DRAM 1 DRAM 0
Reset

Ch A CLK/CTRL/CKE/CMD/Alert

Figure 3-5. CFL-S DDR4 SODIMM Signals Topology

CHx DIMM0
CFL‐S
CLK, CTRL, A B C D
CMD, Alert,
Data, Strobe

Figure 3-6. CFL-S DDR4 1Rx16 Memory Down Strobe/Data/RCOMP Signal Topologies

CFL‐S

Strobe,  BO1 BO2 M BI1

Data

R
RCOMP M

40 Intel Confidential 573583

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Figure 3-7. CFL-S DDR4 1Rx16 Memory Down CLK/CTRL/CKE/CMD/Reset Signal

Topology

Notes:
1. The alert signal must be routed in the opposite direction to the address/command bus. Example: The alert
signal must first connect to the last device that the address/command bus is connected to.
2. DRAM_RST CAP should have no stuff.

Table 3-5. CFL-S DDR4 Mixed SODIMM and Memory down x16 - SODIMM Routing
Guidelines (Sheet 1 of 3)
Target Minimum Trace Spacing Maximum (mils)
MB Layer Route

Impedance (Ω) (mils)

Length
Trace Width

R (Ω±1%)
Reference

Via Count
Region

(mils)

Notes
Group[1/2]

Signal
Byte [1/2]
Tolerance

Group to

Region

Group
Ended

Group
Single

Total
[%]
Diff

Diff

A MS/SL VSS/VCC 0 4 4 4.5 4.5 A≤ 300

B ≤ 600
A+B ≤
B SL VSS/VCC 0/1 3.5 4 15 15 650
1,2,3,
CLK 4800 4
16/
C SL VSS/VCC 0/1 3.5 88 ±10 3.5 16
25

D MS VSS/VCC 1 4 4 15 15 200

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 CFL-S Memory Interface White Paper

Table 3-5. CFL-S DDR4 Mixed SODIMM and Memory down x16 - SODIMM Routing
Guidelines (Sheet 2 of 3)
Target Minimum Trace Spacing Maximum (mils)

MB Layer Route
Impedance (Ω) (mils)
Length

Trace Width

R (Ω±1%)
Reference

Via Count
Region

(mils)

Notes
Group[1/2]
Signal

Byte [1/2]
Tolerance

Group to

Region
Group

Ended

Group
Single

Total
[%]
Diff

Diff
A MS/SL VSS/VCC 0 4 4 4 A≤ 300
B ≤ 600
A+B ≤
B SL VSS/VCC 0/1 3.5 4 4 650
2,5,6,
CTRL/CKE 4800 7,8,9
16/
C SL VSS/VCC 0/1 6 39 ±10 12
25

D MS VSS/VCC 1 4 6 12 200

A MS/SL VSS/VCC 0 4 4 4 A≤ 300

B ≤ 600
A+B ≤
B SL VSS/VCC 0/1 3.5 4 4 650
2,6,7,
CMD 4800 9
16/
C SL VSS/VCC 0/1 6 39 ±10 12
25

D MS VSS/VCC 1 4 6 12 200

A MS/SL VSS/VCC 0 4 4 A≤ 300

B ≤ 600
A+B ≤
B SL VSS/VCC 0/1 3.5 4 650
2,6,7,
ALERT 4800 9
C SL VSS/VCC 0/1 6 39 ±10 25

D MS VSS/VCC 1 4 12 200

A MS/SL VSS 0 4 4 /12 4/12 A≤ 300

B ≤ 600
A+B ≤
B SL VSS 0/1 3.5 4 /12 5/12 650 2,6,7,
10,11
Strobe 4800 ,12,
16/
C SL VSS 0/1 3.5 88 ±10 3.5 /25 13,16
25

10/
D MS VSS 1 4 4 /16 85
16

A MS/SL VSS 0 4 4 /12 4/12 A≤ 300

B ≤ 600
A+B ≤
B SL VSS 0/1 3.5 5 /12 5/12 650 2,6,7,
10,11
Data 4800 ,12,
16/
C SL VSS 0/1 3.5 50 ±10 10 /25 13,16
25

10/
D MS VSS 1 4 10 /16 85
16

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CFL-S Memory Interface White Paper

Table 3-5. CFL-S DDR4 Mixed SODIMM and Memory down x16 - SODIMM Routing
Guidelines (Sheet 3 of 3)
Target Minimum Trace Spacing Maximum (mils)

MB Layer Route
Impedance (Ω) (mils)
Length

Trace Width

R (Ω±1%)
Reference

Via Count
Region

(mils)

Notes
Group[1/2]
Signal

Byte [1/2]
Tolerance

Group to

Region
Group

Ended

Group
Single

Total
[%]
Diff

Diff
Notes:
1. In a One DIMM per Channel memory layout implementation, designers must either route the DIMM0 specific Clock (CK/
CK#[1:0]) signals or the DIMM1 specific Clock(CK/CK#[3:2]) signals to the single DIMM within a channel. Make sure the
DIMM Clock specific signals not routed to the single DIMM are test pointed on the motherboard and left as no connects.
2. For every transition signal via in the processor break-out regions, a ground via must be placed at maximum of one grid
distance away. If needed, it is acceptable to share a ground via between two transition signal vias.
3. The trace widths in these segments are for reference ONLY. The controlling specification is the trace impedance.
4. Strongly recommend that designs increase the Isolation spacing in the Break Out Regions A, B, and C as much as possible
and get to the Main Segment Region D as quickly as possible.
5. In a One DIMM per Channel memory layout implementation, designers must route the Control signals associated with the
specific DIMM Clocks routed to the single DIMM within a channel (CS#/CKE/ODT[1:0] to CK/CK#[1:0], CS#/CKE/ODT[3:2]
to CK/CK#[3:2]). Make sure the DIMM specific Control signals not routed to the single DIMM are test pointed on the
motherboard and left as no connects.
6. The trace widths in these segments are for reference ONLY. The controlling specification is the trace impedance.
7. Strongly recommend that designs increase the Spacing in the Break Out Regions A, B, and C as much as possible and get
to the Main Segment Region D as quickly as possible.
8. If needed a minimum Control to Control trace spacing of 10 mils and a minimum Control to Command/address isolation
spacing of 10.25 mils are allowed for Region D but for not more than 300 mils maximum.
9. Region E must utilize three track routing with only two near aggressors. If needed a minimum trace spacing of 4.5 mils is
allowed in Region E but the total combined length of reduced trace spacing must be less than 100 mils maximum.
10. The DDR4 Data Mask DM[8:0] pins of all DDR4 DIMM connectors must be tied directly to VDDQ.
11. For platforms that donot support ECC, the DQS[8], DQS#[8] and DQ[71:64] pins must be left as no connection at the
processor side.
12. Data bit swapping within a byte lane in the same channel is allowed.
13. Regions E must utilize 2 track routing with only 1 near aggressor.
14. The Signal/Trace Reference can be powered or grounded but they must maintain the same reference and not cross any
plane splits.
15. Capacitor C1 is a defensive design and should have NO STUFF by default.
16. DQ and DQS must have the same widths.
17. Impedance numbers are for reference only, it is calculated according to the stackup layers thickness. The material
conductivity, traces spacing and width. The recommendation is to follow stackup and traces geometries.

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 CFL-S Memory Interface White Paper

Table 3-6. CFL-S DDR4 Mixed SODIMM and Memory down x16 - Memory Down Routing
Guideline (Sheet 1 of 3)

Target Impedance Minimum Trace Spacing Maximum (mils)

(Ω) (mils) Length

Trace Width
Layer Route

R (Ω±1%)
Reference

Via Count
Region

(mils)

Notes
C(uF)
Signal

Byte [1 and
Tolerance

Breakout
Group[1
Group to

Region
Group

and 2]
Ended

Group
Single

Total
(%)
Diff

Diff

2]
BO1 MS VSS 1 4 4 4.5 4.5 300
650
BO2 SL VSS 0 3.5 4 15 15 600

M1 SL VSS 0 6/6.5 72 ±10 4.5 16 16

4.5/ (R1)
M2 SL VSS 0 5/5.5 16 16 1000 36
4 [1st]
(C1)
6000
0.0033 1,2,3,
CLK BI1 SL VSS 8 3 3.5 16 16 150 (C1-no 6,7
[Last] stuff)
8000 (C2)
BI2 SL VSS 0 4.5 85 ±10 4.5 16 16 700
0.01

T1 MS VSS 1 3 3.5 16 16 200

T2 SL VSS 0 4.5 85 ±10 4.5 16 16 300

T3 MS VSS 1 3 3.5 16 16 50

BO1 MS VSS 1 4 4 4 300

650
BO2 SL VSS 0 3.5 4 4 600

M SL VSS 0 5.5/7 40 ±10 5/6 16

[1st]
6000
CTRL/
BI1 MS VSS 8 3 3.5 16 150 36 1,2,3
CKE
[Last]
8000
BI2 SL VSS 0 4.5 50 ±10 6.5 16 700

T2 SL VSS 0 4.5 50 ±10 6.5 16 300

T3 MS VSS 1 3 3.5 16 50

BO1 MS VSS 1 4 4 4 300

650
BO2 SL VSS 0 3.5 4 4 600

4.5/
M SL VSS 0 5.5/7 40 ±10 16
5.5 [1st]
6000
CMD BI1 MS VSS 8 3 3.5 16 150 36 1,2,3
[Last]
8000
BI2 SL VSS 0 4.5 50 ±10 6.5 16 700

T2 SL VSS 0 4.5 50 ±10 6.5 16 300

T3 MS VSS 1 3 3.5 16 50

44 Intel Confidential 573583

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Table 3-6. CFL-S DDR4 Mixed SODIMM and Memory down x16 - Memory Down Routing
Guideline (Sheet 2 of 3)

Target Impedance Minimum Trace Spacing Maximum (mils)

(Ω) (mils) Length

Trace Width
Layer Route

R (Ω±1%)
Reference

Via Count
Region

(mils)

Notes
C(uF)
Signal

Byte [1 and
Tolerance

Breakout
Group[1
Group to

Region
and 2]
Group

Ended

Group
Single

Total
(%)
Diff

Diff

2]
BO1 MS VSS 1 4 4 /12 4/12 300
650
BO2 SL VSS 0 3.5 4 /12 5/12 600 1,2,4,
Strobe 4500 5,6,8,
M SL VSS 0 4/4.5 85 ±10 4.5 16 25 9

BI1 SL VSS 1 3 3.5 16 25 150

BO1 MS VSS 1 4 4 /12 4/12 300

650
BO2 SL VSS 0 3.5 5 /12 5/12 600
1,2,4,
Data 4.5/ 4500
5,8,9
M SL VSS 0 4/4.5 50 ±10 16 25
5.5

BI1 SL VSS 1 3 3.5 16 25 150

BO1 MS VSS 1 4 3.5 4 300

650
BO2 SL VSS 0 3.5 4 4 600

4.5/
M SL VSS 0 4/4.5 50 ±10 16
5.5 [1st] (R1
6000 connec
Alert BI1 MS VSS 0 3 3.5 16 150 ted to 1,2,3
[Last] VDDQ)
8000 50
BI2 SL VSS 0 4.5 50 ±10 6.5 16 700

T2 SL VSS 0 4.5 50 ±10 6.5 16 300

T3 MS VSS 1 3 3.5 16 50

MS/
BO1 VSS 1 3 3.5 75
SL
250
BO2 SL VSS 0 3.5 20 200 (R1)
470
(R2)
Reset M SL VSS 1 3.5 50 ±10 20 3,7
0
(C1)
BI1 MS VSS 8 3 20 8000 0.1

BI2 SL VSS 0 4.5 20

BI3 MS VSS 8 3 20

BI4 SL VSS 0 4.5 20

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 CFL-S Memory Interface White Paper

Table 3-6. CFL-S DDR4 Mixed SODIMM and Memory down x16 - Memory Down Routing
Guideline (Sheet 3 of 3)

Target Impedance Minimum Trace Spacing Maximum (mils)

(Ω) (mils) Length

Trace Width
Layer Route

R (Ω±1%)
Reference

Via Count
Region

(mils)

Notes
C(uF)
Signal

Byte [1 and
Tolerance

Breakout
Group[1
Group to

Region
and 2]
Group

Ended

Group
Single

Total
(%)
Diff

Diff

2]
Notes:
1. Avoid any parallel routing between two adjacent layers.
2. Signals, while routed on inner PCB layers must be ground referenced with solid ground floods on both sides.
3. Use individual termination resistors (R1) for each signal. Donot use Rpacks.
4. The Strobe and Data Group signals within the same byte must always route together on the same layers for their entire
route.
5. DQ Bit Swapping is allowed within the same byte, and Byte Swapping is allowed within the same channel.
6. Clock (CLK and CLK#) and Strobe (DQS and DQS#) differential signal swapping within a pair is not allowed.
7. Capacitor C1 is a defensive design and should have NO STUFF by default.
8. DQ and DQS signals must route at the same layer and have same width.
9. Route 2 adjacent bytes to same DRAM device, such as DRAM0(BYTE0,1) DRAM1 (BYTE 2,3), for better VREF training per
DRAM device.
10. Impedance numbers are for reference only, it is calculating according to the stackup layers thickness, the material
conductivity, traces spacing and width. The recommendation is to follow stackup and traces geometries.

Table 3-7. CFL-S DDR4 Mixed SODIMM and Memory down x16 - SODIMM Lengths
Matching Guidelines
Length Matching (mils)
Signal
Rule Details Notes
Group
Minimum Maximum

CK[X] - CK#[X], where X = 0 or 1 -5 5 1,2

CLK
1,2
CK/CK#[1:0] (max - min) 0 10
1,2
CTRL/CKE (max - min) 0 50
CTRL/CKE
CK/CK#[1:0] - CTRL/CKE -500 0 1,2

1,2
CMD (max - min) 0 100
CMD
1,2
CK/CK#[1:0] - CMD -500 500
1,2
DQS[X] - DQS#[X], where X = 0 to 7 -5 5
Strobe
1,2
CK/CK#[1:0] - DQS/DQS#[X], where X = 0 to 7 -1000 500

Data DQ (Byte[X]) - DQS/DQS#[X], where X = 0 to 7 -10 10 1,2,3

Notes:
1. Length Matching = CPU Die to SO-DIMM Pin (PKG+A+B+C+D+E); where a conversion factor of 0.9 must
be used on Micro-Strip Segments to convert Micro-Strip lengths to Strip-Line equivalent lengths. Keep the
DDR3L signal Die to SODIMM Total Lengths for each signal as short as possible.
2. To help facilitate and check the Length and Matching relationships on a design please reference the
Automated Trace Length Calculator (# 568458). Refer Table 1-2
3. Byte[0] = DQ[7:0], DQS/DQS#[0], Byte[1] = DQ[15:8], DQS/DQS#[1], Byte[2] = DQ[23:16], DQS/
DQS#[2], Byte[3] = DQ[31:24], DQS/DQS#[3], Byte[4] = DQ[39:32], DQS/DQS#[4], Byte[5] =
DQ[47:40], DQS/DQS#[5], Byte[6] = DQ[55:48], DQS/DQS#[6], Byte[7] = DQ[63:56], DQS/DQS#[7].

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Table 3-8. CFL-S DDR4 Mixed SODIMM and Memory down x16 - Memory Down Lengths
Matching Guidelines
Length Matching (mils)
Signal
Rule Details Notes
Group
Minimum Maximum
1,2
BI1 (max-min) 0 50

CLK CK[0] - CK#[0] -5 5 3,4

1,2
CK/CK#[0] (max - min) 0 10
2,7
BI1 (max-min) 0 0

CTRL/CKE CTRL/CKE (max - min) 0 50 1,2

1,2,6
CK/CK#[0] - CTRL/CKE -500 0
1,2,7
BI1 (max-min) 0 0

CMD CMD (max - min) 0 100 1,2

1,2,6
CK/CK#[0] - CMD -500 500
1,2,8
BI1 (max-min) 0 0

Strobe DQS[X] - DQS#[X], where X = 0 to 7 -5 5 1,2

1,2
CK/CK#[0] - DQS/DQS#[X], where X = 0 to 7 -1000 500
1,2,5
Data DQ (Byte[X]) - DQS/DQS#[X], where X = 0 to 7 -10 10

Notes:
1. Length Matching = CPU Die to SO-DIMM Pin (PKG+A+B+C+D+E); where a conversion factor of 0.9 must be
used on Micro-Strip Segments to convert Micro-Strip lengths to Strip-Line equivalent lengths. Keep the
DDR3L signal Die to SODIMM Total Lengths for each signal as short as possible.
2. To help facilitate and check the Length and Matching relationships on a design, refer the Memory Automated
Trace Length Calculator. Refer Table 1-2.
3. Length Matching = CPU Die to SO-DIMM Pin (PKG+A+B+C+D+E); where a conversion factor of 0.9 must be
used on Micro-Strip Segments to convert Micro-Strip lengths to Strip-Line equivalent lengths.
4. To help facilitate and check the Length and Matching relationships on a design, refer the Automated Trace
Length Calculator (# 568458). Refer Table 1-2.
5. Byte[0] = DQ[7:0], DQS/DQS#[0], Byte[1] = DQ[15:8], DQS/DQS#[1], Byte[2] = DQ[23:16], DQS/
DQS#[2], Byte[3] = DQ[31:24], DQS/DQS#[3], Byte[4] = DQ[39:32], DQS/DQS#[4], Byte[5] = DQ[47:40],
DQS/DQS#[5], Byte[6] = DQ[55:48], DQS/DQS#[6], Byte[7] = DQ[63:56], DQS/DQS#[7].
6. The delta between CLK signals to CMD/CTRL/CKE, between DRAMs should be kept < 20 mils. Example:
|DRAM[x] (CK[i]-Addr[j]) - DRAM[y](CK[i]-Addr[j])| < 20 mils.
7. This matching rule refer to all Break-ins (BI) sections that routed within each signal. Example: ADDR[0]
BI1 should be equal in all DRAMs. ADDR[1] BI1 should be equal in all DRAMs. ADDR[0] BI1 may not be
equal to ADDR[1] BI1.
8. DQ - BI should be matched within all bytes and not only within byte (max-min=0). DQ[63..0] BI section
should be equal. DQS - BI should be matched within all bytes and not only within bytes (max-min=0).
DQS[7..0][P/N] BI section should be equal. DQ and DQS BI does not need to be matched. Can allow 50
mils difference. DQS-DQ<=50 mils.

§§

573583 Intel Confidential 47

 CFL-S/H VREF/DM/ODT Guidelines

4 CFL-S/H VREF/DM/ODT
Guidelines

4.1 CFL-S and CFL-H System Memory ODT Signal

Connectivity Details
Table 4-1. ODT Signals Connectivity Table
Processor Memory type Side Signal Rule Notes

DDR4 SO-DIMM DDR0_ODT[3:0] Processor’s ODT[1:0]

1DPC Processor connected to DIMMs
DDR1_ODT[3:0]
ODTs. 1
DIMMs ODT[1:0] Processor’s ODT[3:2]
CFL-H not connected.

DDR4 SO-DIMM DDR0_ODT[3:0]

2DPC Processor Processor’s ODT[3:0]
DDR1_ODT[3:0] balls connected to 1
DIMMs ODTs.
DIMMs ODT[3:0]

DDR4 SO-DIMM DDR0_ODT[3:0] Processor’s ODT[1:0]

1DPC Processor connected to DRAMs’
DDR1_ODT[3:0]
ODTs.
DIMMs ODT[1:0] Processor’s ODT[3:2]
not connected.
CFL-S
DDR4 SO-DIMM DDR0_ODT[3:0]
2DPC Processor Processor’s ODT[3:0]
DDR1_ODT[3:0] connected to DRAMs’ 1
ODTs.
DIMMs ODT[3:0]

Notes:
1. For additional ODT signal connection details, refer to the Customer Reference Board (CRB) schematics
and board files.

4.2 Memory Data Mask (DM) Signals Connectivity

Details
Table 4-2. DIMMs/DRAMs DM Signals Connectivity Table
Memory Type DM Signals Connect to

DDR4 DIMMs DM[8:0] Tied to VDDQ

DIMMs

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CFL-S/H VREF/DM/ODT Guidelines

4.3 CFL H and CFL S System Memory Reference

Voltage (VREF) Guidelines
System memory reference voltages, VREF_DQ_A, VREF_DQ_B and VREF_CA must
meet the following guidelines:
• Follow the Customer Reference Board (CRB) board file and schematic
implementation, as closely as possible.
• The figures at this section show the VREF implementation block diagrams for all
supported platform configurations.
• Place the VREF voltage dividers as close as possible to the SO-DIMMs or memory
down DRAM devices.
• All VREF traces should be at least 20 mils wide with 20 mils spacing to other
signals/planes. Short violations are acceptable, if required due to tight routing
constraints.

Figure 4-1. CFL H/S DDR4 SO-DIMM VREF-CA Overview

CFL H/S
DDR0_VREF_DQ

DDR1_VREF_DQ DDR_VREF_CA

Channel A  VDDQ
VREF_CA
DDR4 SO‐DIMM
1K  2
Channel A  +/‐1%
+/‐1%

VREF_CA
DDR4 SO‐DIMM 22
1k
+/‐1%

VDDQ Channel B  25
+/‐5%
VREF_CA
DDR4 SO‐DIMM
2 1K 
+/‐1% +/‐1%
Channel B 
VREF_CA
22 DDR4 SO‐DIMM
1k
+/‐1%
Notes:
25 = Ohm
+/‐5%
= nF

Notes:
1. To enable easy route, at DDR4 systems, DDR1_VREF_DQ is used as VREF_CA for Channel B.

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 CFL-S/H VREF/DM/ODT Guidelines

Figure 4-2. CFL-H/S DDR4 x16 Memory Down VREF-CA Overview

CFL H/S
Notes:
DDR0_VREF_DQ
= Ohm +/‐ 1%
DDR1_VREF_DQ
= nF
DDR_VREF_CA
VDDQ

47 47 47 47
1.8k 2.7

VREF_CA VREF_CA VREF_CA VREF_CA 1.8k 22

25
ChA DRAM ChA DRAM ChA DRAM ChA DRAM

VDDQ

47
47 47 47 1.8k 2.7

VREF_CA VREF_CA VREF_CA 1.8k 22

VREF_CA
25
ChB DRAM ChB DRAM ChB DRAM ChB DRAM

Figure 4-3. CFL-H DDR4 x8 Memory Down VREF-CA Overview

CFL H
Notes: DDR0_VREF_DQ
= Ohm +/‐ 1%
DDR1_VREF_DQ
= nF
DDR_VREF_CA
VDDQ

47 47 47 47 47 47 47 47
1.8k 2.7

1.8k 22
VREF_CA VREF_CA VREF_CA VREF_CA VREF_CA VREF_CA VREF_CA VREF_CA
25
ChA  ChA  ChA  ChA  ChA  ChA  ChA  ChA 
DRAM7 DRAM6 DRAM5 DRAM4 DRAM3 DRAM2 DRAM1 DRAM0

VDDQ

1.8k 2.7
47 47 47 47 47 47 47 47

1.8k 22
VREF_CA VREF_CA VREF_CA VREF_CA VREF_CA VREF_CA VREF_CA VREF_CA
25
ChB  ChB  ChB  ChB  ChB  ChB  ChB  ChB 
DRAM7 DRAM6 DRAM5 DRAM4 DRAM3 DRAM2 DRAM1 DRAM0

Note: For 2Rx8, each DRAM should have its own cap (47 nF) - 16 caps per channel. In overall
32 caps.

§§

50 Intel Confidential 573583


Memory Interface Schematic Checklist

5 Memory Interface Schematic

Checklist

Check PDG schematic checklist for topologies that not covered in this section.

573583 Intel Confidential 51